CN1499581A - Method of flatting semiconductor die - Google Patents
Method of flatting semiconductor die Download PDFInfo
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- CN1499581A CN1499581A CNA2003101046146A CN200310104614A CN1499581A CN 1499581 A CN1499581 A CN 1499581A CN A2003101046146 A CNA2003101046146 A CN A2003101046146A CN 200310104614 A CN200310104614 A CN 200310104614A CN 1499581 A CN1499581 A CN 1499581A
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- material layer
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- top surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Abstract
A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a scribe line. A layer of silicon nitride is formed on the planar surface of the wafer where the silicon nitride has a top surface which is substantially parallel to the planar surface. A layer of silicon dioxide is deposited on the top surface with the silicon dioxide varying in height above the top surface. A mask is formed across the wafer, including on the scribe line, where the mask has a plurality of locations with each location having a differing density of gap-to-pillar ratio, which is proportional to the height of the silicon dioxide above the top surface. The silicon dioxide is anisotropically etched through each gap of the mask across the entire wafer where each gap is etched by the same amount in the height direction. CMP is then used to planarize the silicon dioxide to the top surface of the silicon nitride across the entire wafer.
Description
The priority that No. the 60/422nd, 314, the temporary transient application case that the request of the application's case was filed an application on October 29th, 2002, its disclosure is all incorporated into for your guidance at this.
Technical field
The present invention is relevant with the method for planarization one first material layer (more clearly saying so is a dielectric substance layer), and it is gone up at semiconductor tube core (die) and uses the chemical machinery grinding technique.
Background technology
Chemical machinery abrasive action (CMP) is a kind of well-known method that planarization one is used for the material of manufacture of semiconductor that is used for.Typically, this material of desiring to be flattened is the dielectric medium on other dielectric mediums that are deposited over silicon nitride for example of for example silicon dioxide.Further, to have a silicon dioxide be the plane, top that deposits thereon to this silicon nitride.Yet, because have irrigation canals and ditches and have hole in the silicon nitride that leads to these irrigation canals and ditches at this substrate, be deposited on silicon dioxide on the silicon nitride and will flow through these holes and flow in the irrigation canals and ditches in the substrate, thereby cause a uneven horizontal plane in the top plan of this silicon nitride.Therefore, the height at this silicon dioxide of the top plan of this silicon nitride is to change basically.In the CMP method, silicon dioxide needs to be ground or remove so that it is to become the plane with the top plan of this silicon nitride.
One attempts to flatten the method for the prior art of silicon dioxide, be to produce the artificial diffusion zone and it is filled with oxide in the substrate of big field domain, but this can't be used for big active region and overcome and the relevant CMP dish shape effect of active region greatly.In other words, this method itself can't overcome the problem with the planarization of wafer All Ranges.The settling mode of another kind of prior art is that the specific part of silicon dioxide is sheltered, and this part is the height of silicon dioxide that is higher than the top surface plane of silicon nitride basically.The masked portion of this silicon dioxide removes the part silicon dioxide in the sizable part of silicon dioxide height that is higher than the top surface plane substantially by this.Yet this can cause the well-known non-effect of desiring that is called as " dish shape (dishing) ", and wherein the abrasive action of this silicon dioxide can remove the silicon nitride in some zone.
At last, at one piece by Brian Lee, Duane S.Boning, the title that Dale L.Hetherington and David J.Stein published in CMP-MICconference in March, 2000 is in the article of " Using Smart Dummy Fill and SelectiveReverse Etch Back for Pattern Density Equalization ", the author has described a kind of emulation mask with density mode of specified arrangement, and remove silicon dioxide from those selected structure cells that eat-back with that, wherein this bottom layer silicon dioxide of some percentage is to be removed and is that density with this Marking film is inversely proportional to.Yet this technology is subject to the shortcoming that its silicon dioxide that does not comprise the entire wafer of crossing Semiconductor substrate comprises the silicon dioxide between the graticule that separates these tube cores.
Summary of the invention
Therefore, the present invention discloses the method for one first material of a kind of planarization on second material of semiconductor tube core.Several substantially the same semiconductor elements are to be defined at one to have on the semiconductor wafer on a plane.Several tube cores are separate with a graticule.One second material layer is to be formed on the plane of semiconductor wafer, this second material layer have one basically with this parallel plane top surface.One first material layer is to be positioned on the top surface, and this first material layer changes on the short transverse on this top surface.One mask crosses this wafer and forms, several positions are arranged in mask, each position is gone up variant with respect to the ratio (density of gap-to-pillar ratio) of the density in column district in the gap, it is proportional with first material height on this top surface.This first material is for anisotropically via each gap etching on entire wafer of mask, and wherein each gap is to come etching with same amount on short transverse.CMP is used on this entire wafer this first material of planarization then to this top surface.
Description of drawings
Fig. 1 is a top view of wafer, and several substantially the same semiconductor elements are defined on this wafer, and this wafer has one to be desired to come first material of planarization according to method of the present invention.
Fig. 2 is the phantom of a semiconductor element shown among Fig. 1, and it is illustrated in growth on the silicon nitride and the profile of the silicon dioxide desiring to be flattened.
Fig. 3 A is the top view for the employed mask of a kind of method of the present invention, and several column districts with different size are wherein arranged, and the gap between adjacent column district then all has identical size.
Fig. 3 B is the cutaway view that uses the mask pattern of shown mask in Fig. 3 A on the shown structure of Fig. 2.
Fig. 3 C is after applying mask and etching, a cutaway view of shown structure in Fig. 3 B.
The top view of the employed mask of Fig. 4 A another method of the present invention wherein has several column districts with same size, and the gap size between adjacent column district is then all inequality.
Fig. 4 B is the cutaway view that uses the mask pattern of mask shown among Fig. 4 A on the structure shown in Fig. 2.
Fig. 4 C be mask be applied in etching after, the cutaway view of shown structure in Fig. 4 B.
Embodiment
With reference to Fig. 1, it shows the top view of the wafer 10 of semi-conductive substrate.Typically, Semiconductor substrate 10 is that monocrystalline silicon or its can be composite semiconductors, for example the III-V material.This wafer 10 has defined several substantially the same semiconductor elements 12 thereon, and each tube core 12 is all separated by a mark line 14 each other.This wafer 10 has the feature of the top end surface 16 that is essentially the plane.In the present invention and known method, thin layer of silicon dioxide 20 be deposited or heat be grown in substrate 10 this top surface 16 on.Though be not inevitably, this thin layer of silicon dioxide 20 can be used for as the gate oxide of MOS transistor and its analog.Be deposited on the silicon dioxide of this ground floor 20 is silicon nitride layer 22.This silicon nitride has a plane 24, and it is parallel with the top surface 16 of Semiconductor substrate 10 basically.
Typically, irrigation canals and ditches 26 (a-c) are to be etched in the silicon nitride 22 and by silicon dioxide 20 to enter in the silicon substrate 10.At last, layer of silicon dioxide 28 is filled up irrigation canals and ditches 26 (a-c) and is deposited on the top on plane 24 of silicon nitride 22.In a concrete example, silicon dioxide layer 28 is to deposit with HDP (high-density plasma) deposition.This silicon dioxide 28 is to be deposited on the plane 24 of silicon nitride 22, and is deposited in the irrigation canals and ditches 26 (a-c), but can not form a plane parallel with plane 24.On the contrary, because silicon dioxide 28 " fills up " irrigation canals and ditches 26, the thickness of the silicon dioxide 28 on these silicon nitride 22 planes 24 will change.A typical cutaway view that in Fig. 2, shows tube core 12.In the method for the invention, this silicon dioxide 28 of planarization be so that resulting structure will be the plane, and be the top plan 24 of aiming at silicon nitride 22 be for desire.Be noted that silicon dioxide layer 20, silicon nitride layer 22 are to be applied to entire wafer 10 with silicon nitride layer 28, be included on the whole mark line 14.Certainly, as the irrigation canals and ditches shown in Fig. 2 26, this do not represent the layer 20 and 22 be present on substrate 10 top surfaces 16 everywhere in.
In the field domain that is denoted as " A ", the thickness or the quantity of the silicon dioxide 28 on the plane 24 of silicon nitride 22 are the thickness that is less than the silicon dioxide 28 in the zone that is denoted as " B " basically.This variation on silicon dioxide 28 thickness will make the column district that is formed on the silicon dioxide 28 with respect to the ratio of the density in gap opposite variation be arranged.Especially, in the less place of thickness, for example in regional A, the column district is bigger with respect to the ratio of the density in gap compared to area B, and the column district is less with respect to the ratio of the density in gap in that the thickness of area B place silicon dioxide 28 is big.
In order to determine silicon dioxide 28 or the thickness of the material of in each zones of different, desiring to be flattened, and thereby produce the required mask that has suitable column district size but have fixing gap size, people one of can two kinds of modes be determined.The first, the thickness in each zone can this expection thickness that stems from the irrigation canals and ditches number in this selection area be that calculate on the basis.For instance, because two irrigation canals and ditches 26a and 26b that the degree of depth is known are arranged in regional A, how many final thickness that can calculate this silicon dioxide 28 in regional A will be, because a part of silicon dioxide 28 in regional A can be used to fill up irrigation canals and ditches 26a and 26b, reduced the height of silicon dioxide 28 among the regional A by this.Similarly, for area B, this kind calculating also can irrigation canals and ditches 26c size, and will flow through and the silicon dioxide volume that fills up irrigation canals and ditches 26c calculates, and has reduced the height of the silicon dioxide 28 in this zone by this.Therefore, can use a computer to calculate the height or the thickness of the silicon dioxide 28 in various zoness of different, and therefore calculate the ratio of those regional column districts with respect to the density in gap.This computer must be understood the information that adds the thickness of upper strata 20 and 22 in the degree of depth that is used for pattern layout on the mask of trench etched and these irrigation canals and ditches.
Perhaps, this can scheme by the SEM (scanning electron microscopy) of hatch region after sedimentary deposit 28 that inspects selected tube core, and finds by experience.In case know above-mentioned main points, can determine need be with the layout of the field domain 30 of appropriate density for this method.Corresponding to column district density required after the anisotropic etching effect, some different column district layout patterns can be arranged.
Based on any one method wherein, be applied in after the entire wafer (it has the part resulting structures of tube core shown in Fig. 3 B) that comprises mark line 14 goes up at mask with several field domains 30, carry out an anisotropic etching effect.Be formed at silicon dioxide 28 between the gap between the adjacent column district 32 in the contour district of silicon dioxide 28 between the position by anisotropically etching.Each gap is the etched silicon dioxide 28 to same thickness value Y that enters.The structure of gained is as shown in Fig. 3 C.
At last, the wafer 10 with the structure as shown in Fig. 3 C carries out traditional CMP Ginding process then.As a result, after having the wafer 10 of the structure as shown in Fig. 3 C with the CMP processed, silicon dioxide 28 will arrive the plane 24 of this structure.
With reference to Fig. 4 A, it shows another kind of method of the present invention.In second method of the present invention, field domain 30 is consistent once more and is to be identical size.Yet the column district 32 of one or more same sizes is formed in each field domain 30, and the gap between each column district is different.Column district 30 can add the thickness of upper strata 20 and 22 according to " highly " of the silicon dioxide 28 that this field domain was fixed thereon and have different with the density in gap.One wherein field domain 30 be that the mask that is set at the contour district of silicon dioxide 28 is formed once more, and cause many wherein in this field domain each zone be for the column district of unanimity be the formation in different zone with respect to the ratio in gap.
The explanation of the method that the similar aforesaid structure shown with being used for processing and manufacturing Fig. 3 B is relevant, after field domain 30 formed in the contour district of silicon dioxide 28, the silicon dioxide 28 between adjacent column district or in the gap was by anisotropically etching.Again, the method for describing with reference Fig. 3 C similarly, this silicon dioxide 28 be on " highly " direction by the identical numerical value Y of etching anisotropically, and obtain as the structure as shown among Fig. 4 C.Shown structure is ground by CMP and resulting structure will be to be silicon dioxide 28 for the plane with respect to the plane 24 of silicon nitride 22 basically then among Fig. 4 C.
Theory of the present invention is as described below: when applying the mask that its column district is inversely proportional to respect to the ratio of a gap density and silicon dioxide 26 " highly ", CMP grinding steps afterwards will make those have more low-density field domain compared with have highdensity field domain etched or grind faster.This has the low-density field domain and represents field domain on the thick part of those silicon dioxide.Therefore, those zones will be that the zone of " approaching " is faster than silicon dioxide etchedly.Further abrasive action can finally bring to these two parts identical plane field domain.
Number reason goes up ground, and this may represent with the following methods: in having the CMP processing method of certain surface texture that density is D, this etch-rate is to be R/D, and wherein R is the etch-rate on plane.Density D is to equal the gross area of high feature structure and (gross area in column district 32) divided by the gross area (field domain area) or (gross area in the gross area 32+ gap in column district).Therefore, density D will always be less than or equal 1.0.If density is low, also just represent the column district less, etch-rate will come soon by the specific density height so.Because the mask density on the thicker silicon dioxide field domain of the low representative of the density field domain thinner than silicon dioxide, this thicker zone is will etched ground faster.
Various specific embodiments can form not undermining under the spirit of the present invention.In particular, the size of field domain can be miniature sizes, 50um * 50um for instance.
[the main element conventional letter table among the figure]
10 semiconductor wafers, 24 silicon nitride planes
12 semiconductor element 26 (a-c) irrigation canals and ditches
14 mark lines, 28 silica
16 top end surfaces, 30 field domains
20 thin layer of silicon oxide, 32 column districts
22 silicon nitride layers
Claims (15)
1. the method for chemical machinery grinding (CMP) first material on second material of semiconductor element, it comprises:
At a semiconductor wafer upper bound fixed number substantially the same semi-conductive tube core, this wafer has a plane, and wherein these several tube cores are separate with a mark line;
Form one second material layer on this plane, wherein this second material layer has a top surface that is arranged essentially parallel to this plane;
Form one first material layer on this top surface, wherein this first material layer is vicissitudinous on the short transverse on the top surface;
Form a mask that crosses this wafer, wherein this mask has several positions, and each position all has different gaps with respect to column district density ratio, and this ratio is proportional with the height of first material on this top surface;
Anisotropically pass through this first material of each gap etching entire wafer of this mask, wherein etching is come with equal number in each gap on short transverse; And
Use CMP to be used for first material of planarization entire wafer to top surface.
2. method as claimed in claim 1, wherein this second material layer is a silicon nitride, and wherein this first material layer is a silicon dioxide.
3. method as claimed in claim 1, it further comprises the 3rd material layer between this second material layer and this wafer.
4. method as claimed in claim 3, wherein this second material layer is a silicon nitride, and wherein this first material layer is a silicon dioxide with the 3rd material layer.
5. method as claimed in claim 4 wherein has the hole that connects first material layer and the 3rd material among this second material layer.
6. method as claimed in claim 5, wherein each this tube core all has the irrigation canals and ditches that filled up by this first material layer therein.
7. method as claimed in claim 6, wherein this gap comprises several consistent basically field domains with respect to the density in column district, but each field domain has the different gap of size, column district of identical size.
8. method as claimed in claim 6, wherein this gap comprises several consistent basically field domains with respect to the density in column district, and the column district that each field domain is of different sizes is measure-alike gap still.
9. method as claimed in claim 1, wherein this gap comprises several consistent basically field domains with respect to the density in column district, but each field domain has the different gap of size, column district of identical size.
10. method as claimed in claim 1, wherein this gap comprises several consistent basically field domains with respect to the density in column district, and the column district that each field domain is of different sizes is measure-alike gap still.
11. the method for planarization first material on second material of semiconductor element, it comprises:
At a semiconductor wafer upper bound fixed number substantially the same semi-conductive tube core, this wafer has a plane, and wherein these several tube cores are separate with a mark line;
On this plane, form one the 3rd material layer;
Form one second material layer on the 3rd material layer, this second material layer has a top surface that is arranged essentially parallel to this plane;
Shelter the selected part of this second material layer, and make that other second material layer part is not masked;
This second material layer of etching, this first material layer and this semiconductor wafer, with via these other not masked portion form irrigation canals and ditches therein;
Apply this first material layer in being included in these irrigation canals and ditches and on this wafer on this second material, wherein this first material layer is to change in the short transverse on top surface;
Form a mask on entire wafer, wherein this mask has several positions, and each position all has different gaps with respect to column district density ratio, and this ratio is proportional apart from first quantity of material of top surface on short transverse with in this position;
Anisotropically pass through this first material of each gap etching entire wafer of this mask, wherein etching is come with equal number in each gap on short transverse; And
Use the CMP method to come first material of planarization entire wafer to top surface.
12. as the method for claim 11, wherein masking steps further comprises:
Form one and hide the selected part of this second material layer and the not masked mask of other parts; And
After etching step, remove mask.
13. as the method for claim 12, wherein this first material and the 3rd material are silicon dioxide, and this second material is a silicon nitride.
14. as the method for claim 12, wherein this gap comprises several consistent basically field domains with respect to the density in column district, but each field domain has the different gap of size, column district of identical size.
15. as the method for claim 12, wherein this gap comprises several consistent basically field domains with respect to the density in column district, the column district that each field domain is of different sizes is measure-alike gap still.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US42231402P | 2002-10-29 | 2002-10-29 | |
| US60/422314 | 2002-10-29 | ||
| US10/423270 | 2003-04-25 | ||
| US10/423,270 US6703318B1 (en) | 2002-10-29 | 2003-04-25 | Method of planarizing a semiconductor die |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1499581A true CN1499581A (en) | 2004-05-26 |
| CN100416770C CN100416770C (en) | 2008-09-03 |
Family
ID=31891557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101046146A Expired - Fee Related CN100416770C (en) | 2002-10-29 | 2003-10-29 | Method of flatting semiconductor die |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6703318B1 (en) |
| EP (1) | EP1416524A3 (en) |
| JP (1) | JP4573515B2 (en) |
| KR (1) | KR20040038788A (en) |
| CN (1) | CN100416770C (en) |
| TW (1) | TWI320584B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103854967A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7522091B2 (en) * | 2002-07-15 | 2009-04-21 | Automotive Systems Laboratory, Inc. | Road curvature estimation system |
| WO2009029302A2 (en) * | 2007-05-08 | 2009-03-05 | University Of Washington | Shadow edge lithography for nanoscale patterning and manufacturing |
| KR100848461B1 (en) * | 2007-08-16 | 2008-07-25 | 주식회사 동부하이텍 | Method of manufacturing semiconductor device |
| JP4968228B2 (en) * | 2007-11-07 | 2012-07-04 | マツダ株式会社 | Engine superstructure |
| US8551886B2 (en) * | 2007-12-28 | 2013-10-08 | Texas Instruments Incorporated | CMP process for processing STI on two distinct silicon planes |
| JP5356742B2 (en) * | 2008-07-10 | 2013-12-04 | ラピスセミコンダクタ株式会社 | Semiconductor device, semiconductor device manufacturing method, and semiconductor package manufacturing method |
| US8129095B2 (en) | 2009-04-08 | 2012-03-06 | International Business Machines Corporation | Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance |
| US9853149B1 (en) * | 2016-10-03 | 2017-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Floating grid and crown-shaping poly for improving ILD CMP dishing |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5928960A (en) * | 1996-10-24 | 1999-07-27 | International Business Machines Corporation | Process for reducing pattern factor effects in CMP planarization |
| EP0855739A1 (en) * | 1997-01-24 | 1998-07-29 | Texas Instruments Inc. | Tapered dielectric etch process for moat etchback |
| US6025270A (en) * | 1997-02-03 | 2000-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarization process using tailored etchback and CMP |
| US5911110A (en) * | 1997-10-28 | 1999-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming shallow trench isolation with dummy pattern in reverse tone mask |
| JP3279276B2 (en) * | 1999-01-27 | 2002-04-30 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2001044168A (en) * | 1999-07-30 | 2001-02-16 | Matsushita Electronics Industry Corp | Manufacture of semiconductor device |
| JP4370484B2 (en) * | 1999-08-16 | 2009-11-25 | エルピーダメモリ株式会社 | Manufacturing method of semiconductor device |
| JP4347960B2 (en) * | 1999-09-14 | 2009-10-21 | 株式会社ディスコ | Dicing method |
| JP3344397B2 (en) * | 2000-01-21 | 2002-11-11 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP2001326199A (en) * | 2000-05-17 | 2001-11-22 | Hitachi Ltd | Manufacturing method of semiconductor integrated circuit device |
| JP2002026199A (en) * | 2000-07-06 | 2002-01-25 | Nakamura Seisakusho Kk | Forming method of heat dissipating member for electronic component |
| JP2002026119A (en) * | 2000-07-10 | 2002-01-25 | Sharp Corp | Method of manufacturing semiconductor device |
| JP2002270769A (en) * | 2001-03-08 | 2002-09-20 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP2002270688A (en) * | 2001-03-09 | 2002-09-20 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| US6541324B1 (en) | 2001-11-02 | 2003-04-01 | Silicon Storage Technology, Inc. | Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region |
-
2003
- 2003-04-25 US US10/423,270 patent/US6703318B1/en not_active Expired - Lifetime
- 2003-10-23 TW TW092129461A patent/TWI320584B/en not_active IP Right Cessation
- 2003-10-29 KR KR1020030075909A patent/KR20040038788A/en not_active Application Discontinuation
- 2003-10-29 JP JP2003368772A patent/JP4573515B2/en not_active Expired - Fee Related
- 2003-10-29 CN CNB2003101046146A patent/CN100416770C/en not_active Expired - Fee Related
- 2003-10-29 EP EP03256830A patent/EP1416524A3/en not_active Withdrawn
-
2004
- 2004-01-21 US US10/762,807 patent/US6969687B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103854967A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854967B (en) * | 2012-11-30 | 2017-09-22 | 中国科学院微电子研究所 | Planarization process method |
Also Published As
| Publication number | Publication date |
|---|---|
| US6703318B1 (en) | 2004-03-09 |
| JP4573515B2 (en) | 2010-11-04 |
| TWI320584B (en) | 2010-02-11 |
| EP1416524A3 (en) | 2005-09-21 |
| TW200415719A (en) | 2004-08-16 |
| JP2004153276A (en) | 2004-05-27 |
| KR20040038788A (en) | 2004-05-08 |
| CN100416770C (en) | 2008-09-03 |
| US6969687B2 (en) | 2005-11-29 |
| US20040152397A1 (en) | 2004-08-05 |
| EP1416524A2 (en) | 2004-05-06 |
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