CN111403484A - PMOS semiconductor device and preparation method thereof - Google Patents
PMOS semiconductor device and preparation method thereof Download PDFInfo
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- CN111403484A CN111403484A CN202010213182.6A CN202010213182A CN111403484A CN 111403484 A CN111403484 A CN 111403484A CN 202010213182 A CN202010213182 A CN 202010213182A CN 111403484 A CN111403484 A CN 111403484A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 238000000034 method Methods 0.000 claims abstract description 23
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 13
- 239000000969 carrier Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Abstract
The invention provides a PMOS semiconductor device and a preparation method thereof.A mask layer covers a semiconductor substrate and is patterned, and the semiconductor substrate is etched to form a groove; depositing a dielectric layer in the groove, and filling the groove to form a gate; covering a layer of nitride etching semiconductor substrate, forming epitaxial regions with regular hexagonal longitudinal sections on two sides of the grid, wherein the upper surfaces of the epitaxial regions are flush with the upper surface of the semiconductor substrate; forming an epitaxial layer in the epitaxial region; removing the mask layer and the nitride, and exposing a part of the grid electrode on the upper surface of the semiconductor substrate; and forming side walls on two sides of the exposed grid. The embedded grid structure is adopted, so that the bottom channel of the grid and the sharp-corner stress maximum point of the SiGe regular hexagonal section are positioned on the same plane, the mobility of a channel carrier is improved, and the performance of a device is improved. Meanwhile, compared with the traditional process, the invention omits the process flows of manufacturing the polycrystalline silicon pseudo grid and removing the pseudo grid, simplifies the process steps and reduces the production cost.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a PMOS (P-channel metal oxide semiconductor) semiconductor device and a preparation method thereof.
Background
With the development of integrated circuits, the field effect size is smaller and smaller, and a stress technology is introduced in the semiconductor manufacturing process to change the lattice structure in a channel, so that the mobility of carriers in the channel is improved; from the prior research, it is observed that the electron mobility is improved by applying tensile stress to the channel, and the hole mobility is improved by applying compressive stress. The embedded SiGe technology is widely applied to improve the performance of the PMOS, and the embedded SiGe technology can apply compressive stress to the channel region by embedding SiGe materials in the source region and the drain region of the PMOS, so that the performance of the PMOS is significantly improved. Generally, the greater the stress, the higher the mobility enhancement of the channel carriers. However, in conventional processes, the PMOS channel is not in the most stressed region of SiGe.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a PMOS semiconductor device and a method for fabricating the same, which can solve the problem in the prior art that the PMOS channel is not located in the SiGe most stressed region.
To achieve the above and other related objects, the present invention provides a PMOS semiconductor device, comprising at least: a semiconductor substrate; two epitaxial layers embedded in the semiconductor substrate and spaced from each other; the longitudinal section of the epitaxial layer is in a regular hexagon shape, and the upper surface of the epitaxial layer is flush with the upper surface of the semiconductor substrate;
a gate electrode positioned on the semiconductor substrate and between the two epitaxial layers, wherein one part of the gate electrode is positioned in the semiconductor substrate, and the other part of the gate electrode protrudes out of the upper surface of the semiconductor substrate;
the gate side wall and the bottom are provided with dielectric layers, wherein the dielectric layers on the gate side wall and the bottom in the semiconductor substrate are directly contacted with the semiconductor substrate;
and the grid part protrudes out of the upper surface of the semiconductor substrate, and the dielectric layer on the side wall of the grid part is provided with a side wall.
Preferably, the semiconductor substrate is single crystal silicon.
Preferably, the top angle of the epitaxial layer between the upper surface and the lower surface of the semiconductor substrate is at the same height as the lower surface of the dielectric layer at the bottom of the gate.
Preferably, the epitaxial layer is a SiGe material.
Preferably, the gate comprises at least one of TIN, TaN or a L.
Preferably, the dielectric layer is HfO 2.
The invention also provides a preparation method of the PMOS semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and covering a mask layer on the semiconductor substrate;
patterning the mask layer, and etching the semiconductor substrate according to the patterned mask layer to form a groove;
depositing a dielectric layer covering the side wall and the bottom of the groove in the groove, filling the groove with metal to form a gate, and flattening the surface of the semiconductor;
covering a layer of nitride on the surface of the semiconductor to be used as a hard mask, etching the semiconductor substrate, and forming an epitaxial region with a regular hexagonal longitudinal section on the semiconductor substrate on two sides of the grid, wherein the upper surface of the epitaxial region is flush with the upper surface of the semiconductor substrate;
growing SiGe epitaxially in the epitaxial region to form an epitaxial layer;
sixthly, removing the mask layer and the nitride on the semiconductor substrate, and exposing a part of the grid to the upper surface of the semiconductor substrate;
and step seven, forming side walls on two sides of the exposed grid electrode.
Preferably, the mask layer in the first step is at least one of silicon nitride and silicon oxide.
Preferably, the method for depositing the dielectric layer in step three is an atomic layer deposition method.
Preferably, the method for filling the groove to form the gate in the third step is physical vapor deposition or atomic layer deposition.
Preferably, the nitride in step four is silicon nitride.
Preferably, the step four of etching the semiconductor substrate to form the epitaxial region includes the steps of: 1. patterning the nitride; 2. etching the mask layer and the semiconductor substrate in sequence according to the nitride pattern, and forming recessed regions on two sides of the grid on the semiconductor substrate; 3. and performing secondary etching to form the epitaxial region with the vertical section of a regular hexagon.
Preferably, in the fourth step, the vertical section of the epitaxial region is a regular hexagon, and a vertex angle between the upper surface and the lower surface of the epitaxial region is at the same height as the lower surface of the dielectric layer at the bottom of the gate.
As described above, the PMOS semiconductor device and the method for manufacturing the same of the present invention have the following advantageous effects: the embedded grid structure is adopted, so that the bottom channel of the grid and the sharp-corner stress maximum point of the SiGe regular hexagonal section are positioned on the same plane, the mobility of a channel carrier is improved, and the performance of a device is improved. Meanwhile, compared with the traditional process, the invention omits the process flows of manufacturing the polycrystalline silicon pseudo grid and removing the pseudo grid, simplifies the process steps and reduces the production cost.
Drawings
FIG. 1 is a schematic structural diagram of a semiconductor substrate covered with a patterned mask layer for forming a recess according to the present invention;
FIG. 2 is a schematic diagram of the structure of the present invention after forming a dielectric layer and a gate in the recess;
FIG. 3 is a schematic view of a semiconductor substrate having a nitride layer formed thereon according to the present invention;
FIG. 4 is a schematic diagram illustrating a structure of a semiconductor substrate after forming a recess region thereon;
FIG. 5 is a schematic structural view of the second etching of the recessed region to form an epitaxial region;
FIG. 6 is a schematic structural diagram of the present invention after an epitaxial layer is grown in the epitaxial region;
FIG. 7 is a schematic diagram of the structure of the present invention after removing the remaining mask layer and nitride on the semiconductor substrate;
FIG. 8 is a schematic diagram of a PMOS semiconductor device according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a PMOS semiconductor device, as shown in fig. 8, fig. 8 is a schematic structural diagram of the PMOS semiconductor device of the present invention. The device comprises at least: a semiconductor substrate 02; two epitaxial layers 09 embedded in the semiconductor substrate 02 and spaced from each other; the longitudinal section of the epitaxial layer 09 is in a regular hexagon shape, and the upper surface of the epitaxial layer 09 is flush with the upper surface of the semiconductor substrate 02; in fig. 8, the epitaxial layer 09 is disposed in the semiconductor substrate, and the upper surface of the epitaxial layer is flush with the upper surface of the semiconductor substrate, that is, the longitudinal section (cross section) of the epitaxial layer is a regular hexagon, so that, as can be seen in fig. 8, one side of the upper surface of the regular hexagon is flush with the upper surface of the semiconductor substrate, that is, the upper surface of the epitaxial layer is flush with the upper surface of the semiconductor substrate.
A gate 05 located on the semiconductor substrate 02 and between the two epitaxial layers 09, wherein one part of the gate 05 is located in the semiconductor substrate 02, and the other part of the gate 05 protrudes out of the upper surface of the semiconductor substrate 02; that is, the gate is located between the two epitaxial layers on the semiconductor substrate, as can be seen from fig. 8, the gate is partially located inside the semiconductor substrate, and the other part protrudes above the semiconductor substrate.
The side wall and the bottom of the gate 05 are provided with dielectric layers 04, wherein the dielectric layers 04 on the side wall and the bottom of the gate 05 in the semiconductor substrate 02 are directly contacted with the semiconductor substrate 02; the dielectric layer 04 is HfO 2. As shown in fig. 8, since a part of the sidewall of the gate 05 is located in the semiconductor substrate, and the bottom thereof is also located in the semiconductor substrate, a layer of the dielectric layer 04 is also present between the bottom of the gate in the semiconductor substrate and the semiconductor substrate, and a layer of the dielectric layer 04 is also present between the sidewall of the gate in the semiconductor substrate and the semiconductor substrate. The dielectric layer 04 is also disposed on the sidewall of the gate protruding above the semiconductor substrate.
Further, the semiconductor substrate 02 is single crystal silicon. The vertex angle of the epitaxial layer 09 between the upper and lower surfaces in the semiconductor substrate 02 is at the same height as the lower surface of the dielectric layer 04 at the bottom of the gate 05. Further, the shapes and the sizes of the two epitaxial layers in the semiconductor substrate are consistent, so that the height corresponding to the connecting line of the top angles between the upper surface and the lower surface of the two epitaxial layers is the height of the lower surface of the dielectric layer 04 at the bottom of the gate, and therefore the height corresponding to the top angle between the upper surface and the lower surface of the epitaxial layers is consistent with the height of the lower surface of the dielectric layer 04 at the bottom of the gate.
The epitaxial layer 09 is a SiGe material, the gate 05 comprises at least one of TIN, TaN or A L in the present embodiment, the gate 05 is TIN, and in other embodiments, can be TaN or A L, or a combination of TIN, TaN and A L.
And a side wall 10 is arranged on the dielectric layer 04 at the part of the gate 05 protruding out of the upper surface of the semiconductor substrate 02.
The invention also provides a preparation method of the PMOS semiconductor device, which comprises the following steps:
providing a semiconductor substrate, and covering a mask layer on the semiconductor substrate; the mask layer in the first step is at least one of silicon nitride and silicon oxide. In this embodiment, the mask layer is a combination of silicon nitride and silicon oxide.
Step two, as shown in fig. 1, fig. 1 shows a schematic structural diagram of a patterned mask layer covering a semiconductor substrate on which a groove is formed in the present invention; in the step, the mask layer 01 is patterned, and the semiconductor substrate 02 is etched according to the patterned mask layer 01 to form a groove 03; in this step, the groove 03 is formed by etching according to the patterned mask layer 01, so that the groove and the patterned mask layer are through.
Step three, as shown in fig. 2, fig. 2 is a schematic structural diagram after a dielectric layer and a gate are formed in the groove in the present invention; firstly, depositing a dielectric layer 04 covering the side wall and the bottom of the groove 03 in the groove 03, then filling the groove with metal to form a gate 05, and flattening the surface of the semiconductor; since the deposited dielectric layer 04 only covers the bottom and sidewalls of the recess and does not fill the recess, metal is then deposited on the dielectric layer 04 to form the gate 05, and since the deposited metal fills the recess, a portion of the metal will tend to be deposited on the upper surface of the recess, and therefore this step requires a planarization step to planarize the raised metal portion to form the structure shown in fig. 2.
Further, the method for depositing the dielectric layer 04 in the third step is an atomic layer deposition method. Still further, the method for filling the groove to form the gate 05 in the third step is physical vapor deposition or atomic layer deposition.
Step four, as shown in fig. 3 (fig. 3 shows a schematic structural diagram after a layer of nitride is formed on the surface of the semiconductor substrate in the present invention), covering a layer of nitride 06 on the surface of the semiconductor substrate as a hard mask, etching the semiconductor substrate 02, forming an epitaxial region 08 with a regular hexagon in longitudinal section on the semiconductor substrate 02 at two sides of the gate 05, wherein the upper surface of the epitaxial region 08 is flush with the upper surface of the semiconductor substrate 02; the nitride in step four is silicon nitride.
The fourth step of etching the semiconductor substrate 02 to form the epitaxial region 08 includes the following steps: 1. patterning the nitride; 2. sequentially etching the mask layer 01 and the semiconductor substrate 02 according to the nitride pattern, and forming recessed regions on the semiconductor substrate 02 at two sides of the gate 05 (as shown in fig. 4, fig. 4 is a schematic structural diagram after the recessed regions are formed on the semiconductor substrate); 3. and performing secondary etching to form the epitaxial region 08 with a regular hexagon in longitudinal section (as shown in fig. 5, fig. 5 is a schematic structural diagram after the epitaxial region is formed by performing secondary etching on the recessed region).
In the fourth step, the vertical section of the epitaxial region is a regular hexagon, and the vertex angle between the upper surface and the lower surface of the epitaxial region is at the same height as the lower surface of the dielectric layer 04 at the bottom of the gate 05. The two epitaxial layers have the same shape and size in the semiconductor substrate, and therefore, the height corresponding to the connection line of the top corner between the upper surface and the lower surface of the two epitaxial layers is the height of the lower surface of the dielectric layer 04 at the bottom of the gate (as shown in fig. 5).
Step five, epitaxially growing SiGe in the epitaxial region 08 to form an epitaxial layer 09; this step uses an epitaxial growth method to grow SiGe in the epitaxial region 08 of said fig. 5, as shown in fig. 6, after which the structure shown in fig. 6 is formed. Fig. 6 is a schematic structural diagram of the epitaxial layer formed in the epitaxial region.
Sixthly, removing the mask layer 01 and the nitride on the semiconductor substrate 02, and exposing a part of the grid 05 to the upper surface of the semiconductor substrate 02; as shown in fig. 7, fig. 7 is a schematic structural view of the semiconductor substrate after removing the remaining mask layer and nitride layer. The mask layer 01 on the semiconductor substrate 02 and the nitride 06 on the mask layer 01 in fig. 6 are completely removed, resulting in the structure shown in fig. 7.
And step seven, forming side walls 10 on two sides of the exposed grid electrode 05. In fig. 7, after the mask layer 01 and the nitride 06 on the mask layer 01 are removed, the dielectric layer 04 on a part of the gate and a part of the sidewall thereof is exposed, and in this step, the sidewall spacer 10 is formed on the outer sidewall of the exposed dielectric layer 04 on the sidewall of the gate. The structure for forming the PMOS semiconductor device according to the present invention is shown in fig. 8.
In conclusion, the embedded gate structure is adopted, so that the bottom channel of the gate and the sharp-corner stress maximum point of the SiGe regular hexagonal cross section are positioned on the same plane, the mobility of channel carriers is improved, and the device performance is improved. Meanwhile, compared with the traditional process, the invention omits the process flows of manufacturing the polycrystalline silicon pseudo grid and removing the pseudo grid, simplifies the process steps and reduces the production cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (13)
1. A PMOS semiconductor device, comprising at least:
a semiconductor substrate; two epitaxial layers embedded in the semiconductor substrate and spaced from each other; the longitudinal section of the epitaxial layer is in a regular hexagon shape, and the upper surface of the epitaxial layer is flush with the upper surface of the semiconductor substrate;
a gate electrode positioned on the semiconductor substrate and between the two epitaxial layers, wherein one part of the gate electrode is positioned in the semiconductor substrate, and the other part of the gate electrode protrudes out of the upper surface of the semiconductor substrate;
the gate side wall and the bottom are provided with dielectric layers, wherein the dielectric layers on the gate side wall and the bottom in the semiconductor substrate are directly contacted with the semiconductor substrate;
and the grid part protrudes out of the upper surface of the semiconductor substrate, and the dielectric layer on the side wall of the grid part is provided with a side wall.
2. The PMOS semiconductor device of claim 1, wherein: the semiconductor substrate is monocrystalline silicon.
3. The PMOS semiconductor device of claim 1, wherein: the top angle of the epitaxial layer between the upper surface and the lower surface of the semiconductor substrate is at the same height with the lower surface of the dielectric layer at the bottom of the grid.
4. The PMOS semiconductor device of claim 1, wherein: the epitaxial layer is made of SiGe material.
5. The PMOS semiconductor device of claim 1, wherein the gate comprises at least one of TIN, TaN, or A L.
6. The PMOS semiconductor device of claim 1, wherein: the dielectric layer is HfO 2.
7. The method for manufacturing a PMOS semiconductor device according to claims 1 to 6, comprising the steps of:
providing a semiconductor substrate, and covering a mask layer on the semiconductor substrate;
patterning the mask layer, and etching the semiconductor substrate according to the patterned mask layer to form a groove;
depositing a dielectric layer covering the side wall and the bottom of the groove in the groove, filling the groove with metal to form a gate, and flattening the surface of the semiconductor;
covering a layer of nitride on the surface of the semiconductor to be used as a hard mask, etching the semiconductor substrate, and forming an epitaxial region with a regular hexagonal longitudinal section on the semiconductor substrate on two sides of the grid, wherein the upper surface of the epitaxial region is flush with the upper surface of the semiconductor substrate;
growing SiGe epitaxially in the epitaxial region to form an epitaxial layer;
sixthly, removing the mask layer and the nitride on the semiconductor substrate, and exposing a part of the grid to the upper surface of the semiconductor substrate;
and step seven, forming side walls on two sides of the exposed grid electrode.
8. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: the mask layer in the first step is at least one of silicon nitride and silicon oxide.
9. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: the method for depositing the dielectric layer in the third step is an atomic layer deposition method.
10. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: and in the third step, the method for filling the groove to form the grid is physical vapor deposition or atomic layer deposition.
11. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: the nitride in step four is silicon nitride.
12. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: the fourth step of etching the semiconductor substrate to form the epitaxial region comprises the following steps: 1. patterning the nitride; 2. etching the mask layer and the semiconductor substrate in sequence according to the nitride pattern, and forming recessed regions on two sides of the grid on the semiconductor substrate; 3. and performing secondary etching to form the epitaxial region with the vertical section of a regular hexagon.
13. The method of manufacturing a PMOS semiconductor device according to claim 1, wherein: in the fourth step, the vertical section of the epitaxial region is a regular hexagon, and the vertex angle between the upper surface and the lower surface of the epitaxial region is at the same height as the lower surface of the dielectric layer at the bottom of the gate.
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| CN113643980A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Semiconductor device and forming method thereof |
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| CN106653751A (en) * | 2015-11-04 | 2017-05-10 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacturing method thereof |
| CN110400845A (en) * | 2019-07-30 | 2019-11-01 | 上海华力集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113643980A (en) * | 2021-07-27 | 2021-11-12 | 上海华力集成电路制造有限公司 | Semiconductor device and forming method thereof |
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