CN1485971A - High precision low power dissipation charge pump circuit - Google Patents
High precision low power dissipation charge pump circuit Download PDFInfo
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Abstract
The invention is a high-precision low-power charge pump circuit. Its character: it connects a coupled capacity controller between the clock module and the coupled capacity, the control signal coming from the comparer's output end, the controller equivalent to a variable resistance whose value varies with the change of the comparer's output voltage. The resistance value's change makes the charge-discharge speed of the coupled capacity change accordingly. It also adopts coupled capacity separating method not to make the charge pump in the stop state, able to keep the output voltage stable.
Description
Technical field:
The high-precision low-power consumption charge pump circuit belongs to technical field of analog integrated circuit design, refers more particularly to the design field of non-volatility memorizer mesohigh charge pump circuit.
Background technology:
Charge pump is that a kind of can the generation is higher than supply voltage V
DDThe circuit of positive high voltage.It is widely used in the various non-volatile type memories, to realize the programming and the erase operation of memory cell.
Fig. 1 is traditional Diekson type positive high voltage charge pump schematic diagram.It is made up of NMOS pipe MN1-MN5 and coupling capacitance C1-C4.Wherein source end and the drain terminal of NMOS pipe MN1-MN5 are contacted one by one, and finally are connected supply voltage V
DDAnd between the high-voltage output end VP, and the drain terminal that the grid of MN1-MN5 all is connected to separately forms diode, and their substrate all is connected to ground Gnd.The end of coupling capacitance C1-C4 all is connected on two-phase non-overlapping clock signal CLK1 or the CLK2, and wherein the end of coupling capacitance C1 and C3 is connected on the clock signal clk 1, and the end of coupling capacitance C2 and C4 is connected on the clock signal clk 2.The other end of coupling capacitance C1-C4 is connected respectively to the source end of NMOS pipe MN1-MN4.
Fig. 2 is the sequential chart of two-phase non-overlapping clock signal CLK1 and CLK2.CLK1 and CLK2 are square-wave signals, and their phase place is opposite, and at supply voltage V
DDAnd saltus step between the ground Gnd.When clock signal CLK1 is low, and CLK2 is when being high, and NMOS pipe MN1 is in conducting state owing to grid voltage is higher than source end (P1) voltage, and coupling capacitance C1 will be charged to supply voltage V like this
DDDeduct the threshold voltage V of NMOS pipe MN1
TWhen CLK1 become height and CLK2 when low, the drain terminal voltage (P1) of MN2 will be coupled capacitor C 1 and be coupled to 2V
DD-V
T, and this moment NMOS pipe MN1 turn-off and MN2 with conducting, coupling capacitance C2 will be charged to 2V like this
DD-2V
TWhen clock signal CLK1 becomes low and CLK2 becomes when high once more, drain terminal (P2) voltage of NMOS pipe MN3 will be coupled capacitor C 2 and be coupled to 3V
DD-2V
T, and this moment NMOS pipe MN2 turn-off and MN3 with conducting, coupling capacitance C3 will be charged to 3V like this
DD-3V
TSuch charging process continues always, and it is maximum that the voltage of output VP will reach, and its concrete numerical value can be expressed as (N+1) * (V
DD-V
T), wherein N represents the progression of positive high voltage charge pump.
Because the output high pressure that charge pump produces can be subjected to serving as a contrast the influence of factors such as inclined to one side effect and process deviation, especially under the bigger situation of load current, its fluctuation is general bigger, needs all that in actual applications it is carried out voltage stabilizing and regulates, to obtain high-precision output.As shown in Figure 3 to be a kind of tradition carry out the method that voltage stabilizing is regulated to the output high pressure, under the driving of two-phase non-overlapping clock CLK1 as shown in Figure 2 that clock generating module produces and CLK2, charge pump work also produces high pressure VP, sampling by two sampling capacitance C1 and C2, obtain a sampled voltage V1, V1 and reference voltage Vref 1 are input to positive and the negative-phase input of comparator U1 respectively, if output high pressure VP is greater than predetermined value, V1 will be greater than reference voltage Vref 1 so, the output voltage V 2 of comparator U1 is high, open NMOS pipe MN2 falls the charge discharging resisting of output VP, reduces the magnitude of voltage of output VP with this; If the voltage of VP is lower than predetermined value, V1 will be less than reference voltage Vref 1 so, and the output voltage V 2 of comparator U1 is low, turn-off NMOS pipe MN2, thereby blocking-up output VP goes up releasing of electric charge, improves the voltage of output VP with this, finally keeps output VP to go up the stability of voltage.But because this method allows charge pump be in maximum rating, and comes stable high voltage by the unnecessary electric charge of releasing always, so its power consumption is very big.
As shown in Figure 4 be another kind of traditional method for stabilizing voltage.Under the driving of two-phase non-overlapping clock CLK1 as shown in Figure 2 that clock generating module produces and CLK2, charge pump work also produces high pressure VP, sampling by two sampling capacitance C3 and C4, obtain a sampled voltage V3, V3 and reference voltage Vref 2 are input to positive and the negative-phase input of comparator U2 respectively, if output high pressure VP is greater than predetermined value, V3 will be greater than reference voltage Vref 2 so, the output voltage V 4 of comparator U2 is high, like this, by V4 is that high level goes to control clock generating module, make the frequency of CLK1 and CLK2 reduce, perhaps stop the output of clock CLK1 and CLK2, reach driving force that reduces charge pump or the purpose that stops charge pump work, reduce the magnitude of voltage of output VP with this; If the voltage of VP is lower than predetermined value, V3 will be less than reference voltage Vre2 so, the output voltage V 4 of comparator U2 is low, it does not produce any influence to clock generating module, charge pump works under original driving force, improve the voltage of output VP with this, finally keep output VP to go up the stability of voltage.But this method is owing to reduced clock frequency even stopped the clock input, make that the additional speed of output electric charge is slack-off with the frequency reduction, and because the time-delay of clock path and the time-delay of capacitor charge and discharge, be higher than or be lower than predetermined value when system detects output high pressure VP, and then stop or during the recovery system clock, output voltage has had bigger fluctuation, and especially this fluctuation is bigger under the situation of large load current.
Summary of the invention:
The objective of the invention is to propose a kind of charge pump circuit of high-precision low-power consumption, it controls the speed that discharges and recharges of coupling capacitance by a coupling capacitance controller that is connected between clock generating module and the charge pump coupling capacitance, come dynamic from being in harmony the driving force that changes charge pump with this, reach the purpose of saving power consumption and improving output high pressure precision, be particularly suitable for being used under the bigger situation of load current; Also adopted the coupling capacitance partition method, make charge pump can not be in halted state, promptly after the output high pressure surpasses predetermined value, still have certain driving force work, make the decline of high-voltage output end magnitude of voltage be unlikely to too fast, to keep the stability of output end voltage.
The present invention contains:
Charge pump;
Clock generating module: produce two-phase non-overlapping clock signal;
Sample circuit: constitute by two electric capacity that are connected between charge pump high-voltage output end and the ground, and from the centre of two electric capacity
Node obtains sampled voltage;
Voltage comparator;
It is characterized in that,
The normal phase input end of described voltage comparator connects reference voltage, and negative-phase input connects described sampled voltage, and its output voltage is reduced with the increase of charge pump output voltage;
Also contain the coupling capacitance controller: its input is above-mentioned two-phase non-overlapping clock signal, and output connects the coupling capacitance of described charge pump, and control end connects the output of described comparator; Described coupling capacitance controller is equivalent to the variable resistor that a resistance changes with the comparator output voltage, and the variation of this resistance makes the clock signal of described coupling capacitance controller output produce corresponding the variation to the speed that discharges and recharges of coupling capacitance in the charge pump.
Its feature is that also described coupling capacitance controller contains two transmission gates; The output of described comparator connects the grid of the PMOS pipe of two transmission gates respectively by two phase inverters, the output of described comparator directly connects the grid of the NMOS pipe of two transmission gates; The input of described two transmission gates connects above-mentioned two phase clock signal respectively, and two outputs alternately connect the coupling capacitance of charge pump respectively.
Its feature is that also described clock signal also directly links to each other with described charge pump by another group coupling capacitance, has the driving force by this group coupling capacitance decision all the time to guarantee described charge pump.
Evidence, the present invention can reduce the power consumption of charge pump greatly, and can access high-precision output high pressure, has reached its intended purposes.
Description of drawings:
Fig. 1, traditional Dickson type positive high voltage charge pump schematic diagram;
Fig. 2, the sequential chart of two-phase non-overlapping clock signal;
Fig. 3, traditional passing through released path to exporting the system block diagram that high pressure carries out the voltage stabilizing adjusting;
Fig. 4, traditional control clock that passes through carries out the system block diagram that voltage stabilizing is regulated to the output high pressure;
Fig. 5 A, the system block diagram of the embodiment of the invention one;
Fig. 5 B, the charge pump schematic diagram of the embodiment of the invention one;
Fig. 5 C, the coupling capacitance controller circuitry schematic diagram of the embodiment of the invention one;
Fig. 6 A, the system block diagram of the embodiment of the invention two;
Fig. 6 B, the charge pump schematic diagram of the embodiment of the invention two;
Fig. 6 C, the coupling capacitance controller circuitry schematic diagram of the embodiment of the invention two.
Embodiment:
Accompanying drawings the specific embodiment of the present invention.
Shown in Fig. 5 A is the system block diagram of first embodiment of the present invention.Wherein sampling capacitance C5 and C6 are connected between high-voltage output end VP and the ground Gnd, be connected to the negative-phase input of comparator U3 from the middle sampled voltage V5 that draws of two sampling capacitances, and the normal phase input end of comparator U3 links to each other with reference voltage Vref 3, and its comparative result V6 is connected on the coupling capacitance controller.The input of coupling capacitance controller also derives from two-phase non-overlapping clock signal CLK1 and the CLK2 that clock generating module produces, and its output signal K1 links to each other with charge pump with K2.And charge pump produces required high pressure and is connected to the end of sampling capacitance C5 from output port VP.The coupling capacitance controller is equivalent to the variable resistor that a resistance changes with the comparator output voltage, when the output voltage of charge pump obtains a sampled voltage through over-sampling, this sampled voltage compare with reference voltage reduce/when increasing, the output voltage of comparator U3 increases/reduces, the variable-resistance resistance of coupling capacitance controller equivalence reduces/increases, make clock signal speed up/slow down, output voltage that so just can the stable charging pump to the impulse electricity of coupling capacitance.
Fig. 5 B is the schematic diagram of charge pump among first embodiment, and it is just the same with charge pump shown in Figure 1.
Fig. 5 C is the schematic diagram of coupling capacitance controller among first embodiment, and it is made up of identical two parts (5Ca and 5Cb), and every part all contains a phase inverter and a transmission gate.Wherein the input of phase inverter is V6, output is connected to the grid of PMOS pipe in the transmission gate, and the grid of NMOS pipe is directly connected on the V6 in the transmission gate, the input of transmission gate T1 and output are respectively on CLK1 and the K1 among the 5Ca, and the input of transmission gate T2 and output are respectively CLK2 and K2 among the 5Cb.When V6 when low, phase inverter I1 and I2 are output as height, transmission gate is closed, and between CLK1 and the K1, and turn-offs fully between CLK2 and the K2.As V6 when being high, phase inverter I1 and I2 are output as low, and two transmission gates are opened, between CLK1 and the K1, and conducting fully between CLK2 and the K2.Equally, if V6 is in high level V
DDAnd certain when value between the low level Gnd, transmission gate can be in half conducting state, be between CLK1 and the K1, and be in half conducting state between CLK2 and the K2, this can equivalence be between CLK1 and K1, and a resistance arranged respectively between CLK2 and the K2, and the size of equivalent resistance reduces along with the increase of V6 magnitude of voltage, therefore clock signal will be subjected to the control of this resistance value size to the speed of discharging and recharging of coupling capacitance, and then the driving force of charge pump will be subjected to the control of this resistance.Therefore can control the driving force of charge pump by the size of V6 magnitude of voltage, and the V6 magnitude of voltage is big more, the driving force of charge pump is big more.
The operation principle of system is as follows in the first embodiment of the invention: under the driving of the two-phase non-overlapping clock that clock generating module produces, charge pump is started working and the magnitude of voltage of VP is progressively risen, when VP is lower than predetermined value, the sampled voltage V5 that sampling capacitance C5 and C6 obtain is less than reference voltage Vref 3, so the output voltage V 6 of comparator U3 is high, the coupling capacitance controller is directly connected to charge pump to two-phase non-overlapping clock signal CLK1 and the CLK2 that clock generating module produces by the transmission gate T1 and the T2 of complete conducting respectively, make charge pump with the driving force work of maximum, guarantee that the magnitude of voltage of output VP can fast rise; When VP is higher than predetermined value, the sampled voltage V5 that sampling capacitance C5 and C6 obtain is greater than reference voltage Vref 3, so the output voltage V 6 of comparator U3 will be low by hypermutation, two-phase non-overlapping clock signal CLK1 that the coupling capacitance controller produces clock generating module by the transmission gate T1 that turn-offs fully and T2 and CLK2 are with disconnecting between the charge pump, charge pump is quit work, and the magnitude of voltage of output VP will progressively descend like this.At last when system works a period of time and after stablizing, differ very little between the magnitude of voltage of output high pressure VP and the predetermined value, also have only very little voltage difference between sampled voltage V5 that process sampling capacitance C5 and C6 obtain and the reference voltage Vref 3, this moment, the output voltage V 6 of comparator U3 can be in harmony at supply voltage V certainly according to the size of charge pump circuit load
DDAnd near certain value between the ground Gnd, and load is more little, the value of V6 can be in harmony certainly near the magnitude of voltage that approaches ground Gnd more, the ducting capacity of transmission gate is also more little like this, its equivalent resistance is big more, the speed of discharging and recharging to coupling capacitance in the charge pump shown in Fig. 5 B can slow down, and the driving force of charge pump circuit is also more little, and then the power consumption of whole system is also more little.The driving force meeting of final charge pump and the size of load are complementary, and do not have unnecessary power consumption, and promptly whole charge pump circuit can dynamically be in harmony under the operating state of power consumption minimum certainly according to the size of load, thereby has saved power consumption.Simultaneously, compare with method shown in Figure 4, the charge pump circuit that the present invention proposes is not the control clock generating module, therefore the time-delay that does not have clock generating module and produced, clock frequency does not change all the time yet, and it is more stable that the output electric charge is replenished speed, and the magnitude of recruitment of each electric charge all be according to the load size dynamically continuous be in harmony adjustment certainly, thereby the voltage fluctuation of its output is very little, has realized high-precision purpose.
Shown in Fig. 6 A is the system block diagram of second embodiment of the present invention.This embodiment has adopted the coupling capacitance partition method, and one group of coupling capacitance of charge pump is separated into two groups of coupling capacitances, and one group of coupling capacitance links to each other with clock signal by the coupling capacitance controller, and output voltage is carried out stable regulation; Another group coupling capacitance then directly links to each other with clock, guarantees that charge pump has minimum driving force always, and can not quit work, and makes output voltage more stable.As shown in Figure 6, sampling capacitance C7 and C8 are connected between high-voltage output end VP and the ground Gnd, be connected to the negative-phase input of comparator U4 from the middle sampled voltage V7 that draws of two sampling capacitances, and the normal phase input end of comparator U4 links to each other with reference voltage Vref 4, and its comparative result V8 is connected on the coupling capacitance controller.The input of coupling capacitance controller also derives from two-phase non-overlapping clock signal CLK1 and the CLK2 that clock generating module produces, and its output signal K3 links to each other with charge pump with K4.Simultaneously charge pump also directly receives two-phase non-overlapping clock signal CLK1 and the CLK2 that produces from clock generating module, and produces required high pressure and be connected to the end of sampling capacitance C7 from output port VP.
Fig. 6 B is the schematic diagram of charge pump among second embodiment, it (is made of NMOS pipe MN6-MN10 and coupling capacitance C21-C24 on the basis of the charge pump shown in Fig. 5 B, clock signal is K3 and K4) increased the coupling capacitance passage that a route coupling capacitance C11-C14 constitutes, the end of coupling capacitance C21-C24 and the end of coupling capacitance C11-C14 are connected in node P6-P9 jointly, and the other end of coupling capacitance C11-C14 then directly connects clock signal clk 1 and CLK2.
Fig. 6 C is the schematic diagram of coupling capacitance controller among second embodiment, and the structure of it and Fig. 5 C is just the same, and it also is made up of identical two parts (6Ca and 6Cb), and every part all contains a phase inverter and a transmission gate.Wherein the input of phase inverter is V8, output is connected to the grid of PMOS pipe in the transmission gate, and the grid of NMOS pipe is directly connected on the V8 in the transmission gate, the input of transmission gate T3 and output are respectively on CLK1 and the K3 among the 6Ca, and the input of transmission gate T4 and output are respectively CLK2 and K4 among the 6Cb.When V8 when low, phase inverter I3 and I4 are output as height, transmission gate is closed, and between CLK1 and the K3, and turn-offs fully between CLK2 and the K4.As V8 when being high, phase inverter is output as low, and transmission gate is opened, between CLK1 and the K3, and conducting fully between CLK2 and the K4.Equally, if V8 is in high level V
DDAnd certain when value between the low level Gnd, transmission gate can be in half conducting state, be between CLK1 and the K3, and be in half conducting state between CLK2 and the K4, this can equivalence be between CLK1 and K3, and a resistance arranged respectively between CLK2 and the K4, and the size of equivalent resistance reduces along with the increase of V8 magnitude of voltage, therefore clock signal will be subjected to the control of this resistance value size to the speed of discharging and recharging of coupling capacitance, and then the driving force of charge pump will be subjected to the control of this resistance.Therefore can control the driving force of charge pump by the size of V8 magnitude of voltage, and the V8 magnitude of voltage is big more, the driving force of charge pump is big more.
The system of second embodiment of the invention has not only adopted the described control coupling capacitance of Fig. 5 to discharge and recharge the method for speed, also adopts the coupling capacitance partition method to guarantee that charge pump has minimum driving force, and can not quit work.Its operation principle is as follows: under the driving of the two-phase non-overlapping clock that clock generating module produces, charge pump is started working and the magnitude of voltage of VP is progressively risen, when VP is lower than predetermined value, the sampled voltage V7 that sampling capacitance C7 and C8 obtain is less than reference voltage Vref 4, so the output voltage V 8 of comparator U4 is high, two-phase non-overlapping clock signal CLK1 and CLK2 that clock generating module produces are directly connected on the coupling capacitance C11-C14 of charge pump shown in Fig. 6 B, simultaneously coupling capacitance controller two-phase non-overlapping clock signal CLK1 that clock generating module is produced and CLK2 are directly connected on the coupling capacitance C21-C24 of charge pump shown in Fig. 6 B by the transmission gate of a complete conducting by K3 and K4, this moment CLK1 and K3 waveform, and the waveform of CLK2 and K4 is the same, the equivalent coupled electric capacity of charge pump is made of C11-C14 and C21-C24 parallel connection, make charge pump with the driving force work of maximum, guarantee that the magnitude of voltage of output VP can fast rise; When VP is higher than predetermined value, the sampled voltage V7 that sampling capacitance C7 and C8 obtain is greater than reference voltage Vref 4, so the output voltage V 8 of comparator U4 will be low by hypermutation, two-phase non-overlapping clock signal CLK1 and CLK2 that clock generating module produces are directly connected on the coupling capacitance C11-C14 of charge pump shown in Fig. 6 B, simultaneously the two-phase non-overlapping clock signal CLK1 that clock generating module produced by the transmission gate that turn-offs fully of coupling capacitance controller and CLK2 are with disconnecting between K3 and the K4, K3 and K4 can not discharge and recharge coupling capacitance C21-C24 like this, this moment, the equivalent coupled electric capacity of charge pump had only C11-C14, make charge pump with the driving force work of minimum, the magnitude of voltage of output VP will progressively steadily descend like this.At last when system works a period of time and after stablizing, differ very little between the magnitude of voltage of output high pressure VP and the predetermined value, also have only very little voltage difference between sampled voltage V7 that process sampling capacitance C7 and C8 obtain and the reference voltage Vref 4, this moment, the output voltage V 8 of comparator U4 can be in harmony at supply voltage V certainly according to the size of charge pump circuit load
DDAnd near certain value between the ground Gnd, and load is more little, the value of V8 can be in harmony certainly near the magnitude of voltage that approaches ground Gnd more, the ducting capacity of transmission gate is also more little like this, its equivalent resistance is big more, the speed of discharging and recharging to coupling capacitance C21-C24 in the charge pump shown in Fig. 6 B can slow down, and the driving force of charge pump circuit is also more little, and then the power consumption of whole system is also more little.The driving force meeting of final charge pump and the size of load are complementary, and do not have unnecessary power consumption, and promptly whole charge pump circuit can dynamically be in harmony under the operating state of power consumption minimum certainly according to the size of load, thereby has saved power consumption.Simultaneously, compare with method shown in Figure 4, the clock frequency of the charge pump circuit that the present invention describes does not change all the time, more stable to the additional speed of output electric charge, and the magnitude of recruitment of each electric charge all be according to the load size dynamically continuous be in harmony adjustment certainly, thereby the voltage fluctuation of its output is very little, has realized high-precision purpose.In this embodiment, adopt the purpose of electric capacity partition method to be to allow charge pump can not be in halted state, promptly after surpassing predetermined value, the output high pressure still allow it with driving force work by coupling capacitance C11-C14 decision, make the decline of high-voltage output end magnitude of voltage be unlikely to too fast, keeping the stability of output end voltage, this method especially still can keep exporting the stable of high pressure under output load current requires to reach the situation of milliampere order of magnitude.When adding coupling capacitance C11-C14, the capacitance of C21-C24 can reduce to some extent, makes the capacitance sum of two electric capacity (as C11 and C21) of each node P6-P9 parallel connection of charge pump can satisfy the general design requirement of whole charge pump.
As mentioned above, the charge pump circuit that the present invention proposes has the feature of high accuracy and low-power consumption, and it is particularly suitable for being used under the bigger situation of load current.
Although above-mentioned description to several embodiment has particularity to a certain degree, this only is the explanation of the principle of the invention, and obviously, the present invention is not limited to these several embodiment that this paper is disclosed and illustrate.Therefore, not exceeding the suitable variation that may make in design of the present invention and the scope all will be included in the further embodiment of the present invention.
Claims (3)
1, high-precision low-power consumption charge pump circuit, contain:
Charge pump;
Clock generating module: produce two-phase non-overlapping clock signal;
Sample circuit: constitute by two electric capacity that are connected between charge pump high-voltage output end and the ground, and from the centre of two electric capacity
Node obtains sampled voltage;
Voltage comparator;
It is characterized in that,
The normal phase input end of described voltage comparator connects reference voltage, and negative-phase input connects described sampled voltage, and its output voltage is reduced with the increase of charge pump output voltage;
Also contain the coupling capacitance controller: its input is above-mentioned two-phase non-overlapping clock signal, and output connects the coupling capacitance of described charge pump, and control end connects the output of described comparator; Described coupling capacitance controller is equivalent to the variable resistor that a resistance changes with the comparator output voltage, and the variation of this resistance makes the clock signal of described coupling capacitance controller output produce corresponding the variation to the speed that discharges and recharges of coupling capacitance in the charge pump.
2, high-precision low-power consumption charge pump circuit as claimed in claim 1 is characterized in that, described coupling capacitance controller contains two transmission gates; The output of described comparator connects the grid of the PMOS pipe of two transmission gates respectively by two phase inverters, the output of described comparator directly connects the grid of the NMOS pipe of two transmission gates; The input of described two transmission gates connects above-mentioned two phase clock signal respectively, and two outputs alternately connect the coupling capacitance of charge pump respectively.
3, high-precision low-power consumption charge pump circuit as claimed in claim 1 or 2, it is characterized in that, described clock signal also directly links to each other with described charge pump by another group coupling capacitance, has the driving force by this group coupling capacitance decision all the time to guarantee described charge pump.
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| CN 03156438 CN1233086C (en) | 2003-08-29 | 2003-08-29 | High precision low power dissipation charge pump circuit |
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| CN 03156438 CN1233086C (en) | 2003-08-29 | 2003-08-29 | High precision low power dissipation charge pump circuit |
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| CN100423419C (en) * | 2004-04-21 | 2008-10-01 | 友达光电股份有限公司 | D.C voltage converter |
| CN101272091B (en) * | 2007-02-28 | 2010-10-20 | 三洋电机株式会社 | Charge pump circuit |
| US7876585B2 (en) | 2007-04-27 | 2011-01-25 | Mstar Semiconductor, Inc. | Voltage providing circuit and related method thereof |
| CN102055320A (en) * | 2011-01-24 | 2011-05-11 | 昆山睿识微电子有限公司 | Charge pump circuit and implementation method thereof |
| CN102263500A (en) * | 2010-05-27 | 2011-11-30 | 上海宏力半导体制造有限公司 | Charge pump circuit |
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| CN103280967A (en) * | 2013-05-29 | 2013-09-04 | 成都芯源系统有限公司 | Charge pump and method for enabling negative output voltage of charge pump to follow positive output voltage |
| CN103631304A (en) * | 2013-12-12 | 2014-03-12 | 中国电子科技集团公司第四十七研究所 | Voltage stabilization circuit |
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| CN100423419C (en) * | 2004-04-21 | 2008-10-01 | 友达光电股份有限公司 | D.C voltage converter |
| CN101272091B (en) * | 2007-02-28 | 2010-10-20 | 三洋电机株式会社 | Charge pump circuit |
| US7876585B2 (en) | 2007-04-27 | 2011-01-25 | Mstar Semiconductor, Inc. | Voltage providing circuit and related method thereof |
| CN101272090B (en) * | 2007-07-10 | 2012-07-18 | 清华大学 | High tension charge pump circuit |
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