CN1722301A - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
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- CN1722301A CN1722301A CN200510078130.8A CN200510078130A CN1722301A CN 1722301 A CN1722301 A CN 1722301A CN 200510078130 A CN200510078130 A CN 200510078130A CN 1722301 A CN1722301 A CN 1722301A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A semiconductor storage device having a word line driving circuit of a small circuit scale, and operating in stability. The device includes a first driving circuit 11 for driving a word line driving signal 15 towards a first potential, a second driving circuit 12 for driving the word line driving signal 15 towards a second potential, a third driving circuit 13 for driving the word line driving signal 15 to a third potential, and a driving control circuit 14. This driving control circuit 14 actuates the first driving circuit 11 when the input signal 16 is at a first logical value, while actuating the second driving circuit 12 when the input signal 16 transfers from the first logical value to the second logical value and actuating the third driving circuit 13 on detection that the word line driving signal 15 has been driven towards the second potential.
Description
Technical field
The present invention relates to semiconductor storage, particularly relate to the semiconductor storage of driving circuit with word line that storage unit is conducted interviews.
Background technology
The semiconductor storages such as DRAM that disposed storage unit at the intersection point with the bit line of word line quadrature are widely used in every respect.In such semiconductor storage, when word line reset, suppress the floating of VBB level of negative potential, the negative word line mode that reduces the leakage current of storage unit etc. is known, for example patent documentation 1 is disclosed.The word line driver circuit of patent documentation 1 rises to current potential VSS (earthing potential) to word line afterwards, the time delay through regulation, makes it drop to the VBB lower than VSS (negative potential) again.Generated by the delay circuit in the signal generating circuit that produces the signal that drives word line the time delay of this regulation.
Also have, when word line reset, and suppress the showy identical of VBB level, when word line activating, can suppress the consumption of VPP current potential.Adopt charging pumping mode as the VPP of booster power from power vd D, be generated in DRAM inside, thereby depend on the conversion efficiency of this circuit, for the current sinking IVPP of VPP and the current sinking IVDD of VDD, the calculating formula of IVPP=α * IVDD (α is a constant) is set up, reduction IVPP has very big effect for the reduction of the current sinking IVDD of DRAM self, and this is known.
Patent documentation 1: the spy open flat 10-241361 communique (Fig. 3, Fig. 5, Fig. 8)
Summary of the invention
In case word line is promoted to after GND (earthing potential) level, the timing that promotes beginning to the VBB level is extremely important for the meaning of the showy grade that suppresses the VBB level, as mentioned above, Ding Shi control is undertaken by the signal that produces from the signal generating circuit (timing generator) that has used delay element (delay circuit)., have a plurality of signal generating circuits to be dispersed in the chip internal of DRAM herein, the control signal that produces from the timing generator of some locality can not corresponding depend on the time lag deviation in the design place of circuit.Therefore, the time-controlled occasion in carrying out signal generating circuit, it is necessary that delay element constitutes for each circuit, thereby has caused the increase of block size.
Also have the test pattern that how uses in the test for DRAM, several times to tens times the when occasion that has makes word line activating to regular event.In this occasion, the fall time of word line (Fall time) is than common length, also needs corresponding control of time with activation from the lifting switching regularly of GND to VBB.Therefore, need a plurality of delay elements on the preparation timing generator, come switching delay element etc. according to pattern, it is complicated that circuit has become.
Have, if there is the level variation of power vd D, will change the time delay of delay element again, just might be able to not stablize the timing that control promotes beginning.
Thereby, the object of the present invention is to provide to have the semiconductor storage that circuit scale is little, stablize the word line driving circuit that moves.
The related semiconductor storage of an aspect of of the present present invention that achieves the above object is to have the semiconductor storage that is driven the word line driving circuit of word line by the driving current potential that changes with 2 stages in rising or descending.Constitute in this semiconductor storage, word line driving circuit has the signal level that detects word line, the testing circuit of output testing result, controls the driving timing of word line according to the output of testing circuit.
Also can constitute, word line driving circuit drives word line from the 1st current potential to the 2nd current potential, and testing circuit detects and driven this situation of word line to the 2nd current potential, drives word line according to the output of testing circuit to the 3rd current potential.
The semiconductor storage that another aspect of the present invention is related has: the 1st driving circuit that drives word line to the 1st current potential; Drive the 2nd driving circuit of word line to the 2nd current potential; And the 3rd driving circuit that drives word line to the 3rd current potential.Also have the 1st driving circuit is moved, when the 1st logical value transits to the 2nd logical value, the 2nd driving circuit is moved at input signal, detecting the Drive and Control Circuit that when the 2nd current potential has driven this situation of word line, the 3rd driving circuit is moved.
Can be that the 2nd current potential is between the 1st current potential and the 3rd current potential.
Also have, can be, the 1st current potential be the current potential higher than the supply voltage of Drive and Control Circuit, and the 2nd current potential is the earthing potential of Drive and Control Circuit, and the 3rd current potential is the current potential lower than earthing potential.
Have, can be, the 1st current potential be the current potential lower than the earthing potential of Drive and Control Circuit, and the 2nd current potential is the current potential of the supply voltage of Drive and Control Circuit, and the 3rd current potential is the current potential higher than supply voltage.
Also have, can be, Drive and Control Circuit has detection and has driven the logical circuit of this situation of word line to the 2nd current potential, and logical circuit moves under the supply voltage of Drive and Control Circuit.
Have, can be, the 1st driving circuit and the 3rd driving circuit comprise the circuit that the signal level of input signal is carried out conversion.
Related on the one hand again semiconductor storage of the present invention has: the 1st driving circuit that drives word line to the 1st current potential; Drive the 2nd driving circuit of word line to the 2nd current potential; Drive the 3rd driving circuit of word line to the 3rd current potential; And the 4th driving circuit that drives word line to the 4th current potential.Also have the 1st driving circuit is moved, when the 1st logical value transits to the 2nd logical value, the 2nd driving circuit is moved at input signal, the 3rd driving circuit is moved detecting when the 2nd current potential has driven this situation of word line, when the 2nd logical value transits to the 1st logical value, the 4th driving circuit is moved at input signal, detecting the Drive and Control Circuit that when the 4th current potential has driven this situation of word line, the 1st driving circuit is moved.
Can be, the 1st current potential be the current potential lower than the earthing potential of Drive and Control Circuit, and the 2nd current potential is the current potential of the supply voltage of Drive and Control Circuit, and the 3rd current potential is the current potential higher than supply voltage, and the 4th current potential is the earthing potential of Drive and Control Circuit.
Also have, can be, Drive and Control Circuit has detection and has driven the 1st logical circuit of this situation of word line and detected the 2nd logical circuit that has driven this situation of word line to the 4th current potential to the 2nd current potential, and the 1st and the 2nd logical circuit moves under the supply voltage of Drive and Control Circuit.
Have, can be, semiconductor storage be DRAM.
According to the present invention, when word line drive signal rose or descend, the signal level of feedback word line drive signal detected the variation of the level of word line drive signal self in Drive and Control Circuit, carried out the action of 2 stages, controlled according to this.Therefore, do not need the outside to have to be used to carry out the control circuit and the delay element of 2 stages action, just can realize with simple circuit formation.Also have, the timing adjustment that does not also need to be used to carry out the action of 2 stages just can be stablized and moved.
Description of drawings
Fig. 1 is the block diagram of driving circuit of the word line of the related semiconductor storage of expression embodiments of the present invention.
Fig. 2 is the circuit diagram of the major part of the related semiconductor storage of expression the 1st embodiment of the present invention.
Fig. 3 is the circuit diagram of driving circuit of the word line of the related semiconductor storage of expression the 1st embodiment of the present invention.
Fig. 4 is the timing diagram of driving circuit of the word line of the related semiconductor storage of expression the 1st embodiment of the present invention.
Fig. 5 is the circuit diagram of driving circuit of the word line of the related semiconductor storage of expression the 2nd embodiment of the present invention.
Fig. 6 is the timing diagram of driving circuit of the word line of the related semiconductor storage of expression the 2nd embodiment of the present invention.
Embodiment
Fig. 1 represents the block diagram of driving circuit of the word line of the semiconductor storage that embodiments of the present invention are related.In Fig. 1, the driving circuit of the word line of semiconductor storage has: the 1st driving circuit 11 that drives word-line signal 15 to the 1st current potential; Drive the 2nd driving circuit 12 of word-line signal 15 to the 2nd current potential; Drive the 3rd driving circuit 13 of word-line signal 15 to the 3rd current potential; And Drive and Control Circuit 14.Drive and Control Circuit 14 makes the 1st driving circuit 11 move when input signal 16 is the 1st logical value, at input signal 16 the 2nd driving circuit 12 is moved, the 3rd driving circuit 13 is moved detecting when the 2nd current potential has driven word line drive signal 15 these situations.
The driving circuit of word line when word line drive signal 15 rises or descends, makes potential change with the 2nd current potential and the action of 2 stages of the 3rd current potential by constituting with upper type.Carry out this 2 graduated increasing action by the signal level of word line drive signal 15 being fed back to Drive and Control Circuit 14.Therefore, carry out the action of 2 stages, the control circuit and the delay element that do not need the outside to have to be used to carry out the action of 2 stages with the variation of the level of word line drive signal 15 self.Also have, also do not need to be used to carry out the timing adjustment of 2 stages action.
Secondly, explain the example of physical circuit according to embodiment.Fig. 2 is expression and the word line driving circuit relevant circuit block diagram of conduct with the DRAM of the related major part of the present invention.For DRAM, chip is divided into 8 as a whole, thereby constitutes a plurality of memory blocks or group.Be divided into the memory cell array 40 that contains identical formation in each piece of 8 respectively, dispose sub-word driver 30 in the both sides of memory cell array 40.End along each memory cell array 40 is provided with Y demoder YDEC, disposes X demoder XDEC in the direction with Y demoder YDEC quadrature.The storage unit of selecting by the not shown sub-word line that extends to longitudinal direction from X demoder XDEC with from the Y selecting line that Y demoder YDEC extends is accessed.
In Fig. 2, low order address gating (RAS) signal and low address signal on the timing generator 20 input DRAM, for the memory cell array 40 of visit regulation to corresponding word lines driving circuit 10 output signal IN1a (IN1b).Word line driving circuit 10 comes driven element word driver 30 according to the signal from timing generator 20 inputs.Sub-word driver 30 is connected with the memory cell array 40 of regulation, drives storage unit in the memory cell array 40 according to the output signal OUT1a (OUT1b) of word line driving circuit 10.
In above formation, word line driving circuit 10 is controlled when word line rising/decline (Rise/Fall), and (OUT1a OUT1b) carries out potential change with 2 stages to make output signal.Secondly, describe word line driving circuit 10 in detail.
Fig. 3 is the circuit diagram of driving circuit of the word line of the related semiconductor storage of expression the 1st embodiment of the present invention.In Fig. 3, driving circuit has N channel fet Q1, Q2, Q7, Q8, Q11, Q12, Q14, Q15, P channel fet Q3, Q4, Q5, Q6, Q9, Q10, Q13, inverter circuit INV1, INV2, INV3, INV4, INV5, NAND circuit NAND1, NAND2.
The input signal IN1 of driving circuit is imported by inverter circuit INV1.The output signal of inverter circuit INV1 is supplied to the grid of FETQ2, the input end of inverter circuit INV2, the input end of NAND circuit NAND1, the input end of NAND circuit NAND2.The output terminal of inverter circuit INV2 is connected with the grid of FETQ1.
Also have, the output signal OUT1 of driving circuit is by another input end input of NAND circuit NAND1, and the output terminal of NAND circuit NAND1 is connected with the input end of the grid of FETQ5, inverter circuit INV3, another input end of NAND circuit NAND2.The output terminal of NAND circuit NAND2 is connected with the input end of inverter circuit INV4, and the output terminal of inverter circuit INV4 is connected with the input end of the grid of FETQ10, inverter circuit INV5.The output terminal of inverter circuit INV5 is connected with the grid of FETQ9.
FETQ1, Q2, Q3, Q4 constitute level-conversion circuit 21.The source ground of FETQ1, Q2.The grid of the drain electrode of FETQ1, the drain electrode of FETQ3 and FETQ4 is connected, and is connected with the grid of FETQ13 again.Also have, the grid of the drain electrode of FETQ2, the drain electrode of FETQ4 and FETQ3 is connected.Have, the source electrode of FETQ4 and FETQ3 is connected with power supply VPP again.
Also have, FETQ5, Q6, Q7, Q8 constitute level-conversion circuit 22.The source electrode of FETQ7, Q8 is connected with power supply VBB.The grid of the drain electrode of FETQ7, the drain electrode of FETQ5 and FETQ8 is connected, and is connected with the grid of FETQ14 again.Also have, the grid of the drain electrode of FETQ8, the drain electrode of FETQ6 and FETQ7 is connected.Have, the source electrode of FETQ5 and FETQ6 is connected with power vd D again.
Have, FETQ9, Q10, Q11, Q12 constitute level-conversion circuit 23 again.The source electrode of FETQ11, Q12 is connected with power supply VBB.The grid of the drain electrode of FETQ11, the drain electrode of FETQ9 and FETQ12 is connected, and is connected with the grid of FETQ15 again.Also have, the grid of the drain electrode of FETQ12, the drain electrode of FETQ10 and FETQ11 is connected.Have, the source electrode of FETQ9 and FETQ10 is connected with power vd D again.
On the other hand, the source electrode of FETQ13 is connected with power supply VPP, and drain electrode is connected with the drain electrode of FETQ14, the drain electrode of FETQ15, becomes lead-out terminal OUT1.The source ground of FETQ14, the source electrode of FETQ15 is connected with power supply VBB.
More than the driving circuit of Gou Chenging is to control the circuit of conduct to the output signal OUT1 of the voltage supply source of word line by input signal IN1, input signal IN1 is the amplitude between ground connection (GND)/VDD, and output signal OUT1 is the amplitude between VBB (negative potential)/VPP (word boost current potential).For this amplitude conversion, have level- conversion circuit 21,22,23 and FETQ13, the Q14, the Q15 that are connected with separately output.Level-conversion circuit 21 is the level-conversion circuits between VDD/VPP, the level translation that level- conversion circuit 22,23 is administered between GND/VBB.On the other hand, output signal OUT1 is fed back to NAND circuit NAND1, and according to the level state (VPP or VBB) of output signal OUT1, NAND circuit NAND1 carries out anti-phase, moves according to this.
Secondly, the action of driving circuit shown in Figure 3 is described.Fig. 4 is the timing diagram of driving circuit of the word line of the related semiconductor storage of expression the 1st embodiment of the present invention.In the DRAM that has adopted the negative word line mode, under pre-charge state, input signal IN1 is fixed on the GND level, and output signal OUT1 is fixed on VBB level (negative potential).Accept activation instruction etc. and activate DRAM from this state, the input signal IN1 that has produced from the timing generator of chip internal etc. just transits to the VDD level.Input signal IN1 is the level transition between GND/VDD, and passes through the level translation of level- conversion circuit 21,22,23, and output signal OUT1 just becomes the level transition between VBB/VPP.Acceptance is from the GND of the input signal IN1 transition to VDD, signal PG11, the NG11 of each FETQ13, the Q14 that is connected with output signal OUT1, each grid of Q15, the current potential of NG12 change as shown in Figure 3, and output signal OUT1 changes to the VPP level from VBB.Input signal IN1 contains the address information from the DRAM outside, and the word line of DRAM inside is optionally boosted.
Secondly, DRAM accepts the precharge instruction from state of activation, just makes word line etc. get back to reset mode.At this moment, in case the output signal OUT1 that has boosted to the VPP level is risen near the GND level by FETQ14, the level of output signal OUT1 is lower than the words of NAND circuit NAND1 thresholding current potential, FETQ14 is ended, make the FETQ15 conducting simultaneously, finally output signal OUT1 is risen to the VBB level.That is, not to make the electric charge that has been charged to the VPP level, but in case, just make the signal OUT1 that has become the GND level drop to the current potential of VBB level to the GND discharge without a break to the discharge of VBB level.Floating of VBB level in the time of so just suppressing word line reset.
Circuit constituted make the above driving circuit that has illustrated, just can drive an output signal line (word line) according to an input signal cable.Generally there are being a lot of driving circuits to be dispersed in the occasion of dram chip inside, the time lag deviation of the designability of the switching timing of 2 graduated increasings when resetting just might produce, but, driving circuit according to embodiment, control switching timing with driving circuit self, thereby without the adjustment of time lag deviation.Also have, DRAM in a large amount of test modes of using etc., have from the word line of common several times to tens times and select action, but, when this test mode, the timing adjustment of also not carrying out being harmonious with separately action just can be carried out the switching that 2 graduated increasings move really.And, do not control switching timing because do not use delay circuit, so produce the caused timing offset of the change of VDD hardly.Have again, control according to timing to the rising of the decline of the GND of word line or VDD to the switching timing of VBB or VPP, even thereby have the change in voltage of VBB or VPP, switching timing can not change yet.
Fig. 5 is the circuit diagram of driving circuit of the word line of the related semiconductor storage of expression the 2nd embodiment of the present invention.The driving circuit of the 2nd embodiment is compared with the driving circuit of the 1st embodiment, has added circuit, makes rising also carry out the action of 2 stages.Symbolic representation same thing identical with Fig. 3 or suitable thing omit explanation among Fig. 5.Fig. 5 compares with Fig. 3, has added FETQ16, NOR circuit NOR1, NOR2, inverter circuit INV6.
The source electrode of FETQ16 is connected with VDD, and drain electrode is connected with the drain electrode of FETQ13, the drain electrode of FETQ14, the drain electrode of FETQ15, produces the output signal OUT2 of driving circuit.And the drain electrode of FETQ16 is connected with the input end of NOR circuit NOR1.The output of inverter circuit INV1 is connected with another input end of NOR circuit NOR1, the input end of NOR circuit NOR2, the input end of NAND circuit NAND2.
The output of NOR circuit NOR1 is connected with another input end of NOR circuit NOR2, and is connected with the grid of FETQ16 by signal NG23.The output of NOR circuit NOR2 is imported by inverter circuit INV6, and the output of inverter circuit INV6 is supplied to the input end of the grid of FETQ2, inverter circuit INV2.
More than the driving circuit of the Fig. 5 of Gou Chenging is identical with embodiment 1 in the action of the side that resets (decline side or Fall side) of output signal OUT2, but, be provided with the 2 stage commutation circuits that FETQ16 constitutes in Rise side (upthrow side), to the level of NOR circuit NOR1 feedback loop output signal OUT2, thereby become the circuit formation of carrying out rising (Rise) action of output signal OUT2 with 2 stages.
Secondly, the action of driving circuit shown in Figure 5 is described.Fig. 6 is the timing diagram of driving circuit of the word line of the related semiconductor storage of expression the 2nd embodiment of the present invention.
When the activation action of DRAM, driving circuit is accepted the rising of input signal IN2, signal NG23 as the output of NOR circuit NOR1 will rise, by the FETQ16 that source electrode is connected with VDD, output signal OUT2 carries out current potential to VDD-Vtn (Vtn is the falling quantity of voltages of FETQ16) at once and rises.Accept the level of this output signal OUT2, NOR circuit NOR1 will be anti-phase, and signal NG23 descends, descend as the signal PG21 of the signal of the drain electrode of FETQ1, output signal OUT2 by conducting the boosted VPP level that arrives of FETQ13.
Driving circuit shown in Figure 5 can carry out above action with the rising of output signal OUT2, carries out the switching of 2 graduated increasings action really.What in addition, the action of the decline of output signal OUT2 and embodiment 1 had illustrated is identical.
Claims (13)
1. a semiconductor storage has the word line driving circuit that is driven word line by the driving current potential that changes with 2 stages in rising or descending, it is characterized in that constituting,
Word line driving circuit has the signal level that detects word line, the testing circuit of output testing result, controls the driving timing of word line according to the output of described testing circuit.
2. semiconductor storage according to claim 1 is characterized in that,
Described word line driving circuit drives described word line from the 1st current potential to the 2nd current potential,
Described testing circuit detects and has driven this situation of described word line to described the 2nd current potential,
Output according to described testing circuit drives described word line to the 3rd current potential.
3. semiconductor storage is characterized in that having:
Drive the 1st driving circuit of word line to the 1st current potential;
Drive the 2nd driving circuit of described word line to the 2nd current potential;
Drive the 3rd driving circuit of described word line to the 3rd current potential; And
Described the 1st driving circuit is moved, when described the 1st logical value transits to the 2nd logical value, described the 2nd driving circuit is moved at described input signal, detecting the Drive and Control Circuit that when described the 2nd current potential has driven this situation of described word line, described the 3rd driving circuit is moved.
4. according to claim 2 or 3 described semiconductor storages, it is characterized in that described the 2nd current potential is between described the 1st current potential and described the 3rd current potential.
5. according to claim 2 or 3 described semiconductor storages, it is characterized in that, described the 1st current potential is the current potential higher than the supply voltage of described Drive and Control Circuit, and described the 2nd current potential is the earthing potential of described Drive and Control Circuit, and described the 3rd current potential is the current potential lower than described earthing potential.
6. according to claim 2 or 3 described semiconductor storages, it is characterized in that, described the 1st current potential is the current potential lower than the earthing potential of described Drive and Control Circuit, described the 2nd current potential is the current potential of the supply voltage of described Drive and Control Circuit, and described the 3rd current potential is the current potential higher than described supply voltage.
7. semiconductor storage according to claim 3, it is characterized in that, described Drive and Control Circuit has detection and has driven the logical circuit of described this situation of word line to described the 2nd current potential, and described logical circuit moves under the supply voltage of described Drive and Control Circuit.
8. semiconductor storage according to claim 3 is characterized in that, described the 1st driving circuit and described the 3rd driving circuit comprise the circuit that the signal level of described input signal is carried out conversion.
9. semiconductor storage is characterized in that having:
Drive the 1st driving circuit of word line to the 1st current potential;
Drive the 2nd driving circuit of word line to the 2nd current potential;
Drive the 3rd driving circuit of word line to the 3rd current potential;
Drive the 4th driving circuit of word line to the 4th current potential; And
Described the 1st driving circuit is moved, when described the 1st logical value transits to the 2nd logical value, described the 2nd driving circuit is moved at described input signal, described the 3rd driving circuit is moved detecting, when described the 2nd logical value transits to described the 1st logical value, described the 4th driving circuit is moved at described input signal, detecting the Drive and Control Circuit that when described the 4th current potential has driven this situation of described word line, described the 1st driving circuit is moved.
10. semiconductor storage according to claim 9, it is characterized in that, described the 1st current potential is the current potential lower than the earthing potential of described Drive and Control Circuit, described the 2nd current potential is the current potential of the supply voltage of described Drive and Control Circuit, described the 3rd current potential is the current potential higher than described supply voltage, and described the 4th current potential is the earthing potential of described Drive and Control Circuit.
11. semiconductor storage according to claim 9, it is characterized in that, described Drive and Control Circuit has detection and has driven the 1st logical circuit of described this situation of word line and detected the 2nd logical circuit that has driven this situation of word line to the 4th current potential to described the 2nd current potential, and the described the 1st and the 2nd logical circuit moves under the supply voltage of described Drive and Control Circuit.
12. semiconductor storage according to claim 9 is characterized in that, described the 1st driving circuit and described the 3rd driving circuit comprise the circuit that the signal level of described input signal is carried out conversion.
13., it is characterized in that described semiconductor storage is DRAM according to any described semiconductor storage in the claim 1,2 and 9 to 12.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004-174141 | 2004-06-11 | ||
| JP2004174141A JP2005353204A (en) | 2004-06-11 | 2004-06-11 | Semiconductor memory |
| JP2004174141 | 2004-06-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1722301A true CN1722301A (en) | 2006-01-18 |
| CN1722301B CN1722301B (en) | 2012-04-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200510078130.8A Expired - Fee Related CN1722301B (en) | 2004-06-11 | 2005-06-13 | Semiconductor storage device |
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| Country | Link |
|---|---|
| US (1) | US7203125B2 (en) |
| JP (1) | JP2005353204A (en) |
| CN (1) | CN1722301B (en) |
| TW (1) | TWI281158B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102007031411A1 (en) * | 2007-07-05 | 2009-01-08 | Qimonda Ag | Integrated circuit and method for reloading a circuit part of the integrated circuit |
| KR100980606B1 (en) * | 2008-09-08 | 2010-09-07 | 주식회사 하이닉스반도체 | Circuit and method for wordline driving |
| JP2012190522A (en) * | 2011-03-14 | 2012-10-04 | Elpida Memory Inc | Semiconductor device |
| US9183947B1 (en) * | 2014-04-16 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Detecting write disturb in multi-port memories |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5416747A (en) * | 1992-07-15 | 1995-05-16 | Kawasaki Steel Corporation | Semiconductor memory driven at low voltage |
| US5650976A (en) * | 1993-05-14 | 1997-07-22 | Micron Technology, Inc. | Dual strobed negative pumped wordlines for dynamic random access memories |
| JP3306682B2 (en) * | 1993-08-18 | 2002-07-24 | 日本テキサス・インスツルメンツ株式会社 | Drive circuit |
| JPH10241361A (en) | 1997-02-25 | 1998-09-11 | Toshiba Corp | Semiconductor memory |
| JPH10247384A (en) * | 1997-03-03 | 1998-09-14 | Mitsubishi Electric Corp | Synchronizing type semiconductor memory |
| US6111808A (en) * | 1998-03-02 | 2000-08-29 | Hyundai Electronics Industries Co., Ltd. | Semiconductor memory device |
| US6628564B1 (en) * | 1998-06-29 | 2003-09-30 | Fujitsu Limited | Semiconductor memory device capable of driving non-selected word lines to first and second potentials |
| US6728257B1 (en) * | 1998-08-28 | 2004-04-27 | The Board Of Trustees Of The University Of Illinois | Fluid flow fair scheduling emulation in wireless shared channel packet communication network |
| KR100313787B1 (en) * | 1999-12-30 | 2001-11-26 | 박종섭 | Wordline driving circuit for semiconductor memory device |
| KR100338772B1 (en) * | 2000-03-10 | 2002-05-31 | 윤종용 | Word line driver having divided bias line in non-volatile memory device and method thereof |
| US6646949B1 (en) * | 2000-03-29 | 2003-11-11 | International Business Machines Corporation | Word line driver for dynamic random access memories |
| US6580658B1 (en) * | 2002-11-07 | 2003-06-17 | Ememory Technology Inc. | Method using a word line driver for driving a word line |
-
2004
- 2004-06-11 JP JP2004174141A patent/JP2005353204A/en active Pending
-
2005
- 2005-05-23 TW TW094116751A patent/TWI281158B/en not_active IP Right Cessation
- 2005-06-09 US US11/148,413 patent/US7203125B2/en active Active
- 2005-06-13 CN CN200510078130.8A patent/CN1722301B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| TWI281158B (en) | 2007-05-11 |
| JP2005353204A (en) | 2005-12-22 |
| US20050276148A1 (en) | 2005-12-15 |
| TW200608395A (en) | 2006-03-01 |
| CN1722301B (en) | 2012-04-25 |
| US7203125B2 (en) | 2007-04-10 |
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