CN1484297A - Technology for mfg. semiconductor unit with improvement of leakage and resistance of deep submicron transistor - Google Patents
Technology for mfg. semiconductor unit with improvement of leakage and resistance of deep submicron transistor Download PDFInfo
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- CN1484297A CN1484297A CNA021427062A CN02142706A CN1484297A CN 1484297 A CN1484297 A CN 1484297A CN A021427062 A CNA021427062 A CN A021427062A CN 02142706 A CN02142706 A CN 02142706A CN 1484297 A CN1484297 A CN 1484297A
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Abstract
This invention discloses a semiconductor component processing technology for improving resistance and leakage phenomenon of deep submicrometers which is to form an isolated zone, a grating structure, source/drain light doped zone, a grating gap wall, increased source/drain structure and a source/drain heavy doped zone, then utilize the way of depositing metal layers in two sections to form metal layers of different thickness or different materials on the grating and the source/drain zone to generate different self-aligned metal silicide, avoiding current leakage of shallow interface.
Description
Technical field
The present invention is relevant a kind of semiconductor fabrication process technology, particularly form the different metal silicide of aligning voluntarily (self-aligned silicide about a kind of, Salicide) on grid structure and source/drain region, and can improve the resistance of deep submicron transistor and the semiconductor subassembly manufacturing process of leaky.
Background technology
The semiconductor subassembly manufacturing process enters into the deep-sub-micrometer manufacturing process, and when the integration of integrated circuit is more and more high, the area of source/drain region also is equal to and dwindles, but can increase the contact resistance of source/drain electrode end, and can't keep the high current driving ability of assembly, so, aim at the metal silicide technology automatically and be widely used in the semiconductor fabrication process gradually in order to reduce the electrical component resistance and to increase the convenience of follow-up connection lead layout.Yet the microminiaturization of assembly more is subject to the application that shallow metal silication meets face (Silicidedjunction), easier causing and the shallow junction leaky, therefore, selective silicon crystal technique of heap of stone is used for making the MOS (metal-oxide-semiconductor) transistor of the source/drain electrode of lifting, and to connect the electric leakage that application was produced of face controlled to obtain shallow junction and metal silication simultaneously.
Known is to consult Fig. 1 (a) to shown in Fig. 1 (c) making source/drain electrode that promotes and the semiconductor fabrication process step of aiming at assemblies such as metal silicide voluntarily.At first, shown in Fig. 1 (a), (it is made up of a grid oxic horizon 142 and a polysilicon layer 144 for shallow trench isolation, STI) 12 and one transistor grid structure 14 to be formed with shallow trench isolation regions in semiconductor substrate 10 earlier; Be shielding with grid structure 14 again, carry out more low-energy first time of implanting ions, in the semiconductor-based end 10, form a source/drain electrode lightly doped region 16; Then after grid structure 14 sidewalls form grid gap wall 18, the high vacuum chemical vapour deposition be optionally grow up in the system silicon build up crystal layer 20 in the source/surface, drain region, to form the source/drain electrode structure that promotes; The implanting ions second time that carries out higher-energy afterwards again forms source/drain electrode heavily doped region 22.
After the driving components such as source/drain electrode structure 22 of transistor grid structure 14 and lifting are all finished, the manufacturing process of aiming at metal silicide immediately voluntarily, at this moment, and shown in Fig. 1 (b), deposition one titanium coating 24 on the semiconductor-based end 10; Then, titanium coating 24 is carried out lonneal so that its with the grid structure 14 of below and source/drain electrode structure 22 on the pasc reaction of silicon build up crystal layer 20 become titanium silicide 28.Afterwards, utilize wet etch method to remove the titanium coating 24 that the part unreacted becomes titanium silicide 28, can form the titanium silicide 28 shown in Fig. 1 (c), at last this titanium silicide 28 be carried out high tempering and handle, to reduce the resistance value of titanium silicide 28.
Yet, in above-mentioned known semiconductor manufacturing technology steps, as desire form thicker metal silicide on grid structure when reducing resistance, then the metal silicide shallow junction of source/drain region very easily has leakage current (leakage current) phenomenon, and then influences component characteristic and reliability thereof.
Therefore, the present invention is at above-mentioned puzzlement, a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved proposed, so that in the resistance that reduces grid and source/drain region, can not cause the leaky of source/drain region again, and then effectively solve the existing disappearance of known techniques.
Summary of the invention
Main purpose of the present invention is that a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved is being provided, it is to form the different metal silicides of aligning voluntarily on grid structure and source/drain region, reducing the resistance in grid structure and the source/drain region, and can avoid the leaky of shallow junction simultaneously.
Another object of the present invention is that a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved is being provided, it is in the resistance value that reduces assembly, and avoid being created in leakage phenomenon in the shallow junction, make it meet the demand of assembly basic electric property, guaranteeing component characteristic and reliability thereof, and then improve product percent of pass.
For reaching above-mentioned purpose, the present invention is formed with the source/drain electrode structure of area of isolation, grid structure, source/drain electrode lightly doped region, grid gap wall, lifting and source/assemblies such as drain electrode heavily doped region in the semiconductor substrate; On this semiconductor-based end, form the chemical vapor deposition layer of a first metal layer, a barrier layer and a patterning then in regular turn, make it expose barrier layer on this grid structure; After removing the barrier layer and the first metal layer that exposes on the grid structure, remove the chemical vapor deposition layer of this patterning; On barrier layer and grid structure, deposit one second metal level then, and the semiconductor substrate carried out hot temper, make with contacted part second metal level of this grid structure and with the contacted part the first metal layer in this source/drain region to be transformed into metal silicide; Then remove unreacted second metal level, barrier layer and the first metal layer, at last this metal silicide is carried out hot temper.
Below illustrate in detail by the specific embodiment conjunction with figs., when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 (a) is each step structure cutaway view of known making semiconductor subassembly to Fig. 1 (c).
Fig. 2 (a) is that the present invention is in each step structure cutaway view of making semiconductor subassembly to Fig. 2 (h).
Embodiment
When known technology formed thicker metal silicide with reduction resistance on grid structure, the metal silicide shallow junction on source/drain region (shallow junction) very easily had leakage phenomenon to produce; And semiconductor subassembly manufacturing process proposed by the invention is to utilize the metal level of different-thickness on grid structure and the source/drain region or unlike material, improving the resistance value that reduces deep submicron transistor, and can avoid the leakage phenomenon of shallow junction.
Fig. 2 (a) is that a preferred embodiment of the present invention is at each step structure cutaway view of making semiconductor subassembly to Fig. 2 (h), as shown in the figure, the main manufacture method of the present invention is to include the following step: shown in Fig. 2 (a), semiconductor substrate 30 is provided earlier, be formed with shallow trench isolation regions (shallow trench isolation in it, STI) 32, in order to driving component and the passive component at the isolated semiconductor-based end 30; Form a transistor grid structure 34 on the semiconductor-based end 30, it is the polysilicon layer 344 that comprises a grid oxic horizon 342 and top thereof; Be shielding with grid structure 34 then, the implanting ions first time of a low concentration carried out in semiconductor substrate 30, so as in the semiconductor-based end 30 formation source/drain electrode light dope (lightly doped) zone 36; Be formed with grid gap wall 38 in two sidewalls of grid structure 34 are other again, its common oxide is formed.
Then, after this source/drain electrode lightly doped region 36 forms, and before forming silicon build up crystal layer, carrying out high-temperature activation earlier handles, it is greater than 800 ℃ or more carry out Rapid Thermal tempering (rapid thermal anneal in the boiler tube of high temperature (about 1050 ℃), RTA) handle, with the silicon crystal lattice on this surface, semiconductor-based ends 30 of reforming.After overheated temper, utilize brilliant method (epitaxy) of heap of stone again, in a brilliant reacting furnace of heap of stone, the silicon build up crystal layer 42 of optionally growing up respectively on grid structure 34 and source/drain region 40 is to form the source/drain electrode structure (raised source/drain structure) that promotes.And then be shielding with this grid structure 34 with grid gap wall 38, the implanting ions second time of a high concentration is carried out in semiconductor substrate 30, so as in the semiconductor-based end 30 formation source/drain electrode heavily doped region 40; Then carry out about 800 a ℃ boiler tube tempering or the Rapid Thermal temper of high temperature (900 ℃) more, become original crystalline state so that the amorphous silicon phenomenon tempering that produces is implanted because of ion in surface, the semiconductor-based ends 30.
Behind each modular construction that forms shown in Fig. 2 (a), can proceed two stage metal deposition manufacturing process.See also shown in Fig. 2 (b), utilize metal sputtering mode or chemical vapour deposition technique, on this semiconductor-based end 30, deposit a first metal layer 44 earlier, the material of this first metal layer 44 is to can be titanium, cobalt metal or platinum metal, or be other feasible metal material, the preferably is a titanium.Form a barrier layer 46 again in the surface of the first metal layer 44, the formation method of this barrier layer 46 is can utilize the cloth of nitrogen ion to plant or feed the surface of nitrogen in this first metal layer 44, makes the part the first metal layer 44 on surface be transformed into metal nitride with as this barrier layer 46.
Then, form a chemical vapor deposition layer 48 on these barrier layer 46 surfaces, shown in Fig. 2 (c), this chemical vapor deposition layer 48 is generally oxide layer, comprise four oxygen ethyl silicon (TEOS) interior, also silicon nitride layer, or any optionally removed chemical vapour deposition (CVD) material, the just material that available wet etching mode is removed in follow-up manufacturing technology steps.Then see also shown in Fig. 2 (d), utilize the dry ecthing mode, this semiconductor-based basal surface is removed in etching, the part chemical vapor deposition layer 48 of grid structure 34 tops is eliminated fully, and exposes the barrier layer 46 on this grid structure 34; Be shielding with this chemical vapor deposition layer 48 again, the etching step that carries out another time Removes All the barrier layer 46 and the first metal layer 44 of grid structure 34 tops, to expose this grid structure 34.At this moment, can remove remaining chemical vapor deposition layer 48, it is to utilize general wet etching mode in etching bath a comprehensive chemical vapor deposition layer 48 to be made at this semiconductor-based end 30 to remove, and can obtain the structure shown in Fig. 2 (e).
See also shown in Fig. 2 (f), utilize metal sputtering mode or chemical vapour deposition technique, form one second metal level 50 on grid structure 34 that exposes and barrier layer 46 (barrier layer 46 on the first metal layer 44), the material of this second metal level 50 is to can be titanium, cobalt metal or platinum metal, or be other feasible metal material, the preferably is a titanium.To carrying out a hot temper in this semiconductor-based end 30, it is to carry out tempering one in greater than 500 ℃ boiler tube, make this first metal layer 44 be transformed into metal silicide 52 with source/drain region 40 surface silicon epitaxial layers, 42 contacted parts, and make this second metal level 50 and the contacted part of silicon material on grid structure 34 surfaces be transformed into metal silicide 54, shown in Fig. 2 (g).After finishing the making of metal silicide 52,54, can remove this unreacted fully becomes residual the first metal layer 44, the barrier layer 46 of metal silicide 52 or reaction back to become the second residual metal level 50 of metal silicide 54 or reaction back with unreacted, shown in Fig. 2 (h), at last metal silicide 52,54 is carried out hot temper, to reduce the resistance value of metal silicide 52,54.
Wherein, employed barrier layer 46 is not for necessity in the above-mentioned manufacturing process, if the design of barrier layer free 46, then chemical vapor deposition layer 48 is directly to be formed at the first metal layer 44 surfaces, and can carry out each follow-up step in regular turn, as long as omit the structure and the step of barrier layer, all the other detailed process are identical with aforementioned content, so repeat no more in this.
A preferable manufacturing process embodiment thus, the metal silicide that this first metal layer produces is to be positioned on source/drain region, the metal silicide that this second metal level is produced then is positioned on grid structure, and two metal layer thickness and metal material kind are can be in response to its characteristic and assembly demand and do in good time scheduling.
The present invention is for improving known disappearance, a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved proposed, it is a mode of utilizing two phase deposition metal levels, the metal level that forms different-thickness or unlike material is on grid structure and source/drain region, to form the different metal silicides of aligning voluntarily.Metal silicide on grid structure is thicker in to reduce its resistance value; Metal silicide on source/drain region can be comparatively thin, cooperates the source/drain electrode structure that promotes again simultaneously, the resistance in source/drain region can significantly be reduced, and can improve the leaky of shallow junction fully.
Therefore, the present invention is when reducing the resistance value of assembly, also can avoid being created in simultaneously the leakage phenomenon in the shallow junction, makes its demand that meets the assembly basic electric property, guaranteeing component characteristic and reliability thereof, and then improves product percent of pass.
Above-described embodiment only is for technological thought of the present invention and characteristics are described, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (20)
1, a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved is characterized in that
Comprise the following steps:
(a) providing the semiconductor substrate, is source/drain electrode structure and the source/assemblies such as drain electrode heavily doped region that is formed with area of isolation, grid structure, source/drain electrode lightly doped region, grid gap wall, lifting in regular turn on it;
(b) deposition one the first metal layer on this semiconductor-based end;
(c) form a barrier layer in this first metal layer surface;
(d) form the chemical vapor deposition layer of a patterning on this barrier layer, to expose the barrier layer on this grid structure;
(e) remove this barrier layer and the first metal layer that exposes on this grid structure;
(f) remove the chemical vapor deposition layer of this patterning;
(g) deposition one second metal level on this barrier layer and this grid structure;
(h) hot temper is carried out at this semiconductor-based end, make with this second metal level of the contacted part of this grid structure and with this source/drain region this first metal layer of contacted part to be transformed into metal silicide;
(i) remove this second metal level, this barrier layer and this first metal layer that unreacted becomes metal silicide; And
(j) this metal silicide is carried out hot temper.
2, semiconductor subassembly manufacturing process according to claim 1 is characterized in that this step (a) forms these assemblies in this semiconductor-based end method more comprises the following steps:
On this semiconductor-based end, form a grid structure, comprise the polysilicon layer of a grid oxic horizon and top thereof;
With this grid structure is shielding, carries out the implanting ions of a low concentration, formation source/drain electrode lightly doped region in this semiconductor-based end;
Be formed with grid gap wall in this grid structure sidewall;
Carrying out the high-temperature activation manufacturing process handles;
Growth one silicon build up crystal layer in this grid structure and this source/drain electrode is to form the source/drain electrode structure that promotes;
With this grid structure and grid gap wall is shielding, a high concentration ion cloth is carried out at this semiconductor-based end plant, with formation source/drain electrode heavily doped region; And
This is carried out the semiconductor-based end carry out hot temper.
3, semiconductor subassembly manufacturing process according to claim 2, the growing method that it is characterized in that this silicon build up crystal layer are to utilize the brilliant method person of finishing of heap of stone.
4, semiconductor subassembly manufacturing process according to claim 1, the material that it is characterized in that this first metal layer are to can be titanium, cobalt metal, platinum metal, or other feasible metal material.
5, semiconductor subassembly manufacturing process according to claim 1 is characterized in that this step (d) more comprises: form a chemical vapor deposition layer on this barrier layer; And
This chemical vapor deposition layer is partly removed in etching, to form the chemical vapor deposition layer of this patterning, makes it expose this barrier layer on this grid structure.
6, semiconductor subassembly manufacturing process according to claim 1, the material that it is characterized in that this second metal level are to can be titanium, cobalt metal, platinum metal, or other feasible metal material.
7, semiconductor subassembly manufacturing process according to claim 1 is characterized in that this barrier layer is by nitrided metal layer institute constitutor.
8, semiconductor subassembly manufacturing process according to claim 8, the generation type that it is characterized in that this nitrided metal layer are for this first metal layer being carried out a nitrogen ion implantation, so that this first metal layer of part is transformed into this nitrided metal layer.
9, semiconductor subassembly manufacturing process according to claim 1 is characterized in that this chemical vapor deposition layer can be and comprises four oxygen ethyl silicon at interior oxide layer, silicon nitride layer, or any optionally removed chemical vapour deposition (CVD) material.
10, semiconductor subassembly manufacturing process according to claim 1 is characterized in that hot temper in this step (h) is to carry out tempering one in greater than 500 ℃ boiler tube.
11, semiconductor subassembly manufacturing process according to claim 1 is characterized in that hot temper in this step (j) is to carry out tempering in about 700 a ℃ boiler tube.
12, a kind of resistance of deep submicron transistor and semiconductor subassembly manufacturing process of leaky improved is characterized in that comprising the following steps:
(a) providing the semiconductor substrate, is source/drain electrode structure and the source/assemblies such as drain electrode heavily doped region that is formed with area of isolation, grid structure, source/drain electrode lightly doped region, grid gap wall, lifting in regular turn on it;
(b) deposition one the first metal layer on this semiconductor-based end;
(c) form the chemical vapor deposition layer of a patterning on this first metal layer, to expose this first metal layer on this grid structure;
(d) remove this first metal layer that exposes on this grid structure;
(e) remove the chemical vapor deposition layer of this patterning;
(f) deposition one second metal level on this grid structure;
(g) hot temper is carried out at this semiconductor-based end, make with this second metal level of the contacted part of this grid structure and with this source/drain region this first metal layer of contacted part to be transformed into metal silicide;
(h) remove this second metal level and this first metal layer that unreacted becomes metal silicide; And
(i) this metal silicide is carried out hot temper.
13, semiconductor subassembly manufacturing process according to claim 12 is characterized in that this step (a) forms these assemblies in this semiconductor-based end method more comprises the row step:
On this semiconductor-based end, form a grid structure, comprise the polysilicon layer of a grid oxic horizon and top thereof;
With this grid structure is shielding, carries out the implanting ions of a low concentration, formation source/drain electrode lightly doped region in this semiconductor-based end;
Be formed with grid gap wall in this grid structure sidewall;
Carrying out the high-temperature activation manufacturing process handles;
Growth one silicon build up crystal layer in this grid structure and this source/drain electrode is to form the source/drain electrode structure that promotes;
With this grid structure and grid gap wall is shielding, a high concentration ion cloth is carried out at this semiconductor-based end plant, with formation source/drain electrode heavily doped region; And
This is carried out the semiconductor-based end carry out hot temper.
14, semiconductor subassembly manufacturing process according to claim 13, the growing method that it is characterized in that this silicon build up crystal layer are to utilize the brilliant method person of finishing of heap of stone.
15, semiconductor subassembly manufacturing process according to claim 12, the material that it is characterized in that this first metal layer are to can be titanium, cobalt metal, platinum metal, or other feasible metal material.
16, semiconductor subassembly manufacturing process according to claim 12 is characterized in that this step (d) more comprises: form a chemical vapor deposition layer on this first metal layer; And
This chemical vapor deposition layer is partly removed in etching, to form the chemical vapor deposition layer of this patterning, makes it expose this first metal layer on this grid structure.
17, semiconductor subassembly manufacturing process according to claim 12, the material that it is characterized in that this second metal level are to can be titanium, cobalt metal, platinum metal, or other feasible metal material.
18, semiconductor subassembly manufacturing process according to claim 12 is characterized in that this chemical vapor deposition layer can be and comprises four oxygen ethyl silicon at interior oxide layer, silicon nitride layer, or any optionally removed chemical vapour deposition (CVD) material.
19, semiconductor subassembly manufacturing process according to claim 12 is characterized in that hot temper in this step (g) is to carry out tempering one in greater than 500 ℃ boiler tube.
20, semiconductor subassembly manufacturing process according to claim 12 is characterized in that hot temper in this step (i) is to carry out tempering in about 700 a ℃ boiler tube.
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| CNA021427062A CN1484297A (en) | 2002-09-18 | 2002-09-18 | Technology for mfg. semiconductor unit with improvement of leakage and resistance of deep submicron transistor |
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| CNA021427062A CN1484297A (en) | 2002-09-18 | 2002-09-18 | Technology for mfg. semiconductor unit with improvement of leakage and resistance of deep submicron transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461409C (en) * | 2004-09-30 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Device having multiple silicide types and a method for its fabrication |
| CN101165917B (en) * | 2006-10-18 | 2010-07-21 | 台湾积体电路制造股份有限公司 | MOS devices with continuous contact etch stop layer and its manufacture method |
-
2002
- 2002-09-18 CN CNA021427062A patent/CN1484297A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461409C (en) * | 2004-09-30 | 2009-02-11 | 台湾积体电路制造股份有限公司 | Device having multiple silicide types and a method for its fabrication |
| CN101165917B (en) * | 2006-10-18 | 2010-07-21 | 台湾积体电路制造股份有限公司 | MOS devices with continuous contact etch stop layer and its manufacture method |
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