CN1469485A - Logarithmic polar CMOS image sensor capable of eliminating pixel noise - Google Patents

Abstract

The logarithmic polar CMOS image sensor capable of eliminating inherent fixed pixel noise has the first to the fourth transistors, photodiode and current source. The first transistor has the grid connected to the first coupling end in the first node and the highest voltage. The second transistor has the grid connected to the second coupling end of the first transistor in the second node and the first coupling end connected to the highest voltage. The third transistor has the grid coupled to the line selecting signal, the first coupling end connected to the second coupling end of the second transistor, and the second coupling end as the voltage output end. The fourth transistor has the grid coupled to the control signal and the first coupling end connected to the second node. The photodiode is connected between the second coupling end and the earth. The current source is connected between the second coupling end of the third transistor and the earth.

Description

Logarithmic polar CMOS image sensor capable of eliminating pixel noise

Technical field

The invention relates to a kind of image sensor in CMOS (logarithmic mode CMOS image sensor) of logarithmic polar type, and particularly relevant for a kind of image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise (in-pixel fixed patternv noise).

Background technology

Good image sensor has high dynamic range except possessing (scope of irradiation amount is increased), low dark current (can be applicable to the environment of low-light (level)) and low power consumption (power dissipation) reads fast and random-access function also is a considerable ring.Picture is the most normal charge coupled cell that is used (Charge Coupled Device at present, be called for short CCD), though have high dynamic range and low dark current, but because its technology is special, therefore cost an arm and a leg, and its drive circuit need high voltage operation, so power consumption is very high, add the characteristic of itself element, and can't accomplish arbitrary access.

Relatively, image sensor in CMOS but has high-quantum efficiency (quantum efficiency), low noise (read noise), high dynamic range (dynamicrange) and the arbitrary access characteristics such as (random access) of reading, and a hundred per cent and CMOS (Complementary Metal Oxide Semiconductor) process compatible.Just charge coupled cell all cannot see on image sensor in CMOS in above-mentioned shortcoming, and the evolution of metal-oxide-semiconductor's technology certainly will will reduce cost, Pixel Dimensions and the consumed power of image sensor in CMOS greatly.So in recent years, image sensor in CMOS is used the substitute that has become charge coupled cell at many sensings of low price.

The image sensor in CMOS of logarithmic polar type promptly is wherein a kind of in the image sensor in CMOS, please refer to Fig. 1.The image sensor in CMOS of logarithmic polar type is mainly by nmos pass transistor 101,103,105 and optical diode 107 constitute.The image sensor in CMOS of this logarithmic polar type is mainly the grid that utilizes transistor 101 and directly receives ceiling voltage V _Dd, voltage difference and drain current formation logarithmic relationship between this moment transistor 101 grids and source electrode, this makes output voltage V _OutThe irradiation intensity of accepting with optical diode also forms logarithmic relationship, and therefore the image sensor in CMOS of this logarithmic polar type has very high dynamic range, and promptly image contrast is very strong.But, it also has when making read-out voltage, because technology makes critical voltage not match, and causes the very big puzzlement of steady noise.In addition, those skilled in the art as can be known, the image sensor in CMOS of this logarithmic polar type also can't be made correlated double sampling (Correlated Double Sampling, be called for short CDS) and eliminate steady noise.

The present invention then is the image sensor in CMOS itself at logarithmic polar type, the do not match shortcoming of the steady noise that causes of critical voltage, also be this logarithmic polar type the image sensor in CMOS maximum shortcoming and propose.

Summary of the invention

In view of this present invention proposes a kind of image sensor in CMOS of logarithmic polar type, can be when making correlated double sampling, effectively eliminate the steady noise that the inherent pixel of image sensor in CMOS of logarithmic polar type is produced, and improve the quality of gained image behind its sensing.

The present invention proposes a kind of image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise, comprising: first MOS transistor, second MOS transistor, the 3rd MOS transistor, the 4th MOS transistor, optical diode and current-source arrangement.Wherein first MOS transistor has gate terminal, first link and second link, and the gate terminal of the first transistor and first link are coupled to first node, and first node couples a ceiling voltage.Second MOS transistor has gate terminal, first link and second link, and second link of the gate terminal of second MOS transistor and first MOS transistor is coupled to Section Point, and first link of second MOS transistor also couples ceiling voltage.The 3rd MOS transistor has gate terminal, first link and second link, the gate terminal of the 3rd MOS transistor couples an array selecting signal, and first link of the 3rd MOS transistor couples second link of second MOS transistor, and second link of the 3rd MOS transistor is a voltage output end.The 4th MOS transistor has gate terminal, first link and second link, and the gate terminal of the 4th MOS transistor couples a control signal, and first link of the 4th MOS transistor couples Section Point.Optical diode has first link and second link, and first link of optical diode couples second link of the 4th MOS transistor, and second link of optical diode couples ground.

In preferred embodiment of the present invention, first MOS transistor, second MOS transistor, the 3rd MOS transistor and the 4th MOS transistor are N channel MOS transistor.It should be noted that the 4th MOS transistor also can be P channel MOS transistor.

Image sensor in CMOS corresponding to the above-mentioned logarithmic polar type of eliminating inherent pixel steady noise, the present invention proposes a kind of method of operation of image sensor in CMOS of the logarithmic polar type of eliminating inherent pixel steady noise, it comprises that when the 4th MOS transistor is accepted control signal with activation (enable) image sensor in CMOS of this logarithmic polar type is done the signal voltage sampling.And when the 4th MOS transistor was accepted control signal with forbidden energy (disable), the image sensor in CMOS of this logarithmic polar type was done the load voltage sampling.

In sum, the present invention only by increasing a MOS transistor, makes the image sensor in CMOS of logarithmic polar type can effectively eliminate the steady noise of inherent pixel.

Description of drawings

Fig. 1 is the ball bearing made using figure of the image sensor in CMOS of known logarithmic polar type; And

Fig. 2 is the ball bearing made using figure of the image sensor in CMOS of the logarithmic polar type of eliminating inherent pixel steady noise of preferred embodiment according to the present invention.

101,103,105,201,203,205, the 211:NMOS transistor

107,207: optical diode

109,209: current-source arrangement

Embodiment

Please refer to Fig. 2, in this preferred embodiment, the image sensor in CMOS of logarithmic polar type that can eliminate inherent pixel steady noise is by nmos pass transistor 201,203, and 205,211, optical diode 207 and current-source arrangement 209 constitute.

This operation principle of image sensor in CMOS of counting utmost point formula is as follows:

What at first will define is V _G201Represent grid voltage, the V of nmos pass transistor 201 _S201Represent source voltage, the V of NMOS crystal 2 01 _Th201Represent the critical voltage of NMOS crystal 2 01 ... by that analogy, I ₂₀₉The electric current of then representing current-source arrangement 209 to be provided.

According to the drain current formula of NMOS crystal when subcritical voltage (sub-threshold) is distinguished, can get electric current I and be $I=I_0\&CenterDot;\mathrm{Ecp}\left[\frac{V_{g201}-V_{s201}-{\mathrm{<figure-callout\; id="201"\; label="V\; th"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{th}}}{{\mathrm{nV}}_T}\right]----\left(1\right)$ Wherein, I ₀Be V _G201-V _S201During=0V, the leakage current of the nmos pass transistor 201 of flowing through.V _TBe thermal voltage (thermal voltage is equivalent to KT/q).By (1) formula can push away nV _T $\ln \left[\frac{I}{I_0}\right]=V_{g201}-V_{s201}-{\mathrm{<figure-callout\; id="201"\; label="V\; th"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{th}},$ Promptly ${\mathrm{<figure-callout\; id="201"\; label="V\; s"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_s=V_{g201}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I}{I_0}\right].$ Wherein, V _G201Be equivalent to ceiling voltage V _DdSo, ${\mathrm{<figure-callout\; id="201"\; label="V\; s"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_s=V_{\mathrm{dd}}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I}{I_0}\right]----\left(2\right)$ And nmos pass transistor 203 operates in saturation region (saturation region), and clearly, the drain current of nmos pass transistor 203 is equivalent to the electric current I that current-source arrangement 209 is provided ₂₀₉, therefore, electric current I ₂₀₉Equal the source current of nmos pass transistor 203.The source current that can get nmos pass transistor 203 according to the source current formula of nmos pass transistor saturation region is $\frac{1}{2}{K}_{P203}{(V_{g203}-V_{s203}-V_{\mathrm{th}203})}^2,$ Be equivalent to electric current I ₂₀₉, promptly ${\mathrm{<figure-callout\; id="209"\; label="I"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">I</figure-callout>}}_{209}=\frac{1}{2}{K}_{P203}{(V_{g203}-V_{s203}-V_{\mathrm{th}203})}^2.$ So push away $\sqrt{\frac{{2I}_{209}}{{\mathrm{<figure-callout\; id="203"\; label="K\; P"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">K</figure-callout>}}_P}}=V_{g203}-V_{s203}-{\mathrm{<figure-callout\; id="203"\; label="V\; th"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{th}}.$ Again, under ideal state, V _S203Be equivalent to the output voltage V that this counts the image sensor in CMOS of utmost point formula _OutSo $V_{\mathrm{out}}={\mathrm{<figure-callout\; id="203"\; label="V\; s"\; filenames="A0212622500151.png"\; state="\{\{state\}\}">V</figure-callout>}}_s=V_{g203}-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(3\right)$ Wherein, K _P203Component parameters for nmos pass transistor 203.Because V _S201=V _G203, therefore take (2) formula to (3) formula, can get $V_{\mathrm{out}}=V_{\mathrm{dd}}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I}{I_0}\right]-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(4\right)$

When optical diode 207 is accepted low light level irradiation (nmos pass transistor 201 operates in time sintering (sub-threshold region)), and nmos pass transistor 211 is when receiving control signals and being controlled to be forbidden energy (OFF), electric current I, the just anti-leakage current I partially of node 1 _Rev1When therefore optical diode 207 is accepted low light level irradiation and nmos pass transistor 211 forbidden energy, the output voltage V of the image sensor in CMOS of logarithmic polar type _Out11, promptly the image sensor in CMOS of logarithmic polar type is made the load voltage of correlated double sampling when (Correlated DoubleSampling is called for short CDS), for $V_{\mathrm{out}11}=V_{\mathrm{dd}}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I_{\mathrm{rev}1}}{I_0}\right]-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(5\right)$

When optical diode 207 is accepted low light level irradiation, and nmos pass transistor 211 is when receiving control signals and being controlled to be activation (ON), the photoelectric current I that electric current I is produced when being equivalent to optical diode 207 irradiations _P1Add the anti-leakage current I partially that node 1 is produced _Rev1(leakage current that this is not produced during irradiation for optical diode).When therefore optical diode 207 is accepted low light level irradiation and nmos pass transistor 211 activations, the output voltage V of the image sensor in CMOS of logarithmic polar type _Out12, the signal voltage when promptly making CDS during the image sensor in CMOS of logarithmic polar type, for $V_{\mathrm{out}12}=V_{\mathrm{dd}}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I_{P1}+I_{\mathrm{rev}1}}{I_0}\right]-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(6\right)$

So when optical diode 207 is accepted low light level when irradiation, nmos pass transistor 211 suspension control signal activation or forbidden energy are taken a sample to load voltage and signal voltage and subtracted each other to cooperate the CDS circuit, and obtain pure signal voltage, this pure signal voltage is $|V_{\mathrm{out}12}-V_{\mathrm{out}11}|=n{V}_T\ln \left[\frac{I_{P1}+I_{\mathrm{rev}1}}{I_{\mathrm{rev}1}}\right]----\left(7\right)$

Similarly, when optical diode 207 is accepted strong illumination (nmos pass transistor 201 operates in saturation region (saturation region)), and nmos pass transistor 211 is when receiving control signals and being controlled to be forbidden energy (OFF), electric current I, the just anti-leakage current I partially of node 1 _Rev1When therefore optical diode 207 is accepted strong illumination and nmos pass transistor 211 forbidden energy, the output voltage V of the image sensor in CMOS of logarithmic polar type _Out21For $V_{\mathrm{out}21}=V_{\mathrm{dd}}-V_{\mathrm{th}201}-{\mathrm{nV}}_T\ln \left[\frac{I_{\mathrm{rev}1}}{I_0}\right]-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(8\right)$

When optical diode 207 is accepted strong illumination, and nmos pass transistor 211 is when receiving control signals and being controlled to be activation (ON), the output voltage V of the image sensor in CMOS of logarithmic polar type _Out22For $V_{\mathrm{out}22}=V_{\mathrm{dd}}-V_{\mathrm{th}201}-\sqrt{\frac{{2I}_{p1}+I_{\mathrm{rev}1}}{K_{P201}}}-V_{\mathrm{th}203}-\sqrt{\frac{{2I}_{209}}{K_{P203}}}----\left(9\right)$

So when optical diode 207 was accepted strong illumination, nmos pass transistor 211 suspension control signal activation or forbidden energy were taken a sample to reset voltage and signal voltage and are subtracted each other to cooperate the CDS circuit, and obtain pure signal voltage, so pure signal voltage is $|V_{\mathrm{out}22}-V_{\mathrm{out}21}|=\sqrt{\frac{{2I}_{p1}+I_{\mathrm{rev}1}}{I_0}}-{\mathrm{nV}}_T\ln \left[\frac{I_{\mathrm{rev}1}}{I_0}\right]----\left(10\right)$

By above-mentioned (7) formula and (10) formula as can be known, critical voltage variation (Thresholdvoltage variation) is eliminated, so can eliminate the steady noise (fixed pattern noise, abbreviation FPN) that does not match and cause because of critical voltage.

Therefore, in this preferred embodiment according to the present invention, become the output voltage V of image sensor in CMOS of the logarithmic polar type of logarithmic relationship with the illumination of optical diode 207 light that receives _OutControl by array selecting signal, do sampling and make signal voltage and load voltage when subtracting each other to export to correlating double sampling circuit by nmos pass transistor, because the unmatched elimination of each transistor critical voltage in the image sensor in CMOS of logarithmic polar type, and improved the quality of last output voltage.

In addition, it should be noted that ceiling voltage V _DdFor different according to the technology of image sensor in CMOS of the logarithmic polar type that can eliminate inherent pixel steady noise, during as 0.25 μ m technology, ceiling voltage V _DdBe 2.5 volts, during 0.35 μ m technology, ceiling voltage V _DdWhen being 3.3 volts or 0.5 μ m technology, ceiling voltage V _DdIt is 5 volts.

Comprehensively above-mentioned, the present invention is only by increasing a MOS transistor, make the image sensor in CMOS of logarithmic polar type when doing relevant two-phase sampling, in the time of can effectively eliminating its output voltage output, critical voltage variation and steady noise that inherent pixel is produced, make its output voltage, the image quality of its output just improves greatly.

Claims (10)

1. the image sensor in CMOS that can eliminate the logarithmic polar type of inherent pixel steady noise is characterized in that, this transducer comprises:

One first MOS transistor has gate terminal, first link and second link, and the gate terminal of this first transistor and first link are coupled to a first node, and this first node couples a ceiling voltage;

One second MOS transistor, have gate terminal, first link and second link, second link of the gate terminal of this second MOS transistor and this first MOS transistor is coupled to a Section Point, and first link of this second MOS transistor couples this ceiling voltage;

One the 3rd MOS transistor, have gate terminal, first link and second link, the gate terminal of the 3rd MOS transistor couples an array selecting signal, and first link of the 3rd MOS transistor couples second link of this second MOS transistor, and second link of the 3rd MOS transistor is a voltage output end;

One the 4th MOS transistor has gate terminal, first link and second link, and the gate terminal of the 4th MOS transistor couples a control signal, and first link of the 4th MOS transistor couples this Section Point; And

One optical diode has first link and second link, and first link of this optical diode couples second link of the 4th MOS transistor, and second link of this optical diode couples ground.

2. the image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise as claimed in claim 1 is characterized in that, the image sensor in CMOS of this logarithmic polar type more comprises:

One current-source arrangement has first link and second link, and first link of this current-source arrangement couples second link of the 3rd MOS transistor, and second link of this current-source arrangement couples ground.

3. the image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise as claimed in claim 1, it is characterized in that this first MOS transistor, this second MOS transistor, the 3rd MOS transistor and the 4th MOS transistor are a N channel MOS transistor.

4. the image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise as claimed in claim 1 is characterized in that, the 4th MOS transistor is a P channel MOS transistor.

5. the image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise as claimed in claim 1, it is characterized in that, one ideally, the voltage of second link of this transistor seconds equates with the voltage of this voltage output end.

6. the image sensor in CMOS of eliminating the logarithmic polar type of inherent pixel steady noise as claimed in claim 3 is characterized in that, this ceiling voltage is between between 5 volts and the transistorized critical voltage of this N channel NOS.

7. the method for operation of the image sensor in CMOS of the logarithmic polar type that can eliminate inherent pixel steady noise, the image sensor in CMOS of this logarithmic polar type comprises one first MOS transistor, one second MOS transistor, one the 3rd MOS transistor, one the 4th MOS transistor, an optical diode and a current-source arrangement; Wherein this first MOS transistor has gate terminal, first link and second link, and the gate terminal of this first transistor and first link are coupled to a first node, and this first node couples a ceiling voltage; This second MOS transistor has gate terminal, first link and second link, second link of the gate terminal of this second MOS transistor and this first MOS transistor is coupled to a Section Point, and first link of this second MOS transistor couples this ceiling voltage; The 3rd MOS transistor has gate terminal, first link and second link, the gate terminal of the 3rd MOS transistor couples an array selecting signal, and first link of the 3rd MOS transistor couples second link of this second MOS transistor, and second link of the 3rd MOS transistor is a voltage output end; The 4th MOS transistor has gate terminal, first link and second link, and the gate terminal of the 4th MOS transistor couples a control signal, and first link of the 4th MOS transistor couples this Section Point; This optical diode has first link and second link, and first link of this optical diode couples second link of the 4th MOS transistor, and second link of this optical diode couples ground; This current-source arrangement has first link and second link, and first link of this current-source arrangement couples second link of the 3rd MOS transistor, and second link of this current-source arrangement couples ground; It is characterized in that its method of operation comprises:

When the 4th MOS transistor was accepted this control signal with activation, the image sensor in CMOS of this logarithmic polar type was done signal voltage sampling; And

When the 4th MOS transistor was accepted this control signal with forbidden energy, the image sensor in CMOS of this logarithmic polar type was done load voltage sampling.

8. the method for operation of the image sensor in CMOS of the logarithmic polar type of eliminating inherent pixel steady noise as claimed in claim 7, it is characterized in that, this signal voltage is for when the 4th MOS transistor activation, the voltage of this voltage output end, this load voltage is when the 4th MOS transistor forbidden energy, the voltage of this voltage output end.

9. the method for operation of the image sensor in CMOS of the logarithmic polar type of eliminating inherent pixel steady noise as claimed in claim 7, it is characterized in that, when the image sensor in CMOS of this logarithmic polar type was done this signal voltage and the sampling of this load voltage, the voltage of second link of this transistor seconds equated with the voltage of this voltage output end.

10. the method for operation of the image sensor in CMOS of the logarithmic polar type of eliminating inherent pixel steady noise as claimed in claim 7, it is characterized in that, when the image sensor in CMOS of this logarithmic polar type was done the sampling of this signal voltage and this load voltage, this ceiling voltage was between between 5 volts and the transistorized critical voltage of this N channel NOS.

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