CN107404622A - Automatic voltage amplifying device and automatic voltage amplifying method - Google Patents
Automatic voltage amplifying device and automatic voltage amplifying method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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Abstract
The invention provides an automatic voltage amplifying device and an automatic voltage amplifying method, wherein the automatic voltage amplifying device comprises an output end, a sensor, a first transistor, a second transistor, a third transistor and a fourth transistor. The sensor receives an input voltage and outputs a DC output voltage. The first transistor is coupled to the sensor and receives the DC output voltage. The second transistor is coupled to the sensor and the first transistor at the first contact and the second contact, respectively. The third transistor is coupled between the first node and a ground terminal. The fourth transistor is coupled between the second contact and the output end. The input voltage increases with time and the dc output voltage rises synchronously with the input voltage.
Description
Technical field
The present invention is relevant with CIS, amplifies dress especially with respect to a kind of automatic voltage applied to CIS
Put and automatic voltage amplification method.
Background technology
In recent years, complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor,
CMOS) CIS has been widely used in numerous electronic products, such as smart mobile phone, digital camera, camera with recording device
Deng.
In general, CMOS CISs are mainly divided into two major classes：Passive type picture-element sensor as shown in Figure 1
(Passive Pixel Sensor, PPS) and active pixel sensor (Active Pixel as shown in Figure 2
Sensor,APS).Although the passive type picture-element sensor PPS in Fig. 1 only has high fill-ratio comprising a transistor M1,
Due to the high request for image output speed and quality now can not be met, therefore it has been rarely employed.Instead in Fig. 2
Active pixel sensor APS can effectively lift reading speed and signal noise ratio, but due to its include three transistor M1~
M3, also result in filling rate thus reduce.
In actual applications, the active pixel sensing in passive type the picture-element sensor PPS or Fig. 2 either in Fig. 1
Device APS, it is both needed to be provided with the amplifying circuit 4 shown in amplifying circuit 3 or Fig. 4 as shown in Figure 3 outside it to realize amplification
The function of voltage, the increase of cost is not only resulted in, higher element sensitivity and larger voltage range can not be also provided.
The content of the invention
In view of this, the present invention proposes a kind of automatic voltage amplifying device and automatic voltage amplification method, effectively to solve
The above-mentioned variety of problems that prior art is suffered from.
A specific embodiment according to the present invention is a kind of automatic voltage amplifying device.In this embodiment, automatic voltage
Amplifying device includes output end, sensor, the first transistor, second transistor, third transistor and the 4th transistor.Sensor
To receive an input voltage and export a VD.The first transistor couples sensor and receives direct current output electricity
Pressure.Second transistor is coupled to the first contact and the second contact with sensor and the first transistor respectively.Third transistor couples
Between the first contact and earth terminal.4th transistor couples are between the second contact and output end.Input voltage with the time and
Increase and VD is according to input voltage synchronization lifting.
In an embodiment, in very first time section, second transistor and third transistor is open and the 4th crystal
Manage to close, input voltage increases to the first level by initial level.It is second transistor, the 3rd brilliant in the second time interval
Body pipe and the 4th transistor are to close, and input voltage increases to the second level by the first level.In in the 3rd time interval,
Two-transistor is unlatching and third transistor and the 4th transistor are closing, and input voltage increases to the 3rd standard by the second level
Position.
In an embodiment, VD in the very first time section with it is linear with first rate in the second time interval
Increase, and VD in the 3rd time interval with the second rate linear increase, wherein the second speed be more than first
Speed.
In an embodiment, in the 4th time interval, second transistor and third transistor are closing and the 4th crystal
To manage to open, input voltage increases to the 4th level by the 3rd level, and VD is linearly increasing with third speed, and the 3rd
Speed is more than the second speed.
In an embodiment, it is equal to the 4th time interval in the output voltage that in the 4th time interval, output end is exported
Input voltage plus the 3rd time interval input voltage subtract again twice the first transistor critical voltage.
In an embodiment, automatic voltage amplifying device further includes the 5th transistor, is coupled to the first contact and
Between two-transistor, the 5th transistor in the 4th time interval for open.
In an embodiment, in the very first time section with the second time interval in, the first junction voltage of the first contact with
Second junction voltage of the second contact is zero.
In an embodiment, in the 3rd time interval, the first junction voltage of the first contact and the second of the second contact
Junction voltage is equal to the critical voltage that input voltage subtracts the first transistor.
Another specific embodiment according to the present invention is a kind of automatic voltage amplification method.In this embodiment, automatic electric
Pressure amplification method is applied to an automatic voltage amplifying device.Automatic voltage amplifying device include a sensor, a first transistor,
One second transistor, a third transistor, one the 4th transistor and an output end.Sensor is respectively coupled to the first transistor and
Three transistors.Second transistor is respectively coupled to one first contact between sensor and third transistor and positioned at first
One second contact between transistor, second transistor and the 4th transistor.4th transistor couples are in the second contact and output
Between end.Sensor receives an input voltage and exports a VD to the first transistor.
Automatic voltage amplification method comprises the steps of：(a) in opening second transistor and the 3rd in very first time section
Transistor simultaneously closes the 4th transistor；(b) in closing second transistor, third transistor and the 4th crystal in the second time interval
Pipe；And (c) in unlatching second transistor in the 3rd time interval and closes third transistor and the 4th transistor.Wherein, it is defeated
Enter that voltage increases with the time and VD is according to input voltage synchronization lifting.
Compared to prior art, being provided according to the automatic voltage amplifying device of the present invention and automatic voltage amplification method can
The charging circuit for improving voltage quasi position gives active pixel sensor (APS), is not required to outside it additionally set amplifying circuit i.e.
The function of automatic voltage amplification can be realized, therefore can effectively save cost and improve its element sensitivity and voltage range.
It can be obtained further by following detailed description of the invention and institute's accompanying drawings on the advantages and spirit of the present invention
Solution.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only
Some embodiments of the present invention, for those of ordinary skill in the art, without having to pay creative labor, also
Other accompanying drawings can be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram of traditional passive type picture-element sensor.
Fig. 2 is the schematic diagram of traditional active pixel sensor.
Fig. 3 and Fig. 4 is the schematic diagram for the amplifying circuit that setting is needed outside traditional active pixel sensor.
Fig. 5 is the schematic diagram according to the automatic voltage amplifying device of the preferred embodiment of the present invention.
Fig. 6 A to Fig. 6 D illustrate automatic voltage amplifying device in Fig. 5 in the very first time time interval of section~the 4th respectively
Interior operation situation.
Fig. 7 is in the signal timing diagram in the very first time time interval of section~the 4th.
Fig. 8 is another 4th crystalline substance that extra setting is controlled by the 3rd clock signal between the first contact and second transistor
The schematic diagram of body pipe.
Fig. 9 is another embodiment of automatic voltage amplifying device.
Figure 10 is the flow chart according to the automatic voltage amplification method of another preferred embodiment of the present invention.
Drawing reference numeral：
RST：Reset signal
SEL：Selection signal
VRST：Reset voltage
Vin：Input voltage
Vout：Output voltage
AMP：Amplifier
Rin、Rf、R：Resistance
C：Electric capacity
5：Automatic voltage amplifying device
SEN：Sensor
M1：The first transistor
M2：Second transistor
M3：Third transistor
M4：4th transistor
M4’：Another 4th transistor M5：5th transistor
CLK1：First clock signal
CLK2：Second clock signal
CLK3：3rd clock signal
CLK4：3rd clock signal
N1：First contact
N2：Second contact
N3：3rd contact
IN：Input
OUT：Output end
VDD：Operating voltage
C1：Electric capacity
Cout：Output capacitance
VC1：First junction voltage
VC2：Second junction voltage
DCout：VD
T0~t4：Time
△ T1~△ T4：The very first time time interval of section~the 4th
Vin1~Vin4：The very first time section the time interval of input voltage~the 4th input voltage
V0~V4：The level of initial level, the first level~the 4th
S10~S16：Step
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, the every other reality that relevant technical staff in the field is obtained under the premise of creative work is not made
Example is applied, belongs to the scope of the protection of the present invention.
A preferred embodiment according to the present invention is a kind of automatic voltage amplifying device.In this embodiment, automatically
The charging circuit that the offer of voltage amplification device can improve voltage quasi position gives active pixel sensor (APS), and it is automatic to use realization
The function of voltage amplification simultaneously effectively improves its element sensitivity and voltage range.
Fig. 5 is refer to, Fig. 5 is the schematic diagram of the automatic voltage amplifying device in this embodiment.
As shown in figure 5, automatic voltage amplifying device 5 can include input IN, output end OUT, sensor SEN, the first crystalline substance
Body pipe M1, second transistor M2, third transistor M3, the 4th transistor M4, electric capacity C1, output capacitance Cout, the first contact N1
And the second contact N2.Sensor SEN is respectively coupled to input IN, the first contact N1 and the first transistor M1 grid；First is brilliant
Body pipe M1 is coupled between operating voltage VDD and the second contact N2 and its grid coupling sensor SEN；Second transistor M2 is coupled
Between the first contact N1 and the second contact N2；Third transistor M3 is coupled between the first contact N1 and earth terminal；4th is brilliant
Body pipe M4 is coupled between the second contact N2 and output end OUT；Electric capacity C1 one end is coupled to second transistor M2 and connect with first
Between point N1 and the other end is coupled to earth terminal；Output capacitance Cout one end is coupled to the 4th transistor M4 and output end OUT
Between and the other end be coupled to earth terminal.
In this embodiment, coupling input IN sensor SEN receives an input voltage vin and exports a direct current output
Voltage DCout to the first transistor M1 grid.Therefore, the first transistor M1 be turned on and off be controlled by VD
DCout.In fact, sensor SEN can be a CIS, but it is not limited.
Second transistor M2 grid receives the second clock signal CLK2, that is, second transistor M2 be turned on and off by
Control in the second clock signal CLK2；Third transistor M3 grid receives the first clock signal CLK1, that is, third transistor M3
Be turned on and off be controlled by the first clock signal CLK1；4th transistor M4 grid receives the 3rd clock signal CLK3, also
That is the 4th transistor M4's is turned on and off being controlled by the 3rd clock signal CLK3.Positioned at sensor SEN, second transistor M2 and
The first contact N1 between third transistor M3 has the first junction voltage VC1；Positioned at the first transistor M1, second transistor M2
And the 4th the second contact N2 between transistor M4 has the second junction voltage VC2；Output end OUT has output voltage Vout.
Then, the automatic voltage illustrated respectively referring to Fig. 6 A to Fig. 6 D and Fig. 7, Fig. 6 A to Fig. 6 D in Fig. 5 amplifies
Device 5 is in the operation situation in the time interval △ T4 of very first time section △ T1~the 4th；Fig. 7 is in very first time section △ T1
Signal timing diagram in~the four time interval △ T4.
It should be noted that the initial level V0, the first level V1, the second level V2, the 3rd level V3 and the 4th in Fig. 7 are accurate
Position V4 is respectively level of the input voltage vin in time t0, t1, t2, t3 and t4, because the 4th level V4 is higher than the 3rd level
V3, the 3rd level V3 are higher than initial level higher than the second level V2, the second level V2 higher than the first level V1 and the first level V1
V0, so input voltage vin increases since time t0 to time t4 with the time.As for very first time section △ T1 from the time
T0 starts untill time t1, can be referred to as " reading the stage "；Second time interval △ T2 are to time t2 since time t1
Only, " reset phase " can be referred to as；3rd time interval △ T3 untill time t3, can be referred to as " feedback since time t2
Input phase "；4th time interval △ T4 untill time t4, can be referred to as " output stage " since time t3.
From Fig. 6 A and Fig. 7：In very first time section △ T1 (that is, since time t0 untill time t1 " read
Take the stage ") in, because the first clock signal CLK1 and the second clock signal CLK2 are in high levle and the 3rd clock signal CLK3
In low level, therefore, be controlled by the first clock signal CLK1 and the second clock signal CLK2 third transistor M3 with
It is to close (OFF) that second transistor M2, which is unlatching (ON) and is controlled by the 3rd clock signal CLK3 the 4th transistor M4,.Now,
First contact N1 the first junction voltage VC1 and the second contact N2 the second junction voltage VC2 are 0；Assuming that very first time area
Between △ T1 input voltage vin be Vin1, then when Vin1 can be linearly increasing to time t1 by initial level V0 during time t0
First level V1, wherein the first level V1 is higher than initial level V0；Because the 4th transistor M4 is in very first time section △ T1
It is closed, therefore output voltage Vout is 0.
From Fig. 6 B and Fig. 7：In the second time interval △ T2 (that is, since time t1 untill time t2 " weight
Put the stage ") in, because the first clock signal CLK1, the second clock signal CLK2 and the 3rd clock signal CLK3 are in low standard
Position, therefore, be controlled by the first clock signal CLK1, the second clock signal CLK2 and the 3rd clock signal CLK3 the 3rd are brilliant
Body pipe M3, second transistor M2 and the 4th transistor M4 are to close (OFF).Now, the first contact N1 the first junction voltage
VC1 and the second contact N2 the second junction voltage VC2 is 0；Assuming that the second time interval △ T2 input voltage vin is
Vin2, then the second level V2 when Vin2 can be linearly increasing to time t2 by the first level V1 during time t1, wherein second is accurate
Position V2 is higher than the first level V1；Because the 4th transistor M4 in the second time interval △ T2 in still in closed mode, therefore exporting
Voltage Vout is also maintained 0.
It should be noted that in very first time section △ T1 and the second time interval △ T2, input voltage vin can first from
Initial level Vo during time t0 is linearly increasing to the first level V1 during time t1, be further continued for from time t1 when the first level
V1 is linearly increasing to the second level V2 during time t2, and VD DCout is in meeting etc. in very first time section △ T1
In very first time section △ T1 input voltage vin 1 and in the second time interval △ T2 can be equal in the second time interval △ T2
Input voltage vin 2, therefore VD DCout also can be linearly increasing with first rate therewith, that is, the direct current in Fig. 7
Output voltage DCout curves are in time t0 to having first slope between t2.
Then, from Fig. 6 C and Fig. 7：In the 3rd time interval △ T3 (that is, since time t2 untill time t3
" feed back input stage ") in, because the second clock signal CLK2 from low level is changed into high levle, and the first clock signal
CLK1 and the 3rd clock signal CLK3 are still maintained at low level, and therefore, second transistor M2 is unlatching (ON) and third transistor
M3 and the 4th transistor M4 is closing (OFF).Now, the of the first contact N1 the first junction voltage VC1 and the second contact N2
Two point voltage VC2 can be equal to the second time interval △ T2 input voltage vin subtract the first transistor M1 critical voltage
(Vth)；Because the 4th transistor M4 is in, still in closed mode, therefore output voltage Vout is also maintained in the 3rd time interval △ T3
For 0.
It should be noted that, it is assumed that the 3rd time interval △ T3 input voltage vin is Vin3, then the 3rd time interval △ T3
Interior VD DCout can be equal to the 3rd time interval △ T3 input voltage vin 3, due to the 3rd time interval △
T3 input voltage vin 3 can be linearly increasing to the 3rd level V3 by the second level V2, wherein the 3rd level V3 is higher than the second level
V2, therefore, the VD DCout in the 3rd time interval △ T3 can be according to the 3rd time interval △ T3 input voltage
Vin3 increase and synchronous lifting.In this embodiment, the VD DCout in the 3rd time interval △ T3 is with second
Rate linear increase, and the second speed can be more than first rate, that is, the VD DCout curves in Fig. 7 in when
Between t2 to having the second slope between t3, and the absolute value of the second slope can be more than the absolute value of first slope.
From Fig. 6 D and Fig. 7：It is (that is, " defeated untill time t4 since time t3 in the 4th time interval △ T4
Go out the stage ") in, the first clock signal CLK1, the second clock signal CLK2 be in low level and at the 3rd clock signal CLK3
In high levle, that is, second transistor M2 and third transistor M3 are to close (OFF) and the 4th transistor M4 be unlatching (ON).It is false
If the 4th time interval △ T4 input voltage vin is Vin4, then the VD DCout in the 4th time interval △ T4
Input voltage vin 4 that can be equal to the 4th time interval △ T4 adds the first junction voltage VC1, that is, is equal to the 4th time interval
△ T4 input voltage vin 4 subtracts the first transistor M1 critical electricity plus the 3rd time interval △ T3 input voltage vin 3
Press (Vth), because the 4th time interval △ T4 input voltage vin 4 can increase to the 4th level V4 by the 3rd level V3, wherein
4th level V4 is higher than the 3rd level V3, along with the 3rd time interval △ T3 input voltage vin 3 is linear by the second level V2
The 3rd level V3 is increased to, therefore, the VD DCout in the 4th time interval △ T4 can be according to the 3rd time interval
The increase of △ T3 input voltage vin 3 and the 4th time interval △ T4 input voltage vin 4 and synchronous lifting.In this embodiment
In, the VD DCout in the 4th time interval △ T4 can be linearly increasing with third speed, and third speed can be big
In the second speed, that is, the VD DCout curves in Fig. 7 in time t3 to having the 3rd slope between t4, and
The absolute value of 3rd slope can be more than the absolute value of the second slope.
It should be noted that due to the 4th transistor M4 in the 4th time interval △ T4 in open (ON) state so that
4th time interval △ T4 output voltage Vout is not 0, but can be equal to the 4th time interval △ T4 VD
DCout subtracts the first transistor M1 critical voltage (Vth), and from the above：4th time interval △ T4 direct current output
Voltage DCout is equal to the 4th time interval △ T4 input voltage of the input voltage vin 4 plus the 3rd time interval △ T3 again
Vin3 subtracts the first transistor M1 critical voltage (Vth), and therefore, the 4th time interval △ T4 output voltage Vout can be equal to
4th time interval △ T4 input voltage vin 4 subtracts twice again plus the 3rd time interval △ T3 input voltage vin 3
The first transistor M1 critical voltage (Vth).
For further, because the 4th time interval △ T4 input voltage vin 4 can be linearly increasing by the 3rd level V3
The 3rd level can be linearly increasing to by the second level V2 to the 4th level V4 and the 3rd time interval △ T3 input voltage vin 3
V3, so the output voltage Vout that the output end OUT of automatic voltage amplifying device 5 is exported in the 4th time interval △ T4
By by the time interval △ T3 of input voltage vin 4 and the 3rd of the 4th linearly increasing time interval △ T4 input voltage
The effect of superposition effect that Vin3 is added automatically achieves voltage amplification and purpose.
In another embodiment, as shown in figure 8, automatic voltage amplifying device 5 also can further include and be coupled to first and connect
Another 4th transistor M4 ' between point N1 and second transistor M2, and when this another 4th transistor M4 ' is controlled by the 3rd
Arteries and veins signal CLK3, that is, this another 4th transistor M4 ' in being in very first time section △ T1 to the 3rd time interval △ T3
Close (OFF), but in being unlatching (ON) in the 4th time interval △ T4, use the direct current prevented in the 4th time interval △ T4
Output voltage DCout and output voltage Vout are excessive, to avoid causing the phenomenon of fault to occur because voltage is excessive.
In another embodiment, as shown in figure 9, sensor SEN also may be disposed at the first contact N1 and the 3rd contact N3 it
Between, and the first transistor M1 grid couples the 3rd contact N3.Automatic voltage amplifying device can further include the 5th crystal
Pipe M5, be coupled between operating voltage VDD and the 3rd contact N3 and be controlled by the 4th clock signal CLK4, but not as
Limit.
Another specific embodiment according to the present invention is a kind of automatic voltage amplification method.In this embodiment, automatic electric
Pressure amplification method is applied to automatic voltage amplifying device.Automatic voltage amplifying device includes sensor, the first transistor, the second crystalline substance
Body pipe, third transistor, the 4th transistor and output end.Sensor is respectively coupled to the first transistor and third transistor.Second
Transistor is respectively coupled to the first contact between sensor and third transistor and positioned at the first transistor, the second crystal
The second contact between the transistors of Guan Yu tetra-.4th transistor couples are between the second contact and output end.Sensor receives
Input voltage simultaneously exports VD to the first transistor.The first transistor is controlled by the direct current output that sensor is exported
Voltage；Second transistor is controlled by the second clock signal；Third transistor is controlled by the first clock signal；4th transistor is controlled
In the 3rd clock signal.Wherein, input voltage can increase with the time, and VD can be synchronous according to input voltage
Lifting.
Figure 10 is refer to, Figure 10 is the flow chart of the automatic voltage amplification method in this embodiment.As shown in Figure 10, it is first
First, in very first time section, this method performs step S10：Open second transistor and third transistor and the crystalline substance of closing the 4th
Body pipe.Now, input voltage can increase to the first level by initial level, wherein the first level is higher than initial level.
Then, in the second time interval, this method performs step S12：Close second transistor, third transistor and the
Four transistors.Now, input voltage can increase to the second level by the first level, wherein the second level is higher than the first level.
It should be noted that in the very first time section with the second time interval, the first junction voltage of the first contact and the
Second junction voltage of two point is zero.Due to input voltage in the very first time section with can by initial in the second time interval
Level increases to the first level so that is exported by sensor to the VD of the first transistor (DCout) in first when
Between can synchronously be increased according to input voltage in section and the second time interval.In this embodiment, VD is in
One time interval is interior linearly increasing with first rate with the second time interval.
Then, in the 3rd time interval, this method performs step S14：Open second transistor and close the 3rd crystal
Pipe and the 4th transistor.Now, input voltage can increase to the 3rd level by the second level, wherein the 3rd level is accurate higher than second
Position.
It should be noted that in the 3rd time interval, due to the first contact the first junction voltage and the second contact
Two point voltage is equal to the critical voltage that input voltage subtracts the first transistor, and input voltage is in the 3rd time interval
3rd level can be increased to by the second level so that exported by sensor to the VD of the first transistor (DCout)
In meeting synchronous lifting according to input voltage in the 3rd time interval.In this embodiment, VD is in the 3rd time
With the increase of the second rate linear in section, wherein the second speed is more than first rate.That is, VD
(DCout) linearly increasing speed can increase to for the 3rd time by very first time section with the first rate in the second time interval
The second speed in section.
Afterwards, in the 4th time interval, this method performs step S16：Close second transistor and third transistor simultaneously
Open the 4th transistor.Now, input voltage increases to the 4th level by the 3rd level, wherein the 4th level is accurate higher than the 3rd
Position.
It should be noted that in the 4th time interval, output voltage that the output end of automatic voltage amplifying device is exported
(Vout) it is equal to the input voltage (Vin) in the 4th time interval plus the input voltage (Vin) in the 3rd time interval again to subtract
Remove the critical voltage of twice of the first transistor.Because the input voltage in the 3rd time interval can be increased to by the second level
Input voltage in three levels and the 4th time interval can increase to the 4th level by the 3rd level so that VD
(DCout) in meeting synchronous lifting according to the increase of input voltage in the 4th time interval.In this embodiment, direct current output electricity
It is interior linearly increasing with third speed to be pressed on the 4th time interval, wherein third speed is more than the second speed.That is, direct current is defeated
Going out the linearly increasing speed of voltage (DCout) can further increase to for the 4th time by the second speed in the 3rd time interval
Third speed in section.
In practical application, automatic voltage amplifying device, which also can further include, is coupled to the first contact and second transistor
Between the 5th transistor, and the 5th transistor is controlled by the 3rd clock signal.Therefore, the 5th transistor is in very first time area
Between to being to close in the 3rd time interval, and the 5th transistor in the 4th time interval to open.
Compared to prior art, being provided according to the automatic voltage amplifying device of the present invention and automatic voltage amplification method can
The charging circuit for improving voltage quasi position gives active pixel sensor (APS), is not required to outside it additionally set amplifying circuit i.e.
The function of automatic voltage amplification can be realized, therefore can effectively save cost and improve its element sensitivity and voltage range.
By the above detailed description of preferred embodiments, it would be desirable to the feature and spirit of the present invention is more clearly described, and simultaneously
It is non-that scope of the invention is any limitation as with above-mentioned disclosed preferred embodiment.On the contrary, the purpose is to wish to
Cover various changes and have being arranged in the category of the scope of the claims to be applied of the invention of equality.Preferably have more than
The detailed description of body embodiment, it would be desirable to the feature and spirit of the present invention is more clearly described, and not with above-mentioned disclosed preferable
Specific embodiment is any limitation as to scope of the invention.On the contrary, the purpose is to wish to cover various changes and have equal
Property be arranged in the category of the scope of the claims to be applied of the invention.
Claims (16)
1. a kind of automatic voltage amplifying device, it is characterised in that include：
One output end；
One sensor, to receive an input voltage and export a VD；
One the first transistor, couple the sensor and receive the VD；
One second transistor, one first contact and one second contact are coupled to the sensor and the first transistor respectively；
One third transistor, it is coupled between first contact and an earth terminal；And
One the 4th transistor, it is coupled between second contact and the output end；
Wherein, the input voltage increases with the time and the VD is according to the input voltage synchronization lifting.
2. automatic voltage amplifying device as claimed in claim 1, it is characterised in that in a very first time section, this second
The transistor AND gate third transistor is unlatching and the 4th transistor is closing, and the input voltage increases to one by an initial level
First level；In in one second time interval, the second transistor, the third transistor and the 4th transistor are to close,
The input voltage increases to one second level by first level；In in one the 3rd time interval, the second transistor is unlatching
And the third transistor and the 4th transistor is close, the input voltage increases to one the 3rd level by second level.
3. automatic voltage amplifying device as claimed in claim 2, it is characterised in that the VD is in the very first time
Section is with linearly increasing with a first rate in second time interval, and the VD is in the 3rd time interval
Interior to be increased with one second rate linear, wherein second speed is more than the first rate.
4. automatic voltage amplifying device as claimed in claim 3, it is characterised in that in one the 4th time interval, this second
Transistor and the third transistor are closing and the 4th transistor is unlatching, and the input voltage increases to one by the 3rd level
4th level, the VD is linearly increasing with a third speed, and the third speed is more than second speed.
5. automatic voltage amplifying device as claimed in claim 4, it is characterised in that in the 4th time interval, the output
The exported output voltage in end is equal to the input of the input voltage plus the 3rd time interval of the 4th time interval
Voltage subtracts a critical voltage of twice of the first transistor again.
6. automatic voltage amplifying device as claimed in claim 4, it is characterised in that further include：
One the 5th transistor, it is coupled between first contact and the second transistor, the 5th transistor is in the 4th time
It is unlatching in section.
7. automatic voltage amplifying device as claimed in claim 2, it is characterised in that in very first time section with this second when
Between in section, one first junction voltage of first contact and one second junction voltage of second contact are zero.
8. automatic voltage amplifying device as claimed in claim 2, it is characterised in that in the 3rd time interval, this first
One first junction voltage of contact is equal to the input voltage with one second junction voltage of second contact and subtracts first crystalline substance
One critical voltage of body pipe.
9. a kind of automatic voltage amplification method, it is characterised in that applied to an automatic voltage amplifying device, automatic voltage amplification
Device includes a sensor, a first transistor, a second transistor, a third transistor, one the 4th transistor and an output
End, the sensor are respectively coupled to the first transistor and the third transistor, and the second transistor is respectively coupled to be located at the sensing
One first contact between device and the third transistor and positioned at the first transistor, the second transistor and the 4th crystal
One second contact between pipe, for the 4th transistor couples between second contact and the output end, the sensor receives one
Input voltage and export a VD to the first transistor, automatic voltage amplification method comprise the steps of：
In opening the second transistor and the third transistor in a very first time section and close the 4th transistor；
In closing the second transistor, the third transistor and the 4th transistor in one second time interval；And
In opening the second transistor in one the 3rd time interval and close the third transistor and the 4th transistor；
Wherein, the input voltage increases with the time and the VD is according to the input voltage synchronization lifting.
10. automatic voltage amplification method as claimed in claim 9, it is characterised in that in very first time section, the input
Voltage increases to one first level by an initial level；In in second time interval, the input voltage is increased by first level
Add to one second level；In in the 3rd time interval, the input voltage increases to one the 3rd level by second level.
11. automatic voltage amplification method as claimed in claim 10, it is characterised in that the VD in this first when
Between it is linearly increasing with a first rate in section and second time interval, and the VD is in the 3rd time zone
Interior to be increased with one second rate linear, wherein second speed is more than the first rate.
12. automatic voltage amplification method as claimed in claim 11, it is characterised in that further comprise the steps of：
In closing the second transistor and the third transistor in one the 4th time interval and open the 4th transistor, the input
Voltage increases to one the 4th level by the 3rd level, and the VD is linearly increasing with a third speed, the 3rd speed
Rate is more than second speed.
13. automatic voltage amplification method as claimed in claim 12, it is characterised in that in the 4th time interval, this is defeated
Go out the exported output voltage in end be equal to the input voltage of the 4th time interval plus the 3rd time interval this is defeated
Enter the critical voltage that voltage subtracts twice of the first transistor again.
14. automatic voltage amplification method as claimed in claim 12, it is characterised in that the automatic voltage amplifying device is further
Comprising one the 5th transistor, it is coupled between first contact and the second transistor, the 5th transistor is in the 4th time
It is unlatching in section.
15. automatic voltage amplification method as claimed in claim 9, it is characterised in that in very first time section with this second
In time interval, one first junction voltage of first contact and one second junction voltage of second contact are zero.
16. automatic voltage amplification method as claimed in claim 9, it is characterised in that in the 3rd time interval, this first
One first junction voltage of contact is equal to the input voltage with one second junction voltage of second contact and subtracts first crystalline substance
One critical voltage of body pipe.
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| Application Number | Priority Date | Filing Date | Title |
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| TW106114371A TWI636668B (en) | 2017-04-28 | 2017-04-28 | Automatic voltage amplifying apparatus and automatic voltage amplifying method |
| TW106114371 | 2017-04-28 |
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Also Published As
| Publication number | Publication date |
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| TWI636668B (en) | 2018-09-21 |
| TW201840131A (en) | 2018-11-01 |
| CN107404622B (en) | 2019-12-06 |
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