CN104836966B - A kind of cmos image sensor column buffer signal integrity optimization circuit and its method - Google Patents
A kind of cmos image sensor column buffer signal integrity optimization circuit and its method Download PDFInfo
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Abstract
The invention discloses a kind of cmos image sensor column buffer signal integrity optimization circuit and its method, the optimization circuit includes operation amplifier, row gating switch, feedback switch, integrated signal gating switch, reference signal gating switch, integrated signal sampling switch, reference signal sampling switch, reference signal sampling holding capacitor, integrated signal sampling holding capacitor.Compared with conventional readout circuit column buffer, the kick back caused by the large change of operational amplifier operating point (recalcitrate) effect during present invention, avoiding traditional structure buffer from park mode to enabled pattern switching.Meanwhile the structure it also avoid when carrying out secondary correlated-double-sampling, two sampling holding capacitors and the charge share effect of column buffer input parasitic capacitance generation, destruction of the column buffer to sampling hold circuit signal integrity is greatly suppressed.
Description
Technical field
The present invention relates to complementary MOS (CMOS) field of image sensors, and in particular to a kind of
Cmos image sensor column buffer signal integrity optimizes circuit and its method.
Background technology
Imaging sensor is the core of hyundai electronicses imaging system, and imaging sensor is based primarily upon two kinds of techniques and realized,
CMOS technology and charge coupling device (CCD) technique.Cmos image sensor technology is due to its integrated level height, small volume, power consumption
Low advantage, rapid development is achieved in recent years.Speed, the precision of cmos image sensor reading circuit determine sensing
The indexs such as frame frequency, dynamic range and the MTF (modulation transfer function) of device, therefore the quality of its design directly affects image sensing
The function and performance of device.
The effect of column buffer is quickly to export preceding level sampled data in reading circuit, because row buffer output terminal is present
Very long wire, can introduce larger dead resistance and parasitic capacitance, while late-class circuit is there is also input capacitance, in order to realize
The quick output of data, column buffer need have very high bandwidth.Fig. 2 (a) show traditional row buffer circuit, but should
Serious charge share effect be present in structure.In normal work, sampling capacitance 35 and 36 is separately sampled reference signal and product
Sub-signal, then switchs 34 and 33 and in turn switches on, and integrated signal and reference signal are output into rear class by column buffer is carried out
Black-level correction.Because the unity gain bandwidth of column buffer must be very high, therefore the input of column buffer is larger to pipe size,
It is also very big to input parasitic capacitance, therefore the charge share effect between column buffer input capacitance and sampling capacitance can not be ignored.
Research shows that the difference of integrated signal and reference signal through column buffer output is reduced to original C2/(C+Cg)2Times, C and Cg
Respectively sampling capacitance and column buffer input parasitic capacitance, the heavy damage integrality of photosignal.
If Fig. 2 (b) is improved row buffer circuit structure, compared with Fig. 2 (a), This structure increases a column buffer,
It is middle to be controlled without switch and column buffer input is directly connected with sampling capacitance top crown, therefore, adopted in sampling capacitance
During sample, column buffer input grid parasitic capacitance save same voltage, eliminate read when row buffering input gate capacitance and
Charge share effect between sampling capacitance.However, there is serious " recalcitrating " (kick-back) effect in the structure.With such as Fig. 3
Illustrated exemplified by shown operational amplifier configuration, within the sampling time before every column buffer is enabled, sampling capacitance 40
The sampling to prime programmable gain amplifier (PGA) output signal is completed, if the voltage for sampling row buffer inputs is
Vin, after the sampling time terminates, column buffer enables by column, and from dormancy into enabled transition process, input pipe leaks column buffer
Source voltage varies widely, and is coupled to sampling capacitance 40 by grid leak overlap capacitance 41 and grid source overlap capacitance 42, causes grid
Voltage varies widely, and destroys the integrality that signal is stored in sampling holding capacitor 40.
The content of the invention
The present invention proposes a kind of cmos image sensor column buffer signal integrity optimization circuit and its method, this row
Because of computing when buffer signal integrality optimization circuit avoids traditional structure buffer from park mode to enabled pattern switching
Kick-back (recalcitrates) effect caused by the large change of amplifier operating point.Meanwhile the structure it also avoid carry out it is secondary
During correlated-double-sampling, two sampling holding capacitors and the charge share effect of column buffer input parasitic capacitance generation.
A kind of imaging sensor reads column buffer signal integrity optimization circuit in circuit, including column buffer, described
Column buffer includes operational amplifier, row gating switch, feedback switch, first integral signal gating switch and secondary signal gating
Switch, the first reference signal gating switch and the second reference signal gating switch, first integral signal sampling switch and the second product
Sub-signal sampling switch, the first reference signal sampling switch and the second reference signal sampling switch, reference signal sampling keep electricity
Hold, and integrated signal sampling holding capacitor；
The operational amplifier positive input terminal is connected with common mode electrical level VCM, and row gating switch is connected with output end；
The feedback switch both ends connect operational amplifier output terminal and negative input respectively；
The reference signal sampling holding capacitor top crown is connected to prime by the first reference signal sampling switch to be compiled
Journey gain amplifier output end, integrated signal sampling holding capacitor are connected to prime by first integral signal sampling switch and can compiled
Journey gain amplifier output end；
The first integral signal gating switch ends connect operational amplifier output terminal and integrated signal sampling capacitance respectively
Top crown, secondary signal gating switch both ends connect the lower pole of operational amplifier negative input end and integrated signal sampling capacitance respectively
Plate；
First reference signal gating switch both ends connect the upper of operational amplifier output terminal and reference signal sampling capacitance respectively
Pole plate, the second reference signal gating switch both ends connect the lower pole of operational amplifier negative input end and reference signal sampling capacitance respectively
Plate；
Second reference signal sampling switch both ends connect operational amplifier positive input terminal and reference signal sampling capacitance respectively
Bottom crown, second integral signal sampling switch ends connect under operational amplifier positive input terminal and reference signal sampling capacitance respectively
Pole plate.
Isolating device be present between the output end and negative end input pipe of the operational amplifier.
A kind of imaging sensor reads the optimization method of column buffer signal integrity optimization circuit in circuit, including following
Step：Read sample certain column data when, the column buffer need to carry the previous clock cycle and enter enabled state, and computing is put
Big device is connected as unit gain form, and to establish operational amplifier operating point, then row gating switch is connected, and feedback switch breaks
Open, during which integrated signal gating switch and reference signal gating switch in turn switch on, and export integrated signal and reference signal respectively.
As a further improvement on the present invention, the sample phase comprises the following steps, the first reference signal sampling switch,
First integral signal sampling switch, second integral signal sampling switch are connected with the second reference signal sampling switch, reference signal
Sampling holding capacitor and integrated signal sampling holding capacitor are respectively completed the sampling to reference signal and integrated signal, and sampling is completed
The first reference signal sampling switch and first integral signal sampling switch off afterwards, and second integral signal sampling switch and second
Reference signal sampling switch is still in on-state, therefore electric capacity is in the hold mode to sampled signal, above-mentioned processing procedure
Each row column buffer is completed parallel.
As a further improvement on the present invention, the first reference signal sampling switch and first integral the signal sampling switch
Control sequential by prime programmable gain amplifier constrain.
As a further improvement on the present invention, the output integrated signal step comprises the following steps, first integral signal
Gating switch is connected with secondary signal gating switch, and integrated signal sampling capacitance jumps to operational amplifier negative input and defeated
Go out end, second integral signal sampling switches off, to isolate common mode electrical level VCM and operational amplifier negative input.
As a further improvement on the present invention, the output reference signal step comprises the following steps, the first reference signal
Gating switch and the second reference signal gating switch are connected, and reference signal sampling capacitance jumps to operational amplifier negative input
And output end, meanwhile, reference signal sampling switch disconnects, to isolate common mode electrical level VCM and operational amplifier negative input.
As a further improvement on the present invention, it is described to establish operational amplifier operating point, it is necessary to appropriate common mode electrical level VCM
So that amplifier is operated in rational voltage range.
Compared with prior art, the present invention has advantages below：
A kind of cmos image sensor column buffer signal integrity optimization circuit of the present invention, according to the charge conservation of electric capacity
Principle, Sampling techniques are overturn using electric charge, each column column buffer is being gated previous clock cycle entrance by SECO
Enabled state, first, the foundation in advance of operational amplifier operating point；Second, it make use of the negative-feedback of operational amplifier, sampling capacitance
Effect so that even if the signal in sampling holding capacitor remains to recover after changing.Traditional structure buffer is avoided from dormancy mould
Formula (recalcitrates) effect to the kick-back caused by the large change of operational amplifier operating point during enabled pattern switching.Meanwhile
The structure it also avoid when carrying out secondary correlated-double-sampling, two sampling holding capacitors and column buffer input parasitic capacitance
The charge share effect of generation, greatly suppress destruction of the column buffer to sampling hold circuit signal integrity.
Further, isolating device be present between the output end of operational amplifier and negative end input pipe, the input of its negative end
Pipe source-drain voltage is constant, therefore the electric charge on grid source, grid leak overlap capacitance does not change, would not also produce kick-back
Effect.
The optimization method of the present invention is based on optimizing circuit in column buffer signal integrity, solves charge share well
Effect and kick-back (recalcitrates) effect caused by the large change of operational amplifier operating point, both the above effect is drawn
The error entered reduces more than 90%, therefore is greatly improved the dynamic range of imaging sensor and improves system imaging quality,
System power dissipation is saved simultaneously.
Brief description of the drawings
Fig. 1 is typical cmos image sensor reading circuit；
Fig. 2 is charge share effect schematic diagram；
Fig. 3 is kick-back effect schematic diagrames；
Fig. 4 is row buffer circuit structure proposed by the present invention；
Fig. 5 is row cushioning control sequential proposed by the present invention；
Fig. 6 is the annexation of column buffer different phase；
Fig. 7 is from a stage to b-stage, again to the change of c stage operational amplifier negative input voltages；
Fig. 8 is the operational amplifier of three kinds of different structures.
Wherein, Fig. 1 is into Fig. 3, and 20, CMOS active pixels, 21, programmable gain amplifier, 22, column buffer, 23, defeated
Go out buffer；30th, programmable gain amplifier, 31, switch, 32, switch, 33, switch, 34, switch, 35, sampling capacitance, 36,
Sampling capacitance, 37, electric capacity, 38,38`, buffer, 39,39`, switch, 40, sampling capacitance, 41, grid leak overlap capacitance, 42, grid
Source overlap capacitance.
Fig. 4 is into Fig. 6, and 10, operational amplifier, 11, row gating switch, 12, feedback switch, 13, the choosing of first integral signal
Open up pass, 15, second integral signal gating switch, the 14, first reference signal gating switch, 16 second reference signals gating is opened
Close, 18, first integral signal sampling switch, 19, second integral signal sampling switch, the first reference signal sampling switch 17,100
Second reference signal sampling switch, 101, reference signal sampling holding capacitor, 102, integrated signal sampling holding capacitor.
Embodiment
It is described in further details below in conjunction with implementation of the accompanying drawing to the present invention and operation principle：
It is typical cmos image sensor reading circuit as shown in Figure 1, including programmable gain amplifier 21, row buffering
Device 22 and output buffer 23, for the ease of the analytic explanation of problem, CMOS active pixels 20 are also show in figure.Carrying out figure
During as shooting, pixel exports reset signal first, then exports exposure signal again, the two phase through programmable gain amplifier 21
After closing double sampled and amplification, the electric capacity C in 22 is sampled and storedSOn, meanwhile, programmable gain amplifier (PGA) 21 it is defeated
Go out reference signal and be sampled and stored the electric capacity C in 22ROn.Exposed for roller exposure and the overall situation, often the above-mentioned place of row pixel
Reason process is parallel.And for simulating the sensor of playback mode, due to the limitation of port number, it is impossible to which each column is distributed
One PAD, but several columns share a PAD, therefore after above-mentioned sampling is completed, the data of these row need to read successively by column
Go out.Each column column buffer needs to export two signals, integrated signal and reference signal, so that late-class circuit makees difference to eliminate row admittedly
Mould-fixed noise (FPN), because row buffering is to be sequentially output data by column, therefore in order to save system power dissipation, lead in this column selection
Column buffer is in park mode after preceding or data output.
As shown in Fig. 4 to Fig. 5, a kind of cmos image sensor column buffer signal integrity optimization circuit of the present invention and control
Sequential processed.Column buffer includes operational amplifier 10, row gating switch 11, feedback switch 12, the He of integrated signal gating switch 13
15, reference signal gating switch 14 and 16, integrated signal sampling switch 18 and 19, reference signal sampling switch 17 and 100, reference
Signal sampling holding capacitor 101, integrated signal sampling holding capacitor 102.One end that 17 and 18 short circuits are switched in column buffer connects
It is connected in Fig. 1 21 output end.When reading certain column data, the column buffer need to carry the previous clock cycle into enabled shape
State, and operational amplifier 10 is connected as unit gain form, to establish the operating point of operational amplifier 10, corresponding to sequential in figure
The a stages, then row gating switch connect, during which integrated signal gating switch and reference signal gating switch in turn switch on, point
Not Shu Chu integrated signal and reference signal, respectively in corresponding diagram sequential b the and c stages.
Column buffer needs the both ends of feedback switch 12 to connect the output end of operational amplifier 10 and negative input respectively, and feedback is opened
The control signal of pass 12 and the control signal of row gating switch 11 are opposite so that certain column operations amplifier 10 is establishing operating point
When, row buffering is isolated with other row bufferings, does not influence the normal work of other row, and when gating this row, gating switch 11
Connect, feedback switch 12 disconnects, normally to export integrated signal and reference signal.
Column buffer needs integrated signal gating switch 13 and 15, and 13 both ends of switch connect the output end of operational amplifier 10 respectively
With the top crown of integrated signal sampling capacitance 102,15 both ends of switch connect the negative input end of operational amplifier 10 and integrated signal respectively
The bottom crown of sampling capacitance 102.When exporting integrated signal, two switch connections, integrated signal sampling capacitance 102 jumps to computing
The negative input of amplifier 10 and output end, integrated signal sampling switch 19 disconnect, to isolate common mode electrical level VCM and operation amplifier
The negative input of device 10.
Column buffer needs to refer to signal gating switch 14 and 16, and 14 both ends of switch connect the output end of operational amplifier 10 respectively
With the top crown of reference signal sampling capacitance 101,16 both ends of switch connect the negative input end of operational amplifier 10 and reference signal respectively
The bottom crown of sampling capacitance 101.When exporting reference signal, two switch connections, reference signal sampling capacitance 101 jumps to computing
The negative input of amplifier 10 and output end, meanwhile, reference signal sampling switch 100 disconnects, to isolate common mode electrical level VCM and fortune
Calculate the negative input of amplifier 10.
Column buffer reference signal samples the top crown of holding capacitor 101 and is connected to prime by reference to signal sampling switch 17
PGA output ends, integrated signal sampling holding capacitor 102 are connected to prime PGA output ends by integrated signal sampling switch 18, joined
The control sequential for examining signal sampling switch 17 and integrated signal sampling switch 18 is constrained by prime PGA.
Column buffer needs appropriate common mode electrical level VCM to cause operational amplifier 10 to be operated in rational voltage range.
In sample phase, switch 17,18,19 is connected with 100, and electric capacity 101 and 102 is respectively completed to reference signal and integration
The sampling of signal, 17 and 18 are switched after the completion of sampling and is disconnected, and switch 19 and 100 still in on-state, therefore electric capacity is in
To the hold mode of sampled signal, the respectively parallel completion of row of above-mentioned processing procedure.
When each column carries out data output, column buffer is required for the experienced three stages course of work, i.e. a of sequential in Fig. 5,
B, the c stages, shown in such as Fig. 6 (a) (b) (c) of circuit connection state corresponding to each stage.In a stages, operational amplifier 10 is made
Can, still in on-state, negative input voltage is pulled to switch 12 by operational amplifier 10 under the negative feedback of itself
Common-mode voltage VCM, complete the foundation of the operating point of operational amplifier 10.Now the output end voltage of operational amplifier 10 is also VCM, and
Gating switch 11 is off, and this column operations amplifier 10 and column bus are kept apart, therefore Ben Lielie Buffer outputs
Common mode electrical level VCM does not influence the normal output of other column datas.When SW is effective, this row is strobed, in the first half in gating stage
Part-time, i.e. b-stage, the bottom crown of sampling capacitance 102 disconnect with datum, and pole is respectively connecting to operational amplifier 10 up and down
Output end and negative input, as shown in Fig. 6 (b).Because sampling capacitance 102 does not have jumping to the rear and front end of operational amplifier 10
There is charge/discharge loop, therefore its both end voltage keeps constant, the negative input voltage of operational amplifier 10 is made in itself feedback
It is forced to be pulled to VCM under, and the bottom crown electric capacity of electric capacity 102 is also VCM, therefore now column buffer output voltage is equal to electric capacity
The integrated signal that 102 top crowns sample, and because the negative input voltage of operational amplifier 10 in a, b-stage is VCM, its
The quantity of electric charge in parasitic capacitance does not change, therefore will not cause charge share occurs between electric capacity 102.In the gating stage
The latter half time, i.e. c stages, the bottom crown of sampling capacitance 101 disconnects with datum, and pole is respectively connecting to computing and put up and down
The big output end of device 10 and negative input, as shown in Fig. 6 (c).Because sampling capacitance 101 is being jumped to before and after operational amplifier 10
There is no charge/discharge loop, therefore its both end voltage keeps constant, the negative input voltage of operational amplifier 10 feeds back at itself
It is forced to be pulled to VCM under effect, and the bottom crown electric capacity of electric capacity 101 is also VCM, therefore now column buffer output voltage is equal to electricity
Hold the reference signal that 101 top crowns sample, and because the negative input voltage of operational amplifier 10 in b, c stage is VCM,
The quantity of electric charge in its parasitic capacitance does not change, therefore will not cause charge share occurs between electric capacity 101.
Fig. 7 is from a stage to b-stage, again to the change of the negative input voltage of c stages operational amplifier 10, wherein t1
Corresponding S1 rising edge, t2 correspond to S2 rising edge.As can be seen that actually in the handoff procedure of different phase, computing is put
Of short duration change can occur for the big negative input voltage of device 10, cause the quantity of electric charge in grid parasitic capacitance to be changed, cause grid
Charge share between parasitic capacitance and sampling capacitance in fact be present, only resulting charge variation amount is quickly by operation amplifier
The feedback effect of device 10 is compensated, and the signal on sampling capacitance actually experienced the process of a holding → saltus step → recovery.
The innovation of column buffer of the present invention is that：First, the foundation in advance of the operating point of operational amplifier 10；Second, it make use of fortune
Calculate amplifier 10, the negative feedback of sampling capacitance so that even if the signal in sampling holding capacitor remains to recover after changing.
Column buffer utilization of the present invention is established the electric charge that operating point is eliminated between sampling capacitance and grid parasitic capacitance and divided in advance
Enjoy, the kick-back effects for the column buffer pointed out in background technology are due to the large change of operational amplifier operating point
Introduced (from dormancy to enabled), theoretically, the foundation in advance of operational amplifier operating point, it should can also eliminate simultaneously
Kick-back effects, however, by carefully analyzing operational amplifier configuration, it is in fact really not so.Three kinds of knots as shown in Figure 8
Structure operational amplifier, if using the operational amplifier shown in Fig. 8 (a), even if operating point is established in advance, from a stage b stages again
Kick-back effects still occur when switching to the c stages.Because enable a before this row is strobed in operational amplifier
Stage, operational amplifier negative input and output end voltage are VCM (not considering offset voltage), in b-stage, although finally
Negative end can be stabilized to VCM, and the electric charge in the overlap capacitance of operational amplifier negative end input pipe grid source will not change, but due to
Output end end value is VCM+Vsig (Vsig is integrated signal), i.e., negative sense input pipe drain voltage is varied widely, and is become
Change amount is Vsig, causes the quantity of electric charge in negative end input pipe grid leak overlap capacitance 41 to change, the charge variation amount is by adopting
Sample electric capacity 102 is provided, therefore certain destruction is caused to the signal on sampling capacitance.Computing for Fig. 8 (b) and 8 (c) is put
Big device, although being changed in the effectively front and rear output end voltages of S1, negative end input pipe source-drain voltage is constant, therefore grid
Electric charge on source, grid leak overlap capacitance does not change, would not also produce kick-back effects.Certainly, satisfactory computing
Amplifier also not only both structures, as long as isolating device between operational amplifier output terminal and negative end input pipe be present, all
Kick-back effects will not occur.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to is assert
The embodiment of the present invention is only limitted to this, for those skilled in the art, is not departing from this
On the premise of invention thinking, some simple replacements can also be designed, the right that the present invention is submitted should be all considered as belonging to and want
The scope of patent protection for asking book to determine.
Claims (8)
1. column buffer signal integrity optimizes circuit in a kind of cmos image sensor reading circuit, it is characterised in that：Including
Column buffer, the column buffer include operational amplifier (10), row gating switch (11), feedback switch (12), first integral
Signal gating switchs (13) and secondary signal gating switch (15), the first reference signal gating switch (14) and the second reference signal
Gating switch (16), first integral signal sampling switch (18) and second integral signal sampling switch (19), the first reference signal
Sampling switch (17) and the second reference signal sampling switch (100), reference signal sampling holding capacitor (101), and integrated signal
Sample holding capacitor (102)；
Operational amplifier (10) positive input terminal is connected with common mode electrical level VCM, and row gating switch (11) is connected with output end；
Feedback switch (12) both ends connect operational amplifier (10) output end and negative input respectively；
Reference signal sampling holding capacitor (101) top crown is connected to prime by the first reference signal sampling switch (17)
Programmable gain amplifier output end, integrated signal sampling holding capacitor (102) switch (18) by first integral signal sampling
It is connected to prime programmable gain amplifier output end；
Described first integral signal gating switch (13) both ends connect operational amplifier (10) output end and integrated signal sampling respectively
The top crown of electric capacity (102), secondary signal gating switch (15) both ends connect operational amplifier (10) negative input end and integration respectively
The bottom crown of signal sampling electric capacity (102)；
First reference signal gating switch (14) both ends connect operational amplifier (10) output end and reference signal sampling capacitance respectively
(101) top crown, second reference signal gating switch (16) both ends connect operational amplifier (10) negative input end and reference respectively
The bottom crown of signal sampling electric capacity (101)；
Second reference signal sampling switch (100) both ends connect operational amplifier (10) positive input terminal and reference signal sampling electricity respectively
Hold the bottom crown of (101), second integral signal sampling switch (19) both ends connect operational amplifier (10) positive input terminal and ginseng respectively
Examine the bottom crown of signal sampling electric capacity (102).
2. column buffer signal integrity optimizes circuit in cmos image sensor reading circuit according to claim 1,
It is characterized in that：Isolating device be present between the output end and negative end input pipe of the operational amplifier (10).
A kind of 3. column buffer signal integrity optimization circuit in cmos image sensor reading circuit as claimed in claim 1
Optimization method, it is characterised in that：Comprise the following steps：When reading certain column data after sampling, the column buffer need to shift to an earlier date one
The individual clock cycle enters enabled state, and operational amplifier (10) is connected as into unit gain form, to establish operational amplifier
(10) operating point, then row gating switch (11) connection, feedback switch (12) disconnect, during which integrated signal gating switch and reference
Signal gating switch in turn switches on, and exports integrated signal and reference signal respectively.
4. column buffer signal integrity optimization circuit is excellent in cmos image sensor reading circuit as claimed in claim 3
Change method, it is characterised in that：The sample phase comprises the following steps, the first reference signal sampling switch (17), first integral
Signal sampling switch (18), second integral signal sampling switch (19) are connected with the second reference signal sampling switch (100), are referred to
Signal sampling holding capacitor (101) and integrated signal sampling holding capacitor (102) are respectively completed to reference signal and integrated signal
Sampling, the first reference signal sampling switch (17) and first integral signal sampling switch (18) disconnect after the completion of sampling, and the
Two integrated signal sampling switch (19) and the second reference signal sampling switch (100) are in adopting still in on-state, electric capacity
The hold mode of sample signal, above-mentioned each row column buffer of processing procedure are completed parallel.
5. column buffer signal integrity optimization circuit is excellent in cmos image sensor reading circuit as claimed in claim 4
Change method, it is characterised in that：The first reference signal sampling switch (17) and the control of first integral signal sampling switch (18)
Sequential processed is constrained by prime programmable gain amplifier.
6. column buffer signal integrity optimization circuit is excellent in cmos image sensor reading circuit as claimed in claim 3
Change method, it is characterised in that：It is described output integrated signal step comprise the following steps, first integral signal gating switch (13) and
Second integral signal gating switch (15) is connected, and it is defeated that integrated signal sampling capacitance (102) jumps to operational amplifier (10) negative sense
Enter end and output end, second integral signal sampling switch (19) disconnects.
7. column buffer signal integrity optimization circuit is excellent in cmos image sensor reading circuit as claimed in claim 3
Change method, it is characterised in that：It is described output reference signal step comprise the following steps, the first reference signal gating switch (14) and
Second reference signal gating switch (16) is connected, and it is defeated that reference signal sampling capacitance (101) jumps to operational amplifier (10) negative sense
Enter end and output end, meanwhile, reference signal sampling switch (100) disconnects.
8. column buffer signal integrity optimization circuit is excellent in cmos image sensor reading circuit as claimed in claim 3
Change method, it is characterised in that：It is described when establishing operational amplifier (10) operating point, it is necessary to which appropriate common mode electrical level VCM is so that transport
Put and be operated in rational voltage range.
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| EP3392675B1 (en) * | 2017-04-21 | 2021-03-10 | Melexis Technologies NV | Active pixel circuit for a time-of-flight system and method for operating the same |
| CN107396008B (en) * | 2017-07-12 | 2020-10-02 | 上海集成电路研发中心有限公司 | CMOS image sensor low-noise reading circuit and reading method thereof |
| CN108391071B (en) * | 2017-11-23 | 2020-04-14 | 南京邮电大学 | SPAD array level readout circuit adopting secondary correlation double sampling technology |
| CN108521549B (en) * | 2018-03-28 | 2020-08-25 | 西安微电子技术研究所 | Super large area array CMOS image sensor structure |
| CN109587419B (en) * | 2018-11-06 | 2021-04-30 | 上海集成电路研发中心有限公司 | Low-power-consumption reading circuit structure of image sensor and working time sequence control method |
| CN110278397B (en) * | 2019-07-26 | 2021-04-13 | 北京思比科微电子技术股份有限公司 | Low-power-consumption column circuit for CMOS image sensor |
| CN113395468A (en) * | 2020-03-11 | 2021-09-14 | 格科微电子（上海）有限公司 | Method for sampling and amplifying image sensor signal |
| CN112866590B (en) * | 2020-12-31 | 2022-08-16 | 长春长光辰芯光电技术有限公司 | Method for reducing error value of image sensor sequential circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102265604A (en) * | 2008-12-08 | 2011-11-30 | 美商豪威科技股份有限公司 | Analog multiplexer configured to reduce kickback perturbation |
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| KR20060018553A (en) * | 2004-08-25 | 2006-03-02 | 삼성전자주식회사 | A circuit for compensating for the fluctuation of reference voltage and comparator having the same |
| KR101543674B1 (en) * | 2009-01-13 | 2015-08-11 | 삼성전자주식회사 | - - Image sensor for reducing kick-back noise and image pick-up device having the same |
| TWI530183B (en) * | 2011-12-08 | 2016-04-11 | Sony Corp | An imaging element, a control method, and an imaging device |
-
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| Publication number | Priority date | Publication date | Assignee | Title |
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