CN1467805A - Method and system for monitoring ion implantation to semiconductor basic material - Google Patents
Method and system for monitoring ion implantation to semiconductor basic material Download PDFInfo
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- CN1467805A CN1467805A CNA021605777A CN02160577A CN1467805A CN 1467805 A CN1467805 A CN 1467805A CN A021605777 A CNA021605777 A CN A021605777A CN 02160577 A CN02160577 A CN 02160577A CN 1467805 A CN1467805 A CN 1467805A
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Abstract
The present invention relates to a method for effectively supervising a dose of implanted silicon atom comprising: implanting first layer atoms onto a semiconductor base material with first layer dose and first layer energy, then implanting silicon atoms with second layer dose and second energy, backfiring the semiconductor base material and measuring the sheet resistance thereof, and then supervising and validating a value of the second layer dose according to the sheet resistance. The method according to the present invention also determines a value of the second layer dose upon a surface resistance value.
Description
Technical field
The technology that the present invention relates to integrated circuit and make semiconductor device.The accuracy of implanted silicon ion when specifically, the invention provides a kind of method and system and monitor semiconductor and make.And can be applicable to other widely on the purposes in addition.For example, the present invention can be applicable on different types of device, such as DRAM (Dynamic Random Access Memory) (DRAM), static random access memory (SRAM),, application-specific integrated circuit (ASIC) device (ASIC), microprocessor, microcontroller, flash memory and other device.
Background technology
It is indispensable one critical processes in the semiconductor device manufacturing that ion is implanted.Its principle is impurity to be injected semi-conductive base material change that it is electrical, makes it change into another kind of kenel by first kind of kenel.Therefore in many roads processing procedure that semiconductor is made, " P " kenel impurity and " N " kenel impurity often is used to inject semi-conductive base material.These impurity are controlled its processing procedure by its dosage, energy and other parameter.The measurement of the dosage of its implant impurity, common available heat wave instrument (such as: TP500) or Other Instruments measure.The implantation of silicon ion generally is used for semi-conductive fabrication steps, such as: the silicon that the silicon of metal silicide is implanted and preposition amorphous is formatted is implanted.The error of implant dosage unfortunately have many restrictions to be present in the implant dosage of monitoring silicon ion, because can't be monitored out usually by traditional monitor mode.Therefore be a big difficulty for the accuracy that continues monitoring silicon ion implant dosage.
So provide a kind of improving technology, be indispensable contribution at the improvement of above-mentioned manufacture of semiconductor at this.
Summary of the invention
The invention relates to the manufacturing of integrated circuit and device thereof, more accurate theory, the accuracy of implanted silicon ion when the invention provides a kind of method and system and monitoring semiconductor and make.And can be applicable to other widely on the purposes in addition.For example: the present invention can be applicable on different types of device, such as DRAM (Dynamic Random Access Memory) (DRAM), static random access memory (SRAM), patent integrated circuit (ASIC), microprocessor, microcontroller, flash memory and other device.
Particularly, this invention provides a kind of method to monitor the dosage that silicon ion is implanted accurately, and method is as follows:
At first on the surface of semiconductor substrate with first kind of dosage and first kind of energy, implant first kind of ion, and then with second kind of dosage and second kind of energy implanted silicon ion, the method also comprises tempering semiconductor silicon base material, and measures its surperficial sheet resistor.Can monitor and verify the silicon ion exact dose of being implanted via sheet resistor then.
In particular, the present invention provides a method accurately for semiconductor substrate in the integrated circuit manufacturing.The method comprises: provide a slice test chip in implanting board.On this chip, inject the ionic species that can be used as reference dose and reference energy,, inject silicon ion again with other dosage and other energy.Tempering semiconductor silicon base material then, and measure its surperficial sheet resistor, monitor and verify the silicon ion exact dose of being implanted again via sheet resistor.Use the value of silicon ion dosage then, come verification to implant equipment, with the semiconductor quality of guaranteeing that this device fabrication is come out.
Therefore the present invention can improve the restriction on the conventional semiconductors processing procedure monitoring technology.Summary, the present invention provides a kind of accurate and easy monitoring technology to manufacture of semiconductor.Specifically, the present invention can accurately monitor the dosage that silicon ion is implanted, thereby has promoted the yield of device on the chip, moreover does not need can reach above-mentioned benefit via complicated procedures such as improving board equipment and processing procedure.
Description of drawings
Fig. 1 to Fig. 5 has specifically described each process of the present invention.
Embodiment
The invention relates to the manufacturing of integrated circuit and device thereof, more accurate theory, the accuracy of implanted silicon ion when the invention provides a kind of method and system and monitoring semiconductor and make.And can be applicable to other widely on the purposes in addition.For example: the present invention can be applicable on different types of device, such as DRAM (Dynamic Random Access Memory) (DRAM), static random access memory (SRAM), application-specific integrated circuit (ASIC) device (ASIC), microprocessor, microcontroller, flash memory and other device.
The present invention calculates with the concrete grammar of monitoring implanted silicon ion dose as follows:
1, provides a test chip;
2, with " arsenic " as impurity implant for the first time dosage and for the first time energy on test pieces;
3, with silicon as the impurity second time, implant for the second time dosage and for the second time energy on test pieces;
4, tempering test pieces;
5, measure the sheet resistor of test pieces;
6, on other chip, repeat 1 ~ 5 step with various dose;
7, calculate the relevance of dosage and sheet resistor;
8, at least one built-in testing sheet or other multi-disc test pieces, use this relevance;
9, adjust the processing procedure of other test pieces;
10, carry out other required step.
The invention provides above method, that is the use test sheet is adjusted implantation process to reach the purpose of verification, this kind test pieces is not product chips usually, and the sheet resistor of measuring test pieces can be used to verification or calibration implantation process, and the user who the invention provides ion implantation manufacture process adjusts or monitor the implant dosage of silicon ion.Below more detail record the present invention.
Fig. 1 to Fig. 5 detailed presentations the inventive method.These legends are only as explanation, but therefore do not limit right application range of the present invention.As shown in the figure, prepare a slice silicon (as indicating 100) earlier.This silicon is 2 ~ 5 ohm-cms for the P type has resistivity.As shown in the figure, silicon crystal lattice is arranged (as indicating 101,103) in the monocrystalline mode, and this silicon is a test pieces, is imported in the board, whether can be engaged in production as this board equipment of monitoring.
As Fig. 2, impurity arsenic is implanted in chip surface and arrives a certain degree of depth (as indicating 201), and the dosage of implanting arsenic is usually from 1.0E12 to 1.0E13, and other impurity also can be applicable on the method.Implant impurity arsenic is used for improving its electrical conductivity and reference is implanted in conduct.
Then at chip surface implanted silicon (as indicating 301), next this chip of tempering (as Fig. 4), this drawing process makes silicon ion move to the position of lattice structure (as indicating 403), and also activated the arsenic impurities of implanting, this tempering need use its temperature of Rapid Thermal processing procedure (RTP) in 950 ℃ ~ 1050 ℃ inert environments, is meant the environment that is included in nitrogen or other nullvalent gas at the inert environments of this indication.
Measure its sheet resistor afterwards, as shown in Figure 5.Common available RS-75 of sheet resistor or Other Instruments are measured sheet resistor, and in this invention, sheet resistor will increase with the increase of the silicon of implanting.The increase of sheet resistor is because implanted the density step-down of arsenic impurities, but the present invention of following example more detailed description.
Though the present invention cooperate to go up some experimental datas with preferred embodiment and is illustrated, this embodiment is not in order to limiting the present invention, anyly is familiar with this art field person and all can finishes various changes and variation in without departing from the spirit or scope of the invention.Therefore, spirit of the present invention and scope system is defined by the claim of enclosing.
Embodiment
In order to verify principle of the present invention and application, we have done following experiment.Yet therefore this experiment does not limit the right application range of its invention except as a kind of checking.In experiment, we use resistivity is the P cake core of 2 ~ 5 ohm-cms, and the implantation value of these chips and measured value are all shown in following table one.
Table one
| Disk number | Dosage (%) | ????TW | TW (changing %) | TW (sensitivity) |
| ????1 | ??100 | ????930.1 | ??N/A | ??N/A |
| ????2 | ??105 | ????938.2 | ??0.87 | ??0.174 |
As shown in the figure, implanted silicon, energy 35KeV, dosage 8E14atoms/cm2, and use heat wave instrument TP500 to measure its TW heat wave value.First chip implanted 100% dosage, implants 105% dosage for second, and to record its TW heat wave value respectively be 930.1 and 938.2.
The change percentage of TW heat wave value is 0.87% (less than 1%), and susceptibility is 0.174, and account form is as follows:
TW (change percentage)=[(938.2-930.1)/930.1] * 100%=0.87%
The TW[susceptibility]=(0.87% ÷ 5%)=0.174
At this 0.5% is the first variation percentage with second chip implant dosage.
So low susceptibility can't be monitored out the minor variations of the implant dosage of silicon ion, and this is the restriction of present conventional method, so we adopt following method to improve.Table two is its implantation value percentage and sheet resistor data thereof:
Table two
| Disk number | Dosage (%) | ????Rs | Rs (changing %) | Rs (sensitivity) |
| ????1 | ??100 | ????2244 | ??N/A | ??N/A |
| ????2 | ??105 | ????2351 | ??4.77 | ??0.954 |
First chip implanted 100% dosage, implants 105% dosage for second, and after tempering, recording sheet resistor respectively is 2244 and 2351, and the change percentage of sheet resistor is 4.77%, and therefore calculating its susceptibility is 0.954, near 1.The method is to be 30KeV with the silicon ion energy, and dosage is that 5.0E15 is implanted in the chip of anticipating.At the chip that this what is called was anticipated, be to refer to be implant impurity with arsenic earlier, energy 60KkV, dosage are 5.0E12, implant in the test pieces of P type.As implied above, the sheet resistor in the method can be significantly and the responsive minor alteration that reflects dosage, can make us than traditional monitoring method, more efficiently comes the monitoring ion implantation process.
Though the present invention cooperate to go up some experimental datas with preferred embodiment and is illustrated, this embodiment is not in order to limiting the present invention, anyly is familiar with present technique field person and all can finishes various changes and variation in without departing from the spirit or scope of the invention.Therefore, spirit of the present invention and scope should be defined by the claims of enclosing.
Claims (20)
1, the method for monitoring implanted silicon dosage comprises:
On base material,, implant the first road impurity earlier with the first road dosage, the first road energy;
On base material with the second road dosage, the second road energy, implanted silicon impurity;
The tempering base material;
Measure the substrate surface sheet resistor;
Monitor or verify the value of the second road dosage according to the value of sheet resistor.
2, the method for claim 1 is characterized in that, the first road implant impurity is an arsenic.
3, the method for claim 1 is characterized in that, the first road dosage is lower than the second road dosage.
4, the method for claim 1 is characterized in that, the first road dosage hangs down 10 3 power rank at least than second road.
5, the method for claim 1 is characterized in that, sheet resistor is the Rs value.
6, the method for claim 1 is characterized in that, the first road impurity is arsenic, indium or antimony.
7, the method for claim 1 is characterized in that, also comprises the step of repetition with other dosage, other energy implanted silicon impurity.
8, the method for claim 1 is characterized in that, the tempering environment is a Rapid Thermal processing procedure, and is maintained in the nullvalent gaseous environment.
9, the method for claim 1 is characterized in that, base material is the P type.
10, the method for claim 1 is characterized in that, uses the tempering activated atom.
11, want grave 1 described method as right, it is characterized in that, in nullvalent gaseous environment, carry out tempering.
12, method as claimed in claim 11 is characterized in that, nullvalent gaseous environment is the inflated with nitrogen environment.
13, a kind of method of making integrated circuit on semiconductor substrate comprises:
Insert a testing substrates in implanting board;
With basic dose, reference energy, implant a benchmark atom on the surface of testing substrates;
With the first road dosage, the first road energy, the implanted silicon atom is implanted as first road with this on the testing substrates surface;
Tempering base material in inert environments;
Measure the sheet resistor of substrate surface, this sheet resistor is relevant with the silicon atom that first road is implanted at least;
Monitor and verify the dose value that first road is implanted according to the value of sheet resistor;
Use the value of the first road dosage to come the board equipment of verification implantation;
Use this board to make semiconductor substrate.
14, method as claimed in claim 13 is characterized in that, basic dose is lower than the first road dosage.
15, method as claimed in claim 13 is characterized in that, basic dose hangs down 10 3 power rank at least than the first road dosage.
16, method as claimed in claim 13 is characterized in that, sheet resistor is the Rs value.
17, method as claimed in claim 13 is characterized in that, the benchmark atom is an arsenic.
18, method as claimed in claim 13 is characterized in that, semiconductor substrate is the finished product disk.
19, method as claimed in claim 13 is characterized in that, the tempering environment is a Rapid Thermal processing procedure (RTP), and is maintained in the nullvalent gaseous environment.
20, method as claimed in claim 13 is characterized in that, semiconductor substrate is a P type base material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA021605777A CN1467805A (en) | 2002-12-30 | 2002-12-30 | Method and system for monitoring ion implantation to semiconductor basic material |
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| CNA021605777A CN1467805A (en) | 2002-12-30 | 2002-12-30 | Method and system for monitoring ion implantation to semiconductor basic material |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414554B (en) * | 2007-10-17 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method |
| CN101246809B (en) * | 2007-02-13 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Monitoring coupon and monitoring method for ion implantation technique |
| CN101355028B (en) * | 2007-07-25 | 2012-10-03 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing grid pole oxide layer |
| CN104913805A (en) * | 2014-03-11 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Method for improving daily inspection stability of ion implanter |
-
2002
- 2002-12-30 CN CNA021605777A patent/CN1467805A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246809B (en) * | 2007-02-13 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Monitoring coupon and monitoring method for ion implantation technique |
| CN101355028B (en) * | 2007-07-25 | 2012-10-03 | 中芯国际集成电路制造(上海)有限公司 | Method for repairing grid pole oxide layer |
| CN101414554B (en) * | 2007-10-17 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method |
| CN104913805A (en) * | 2014-03-11 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Method for improving daily inspection stability of ion implanter |
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