CN1466219A - AND gate logic device with monowall carbon nano tube strucure and mfg. method - Google Patents

Abstract

This invention relates to an AND-gate logic device with single wall carbon nm tube as the basis, composed of a single wall nm tube, two independent grids and three independent grids. A middle electrode is added by constant bias as the output end, the other two connect to the earth. Two grids are used as the input end controlling on-off of the single wall carbon nm tube realizing the logic AND operation.

Description

Has AND gate logical device of Single Walled Carbon Nanotube structure and preparation method thereof

Technical field

The invention belongs to a kind of logical device, particularly a kind of AND gate logical device based on Single Walled Carbon Nanotube and preparation method thereof.

Background technology

In afternoon December 23 nineteen forty-seven, the Xiao Keli of U.S.'s Bell Laboratory (W.Shockley), Bradley pause (W.Brattain) and Ba Ding (J.Bardeen) successfully utilizes semi-conducting material to make first transistor in the world.This transistor is " point-contact transistor ".After 1 year, Xiao Keli has invented " junction transistor " again, and this is only modern transistorized ancestors.Therefore Xiao Keli becomes " father of transistor ".1956, people such as Xiao Keli obtained Nobel Prize in physics jointly because of its epoch-making invention.The invention of semiconductor transistor becomes the beginning of semiconductor technology, and from then on the mankind have entered a brand-new era---the information age.Occur from first semiconductor transistor, performance that it is excellent and development potentiality have just attracted everybody's sight, and the speed of development is also advanced by leaps and bounds.1958, TI company developed first integrated circuit in the world, one and half inches long, than the also thin germanium wafer of toothpick on, held 5 electronic components.Only after 1 year, the Robert of fairchild company (Fairchild). promise should this (Robert.Noyce) be succeeded in developing the planar integrated circuit manufacturing technology.Intel company (Intel) 4 bit microprocessors 4004 that formally distribute in 1971, it contains 2300 transistors.4004 become the first step of the CPU that marches toward.To end of the year calendar year 2001 Pentium chip that Intel company releases integrated a forty-two million transistor.

The conventional semiconductors technical development till now, can be described as achieve great success, the achievement splendidness.Various products based on semiconductor technology have become indispensable part in people's life now.But, along with improving constantly to the requirement of integrated level and arithmetic speed.All inadequate natural endowments of conventional semiconductors integrated circuit also come out gradually.According to one of founder of Intel company---the famous Moore's Law that mole is found: the number of transistors that is integrated on the chip piece approximately every two years doubles.Calculate like this, by 2010, the number of transistors on chip will be above 1,000,000,000.Along with the raising of transistor integrated level, the power consumption of chip and heat radiation will become the huge obstacle that hinders semiconductor technology evolves.Cover the Er Xinte prediction according to the chief technology officer that Intel company is responsible for the chip design indoor design, can not get solving, to chip in 2005, during integrated 200,000,000 transistors, will hotly must look like " nuclear reactor " as the heat radiation of fruit chip and the problem of power consumption; The level of high-temperature gas nozzle when 2010 will arrive rocket launching; 2015 will be the same with the surface of the sun hot.

Austrian scientist professor Zola who proposes many great new academic thought such as ion trap ion calculating has the earliest provided a relative estimative figure, and he thinks that the memory of traditional computer will meet with the limit after general ten years.Professor professor Long Guilu of Tsing-Hua University also supports this viewpoint, and he thinks and infers that according to " Moore's Law " what in a decade or so is exactly the limit of classic computer.

Exactly because traditional semiconductor device can not be satisfied the demand in the near future, so people seek a kind of semi-conductive substitute urgently.This substitute must have the characteristics that semi-conducting material does not have, to overcome semi-conductive many disadvantages.The development that appears as electronic device of new generation of nano material has hewed out a brand-new road.With Single Walled Carbon Nanotube and nano wire is that new road has been opened up in the circuit development that appears as of the new process technology of the nano material of new generation of representative and the thing followed, become the preferred material of electronic device of future generation, so important meaning is arranged based on the research and development of the nanometer circuit of Single Walled Carbon Nanotube.

1998, and the people such as R.Martel in IBM research center (" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, Vol 73, No.17,2447) produce field effect transistor with Single Walled Carbon Nanotube.This Single Walled Carbon Nanotube field effect transistor at room temperature has good electrical properties, and its every performance index can compare favourably with traditional semiconductor field fully.Field effect transistor is the basis of Digital Logical Circuits, therefore we can say that the appearance of Single Walled Carbon Nanotube field effect transistor is the first step of nanometer logical circuit of marching toward.After this, people such as Adrian.Bachtold (" science " SCIENCE, 2001,294,1317.) on the basis of Single Walled Carbon Nanotube field effect transistor, successfully design and produce out the logic gates and the device of at room temperature working, comprising logical "not" circuit, logic " or not " circuit, random asccess memory and oscillator.These Single Walled Carbon Nanotube circuit and devices use Single Walled Carbon Nanotube change the principle of its conducting state under the control of bias voltage (Single Walled Carbon Nanotube has different electrical properties because of its structure is different, the Single Walled Carbon Nanotube of indication is in not on-state when not adding grid voltage herein, is in conducting state when adding certain grid voltage).Simultaneously, people such as Yu Huang produces the logical based on semiconductor nanowires.The operation principle of this nano wire logical circuit is to utilize different doped P-type or N type semiconductor nano wire to be in contact with one another, thereby forms the P-N knot, utilizes the character of semiconductor P-N to realize logical operation.Though these Single Walled Carbon Nanotube and nanowire circuit and device performance are good, and its shortcoming is also arranged.In the making of nanometer circuit, the placement of Single Walled Carbon Nanotube and nano wire is puzzlement people's a difficult problem always.At present, people use " tunnel microscope " (STM) or " atomic force microscope " (AFM) technology control nano material, it is in place.And these methods exist that efficient is low, the determining of weak effect.Circuit that people such as Adrian.Bachtold make and device mostly use the Single Walled Carbon Nanotube more than.And in the nanowire circuit that people such as Yu Huang make, use the nanowire crossbars structure arranged.These making that are designed to circuit bring and very big difficulty, are unfavorable for the integrated of device.

Summary of the invention

The objective of the invention is for complexity that solves the Single Walled Carbon Nanotube logic circuit structure and the difficulty that reduces making, for make efficiency and the effect that improves device; Thereby provide a kind of to use a Single Walled Carbon Nanotube, simple in structure, be easy to make with integrated and have AND gate logical device of Single Walled Carbon Nanotube structure and preparation method thereof.

The present invention is the AND gate logical device with Single Walled Carbon Nanotube structure, comprising: the Si substrate is provided with SiO on this Si substrate ₂Insulating barrier, the resistance in Single Walled Carbon Nanotube, grid, electrode and the external circuit; It is characterized in that: described grid comprises two independently grids, and grid is by depositing Al in the groove that is provided with on this Si substrate and the Al that forms through surface oxidation ₂O ₃Insulating barrier constitutes; Described electrode comprises 3, electrode be arranged on the Single Walled Carbon Nanotube or under; Grid and electrode are alternate to be arranged in parallel; The straight SiO that is placed on of Single Walled Carbon Nanotube ₂On the surface of insulating barrier, with the Al of grid ₂O ₃The layer of precious metal surface of surface of insulating layer and electrode contacts; On first electrode and second electrode grounding, second electrode and substrate or the resistance in the external circuit link to each other.

Described SiO ₂The thickness of insulating barrier is between 35nm to 100 μ m; The degree of depth of groove is between 10nm to 95 μ m.

Described Single Walled Carbon Nanotube is a Single Walled Carbon Nanotube.

The orientation of described Single Walled Carbon Nanotube is vertical with grid with electrode.

Described grid and electrode are alternate to be arranged in parallel; Grid and distance between electrodes are between 5nm to 100 μ m.

The Al of described grid ₂O ₃Thickness of insulating layer is between 1 nanometer to 5 nanometer; Grid is positioned at SiO on the Si substrate ₂Among two grooves in the insulating barrier.

Described gate upper surface and the SiO on the Si substrate ₂Maintain an equal level on the surface of insulating layer.

Described electrode top and the SiO on the Si substrate ₂Maintain an equal level on the surface of insulating layer.

Preparation provided by the invention has the method for the AND gate logical device of Single Walled Carbon Nanotube structure, comprises the steps:

(i) on substrate, establish insulating barrier earlier, on insulating barrier, erode away 5 grooves that are used for plated metal;

(ii) depositing conducting layer in groove again, and the conductive layer burning formed insulating barrier, thus form two grids;

(iii) the insulating barrier in two grid both sides erodes away the groove that is used for depositing conducting layer then, and deposits 3 electrodes of conductive layer formation within it;

(iv) more just Single Walled Carbon Nanotube place perpendicular to electrode and grid, and contacting with grid with electrode;

(on v) first electrode and second electrode grounding, second electrode and substrate or the resistance in the external circuit link to each other, thereby form an AND gate logical device with Single Walled Carbon Nanotube structure.

Advantage of the present invention:

AND gate logical device with Single Walled Carbon Nanotube structure of the present invention is compared with the existing circuit that has carbon nano-tube and nano wire to make: structurally, the multiple-grid utmost point and multi-electrode structure have alternately creatively been used, and only use a carbon nano-tube just to realize the function of logical, make device be easy to make, be the integrated road of having opened up of following nanometer circuit.Single Walled Carbon Nanotube logical gate logic device of the present invention has been compared simple in structure with known logic gates, be easy to make and integrated advantage.

Manufacture method of the present invention adopts straight being placed on electrode and the grid of Single Walled Carbon Nanotube, and guarantee between Single Walled Carbon Nanotube and the metal electrode contact good, the purpose of Fang Zhiing is to guarantee that Single Walled Carbon Nanotube is on the planar structure like this, and having avoided forming tunnel junctions because of Single Walled Carbon Nanotube is crooked influences device performance.

Description of drawings

Fig. 1 is the semiconductor nanowires logical that people such as Yu Huang makes;

Fig. 2 is the schematic diagram with AND gate logical device of Single Walled Carbon Nanotube structure of the present invention;

Fig. 3 is the structural representation of a kind of embodiment of the present invention;

Fig. 4 is the structural representation of another kind of embodiment of the present invention;

Indicate among the figure: 1, Single Walled Carbon Nanotube; 2, first grid; 3, second grid;

4, first electrode; 5, second electrode; 6, third electrode; 7, SiO ₂Insulating barrier;

8, Si substrate; 9, resistance; 10, constant pressure source; 11, P type Si nano wire;

12, N type GaN nano wire.

Embodiment

Embodiment 1:

Make an AND gate logical device with Single Walled Carbon Nanotube structure with reference to Fig. 2 and 3, its device architecture be described in detail below in conjunction with manufacture method:

The silicon of choosing (001) orientation is as substrate 8.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on substrate 8 ₂Layer 7.At first make grid 2,3: at SiO ₂Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier.Photoresist behind the electron beam exposure through development, photographic fixing, remove the photoresist of exposure after, on photoresist layer, form two wide 30nm, at a distance of the groove of 130nm.The SiO that uses dry etching method etching not have photoresist to cover ₂, at SiO ₂Form two wide 30nm in the insulating barrier, the groove of dark 30nm, wide 130nm.Utilize the method for electron beam evaporation, at the thick Al of surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating ₂O ₃Insulating barrier.So just finished the preparation of grid 2,3.Prepare electrode 4,5,6 then: repeat above lithography step, evenly smear the photoresist that a layer thickness is 80nm on the entire device surface.Behind the resist exposure, in photoresist layer, form the groove of three wide 30nm.Article one, in the centre of grid, two other is in the grid outside, apart from grid 50nm.Use dry etching, do not having the SiO of photoresist ₂Etch the groove of three wide 30nm, dark 30nm in the insulating barrier.Utilizing the method for electron beam evaporation again, is the gold of 30nm at whole surface deposition one layer thickness.Both finished the preparation of electrode 4,5,6 after then electric lithography glue being peeled off, cleaned.Selecting a length is 300nm, and carrier concentration is 9 * 10 ⁶Cm ^-1Single Walled Carbon Nanotube 1 is placed on the entire device with atomic force microscope.Requiring Single Walled Carbon Nanotube to place does not have bending, and direction is basic vertical with the grid direction with electrode, and will contact well with grid with electrode.After device encapsulated, connect resistance 9 and constant pressure source 10, electrode 4,6 ground connection are finished the preparation of entire device.

After device was finished, the outward appearance of entire device should be formed (referring to Fig. 4) by two grids and three electrodes.For fear of the crooked tunnel junctions that produces of Single Walled Carbon Nanotube, electrode and grid all should and SiO ₂Layer maintains an equal level.Single Walled Carbon Nanotube is positioned on grid and the electrode.

The present invention selects the Single Walled Carbon Nanotube of semiconductive for use.The character of the Single Walled Carbon Nanotube of this semiconductive is: conductivity is preferably arranged at normal temperatures, and its resistance is generally a hundreds of k Ω.Its charge carrier is the hole as can be known by experiment, so conduction type is the p type.Its electric conductivity changes with the change of grid voltage.When grid voltage increases to certain value, Single Walled Carbon Nanotube will be in cut-off state.

Electrical properties and schematic diagram of the present invention 2 below in conjunction with Single Walled Carbon Nanotube illustrate operation principle of the present invention.

As mentioned above: Single Walled Carbon Nanotube resistance at normal temperatures is generally a hundreds of K Ω.Its charge carrier is the hole by testing as can be known, and conduction type is the P type.Under the effect of forward grid bias, the concentration in charge carrier---hole will reduce.At thickness of insulating layer is under the situation of 140nm, and grid voltage is about 6V, and the hole in the Single Walled Carbon Nanotube will be exhausted fully, and Single Walled Carbon Nanotube is in cut-off state.Simultaneously, the present invention as can be known: at this moment, if keep the cut-off state of Single Walled Carbon Nanotube, added bias voltage should be not more than 1.5V at the Single Walled Carbon Nanotube two ends.So the present invention is defined in the circuit of the present invention, 1.2V is logical value " 1 ", and 0V is logical value " 0 ".

In logical circuit, unified logical value is very important, all should observe this regulation in all parts of logical circuit, can guarantee that like this circuit structure is simple, efficient is higher, calculating is reliable.Except input and output will be observed this regulation, the grid of control Single Walled Carbon Nanotube also must be observed this regulation.

By above discussion the present invention as can be known: when the gate insulator layer thickness was 140nm, the voltage that exhausts of grid was 6V.The present invention determines by following calculating, during the exhausting voltage and be 1.2V of grid, and the thickness of gate insulator.

Known, there is following relationship in the voltage that blocks between Single Walled Carbon Nanotube and the grid:

Q＝CV _G，T???????????????????????(1)

V _{G, T}For blocking voltage, Q is electrically charged by charge carrier, and C is the electric capacity between Single Walled Carbon Nanotube and the grid.

Q and carrier concentration satisfy formula:

Q＝peL????????????????????????(2)

P is a carrier concentration; E is electrically charged by charge carrier, and charge carrier is the hole in p type Single Walled Carbon Nanotube, so e=+1.6 * 10 here ^-19Coulomb; L is the length of Single Walled Carbon Nanotube and grid contact portion.

Electric capacity between notice of invitation wall carbon nano tube and the grid satisfies formula again:

C≈2πεε ₀L/ln(2h/r)??????????(3)

H is the distance between Single Walled Carbon Nanotube and the grid, i.e. the thickness of gate insulator; R is the Single Walled Carbon Nanotube radius; ε is a dielectric constant, and the present invention here gets ε=2.5.

Formula (2), (3) are brought in the formula (1) and can be got:

peln(2h/r)＝2πεε ₀V _G，T $h=\frac{1}{2}{\mathrm{re}}^{\left(\frac{2\mathrm{\π\ϵ}{\mathrm{\ϵ}}_0{V}_{G.T}}{\mathrm{pe}}\right)}---\left(4\right)$

It is 9 * 10 that the present invention selects carrier concentration ⁶Cm ^-1P type Single Walled Carbon Nanotube.The Single Walled Carbon Nanotube radius is 0.8nm, and cut-ff voltage is 1.2V.Bringing formula (4) into can get: h ≈ 3nm.That is: in the present invention, work as Al ₂O ₃Thickness of insulating layer is not more than under the situation of 3nm, and Single Walled Carbon Nanotube is in cut-off state.

The present invention utilizes the conducting state of two grid control Single Walled Carbon Nanotube to realize the logical computing.When input terminal electrode 2,3 has one or two input value all is logical zero, promptly during voltage 0V, and the part of Single Walled Carbon Nanotube or all be in conducting state.At this moment, the voltage of output terminal electrode 5 is 0, i.e. logical value " 0 "; Have only the logical value when input terminal electrode 2,3 input to be logical one, promptly during voltage 1.2V, Single Walled Carbon Nanotube is in cut-off state.At this moment, output electrode 5 electromotive forces equate with constant pressure source 10, are 1.2V, i.e. logical value " 1 ".Truth table of the present invention is as shown in table 1.As can be seen, the present invention has realized the logical computing by grid to the control of Single Walled Carbon Nanotube state from truth table.

Table 1

????X in1(2)	??X in(3)	???Y out(5)
			????1	??0	???0
????0	??1	???0
			????0	??0	???1
????1	??1	???1

Embodiment 2:

The silicon of selecting (001) orientation for use is as substrate 8.Method by embodiment 1 prepares SiO ₂ Insulating barrier 7 and two grids 2,3.Select a Single Walled Carbon Nanotube 1 that length is 600nm, utilize atomic force microscope (AFM) technology that it is positioned on two grids.Require two grids should approximately be in the centre position of Single Walled Carbon Nanotube, two grids contact well with Single Walled Carbon Nanotube, and Single Walled Carbon Nanotube do not have bending, and direction is vertical with two grids.After Single Walled Carbon Nanotube is in place,, on Single Walled Carbon Nanotube, prepares three width with focused ion beam (FIB) method and be 0.1 μ m, highly be the gold electrode 4,5,6 of 200nm in the position of the centre of two grids two outside 50nm.After the encapsulation of device finishes, connect resistance 9 and constant pressure source 10, electrode 4,6 ground connection are finished preparation of devices.

After encapsulation finished, the monnolithic case of device should be by two and SiO ₂The grid that layer maintains an equal level and three place SiO ₂Electrode on the layer is formed (referring to Fig. 5).Single Walled Carbon Nanotube is put on the grid, is fixed by electrode.

Embodiment 3:

Press 2,3 and three electrodes 4,5,6 of method two grids of preparation of embodiment 1.Method deposition long 100 μ m, a diameter of applying electronic beam evaporation are the Al line of 12nm.Its direction is vertical with electrode, an end is connected with electrode 5, and another section deposition one is of a size of 30nm * 30nm, and thickness is the gold electrode of 30nm.After peroxidating, will form the thick Al of 4-5nm on Al line surface ₂O ₃Oxide layer.The diameter of turning part is about 2nm in the Al line.Like this, the resistance of Al line is approximately tens M Ω, and resistance 9 preparations finish.Single Walled Carbon Nanotube is selected and placed to standard and method by embodiment 1.With after the device package, connect constant pressure source 10 at last, electrode 4,6 ground connection are finished the making of device.

Key in the manufacture craft is to make thin as far as possible gate insulator, guarantees that again insulating barrier has good insulation performance simultaneously.The thickness that reduces insulating barrier can further reduce grid voltage, improves the Performance And Reliability of device.

Claims (10)

1. AND gate logical device with Single Walled Carbon Nanotube structure, comprising: the Si substrate is provided with SiO on this Si substrate ₂Insulating barrier, the resistance in Single Walled Carbon Nanotube, grid, electrode and the external circuit; It is characterized in that: described grid comprises two independently grids, and grid is by depositing Al in the groove that is provided with on this Si substrate and the Al that forms through surface oxidation ₂O ₃Insulating barrier constitutes; Described electrode comprises 3, electrode be arranged on the Single Walled Carbon Nanotube or under; Grid and electrode are alternate to be arranged in parallel; The straight SiO that is placed on of Single Walled Carbon Nanotube ₂On the surface of insulating barrier, with the Al of grid ₂O ₃The layer of precious metal surface of surface of insulating layer and electrode contacts; On first electrode and second electrode grounding, second electrode and substrate or the resistance in the external circuit link to each other.

2. the AND gate logical device with Single Walled Carbon Nanotube structure according to claim 1 is characterized in that: grid and two electrodes are positioned at the SiO on the substrate ₂In the groove in the insulating barrier, the degree of depth of groove is between 10nm to 95 μ m; SiO ₂The thickness of insulating barrier is between 35nm to 100 μ m; The width of grid and electrode is between 10nm to 50 μ m.

3. the AND gate logical device with Single Walled Carbon Nanotube structure according to claim 1 is characterized in that: it is to cover thereon at a layer of precious metal that described two electrodes are positioned on the insulating barrier of substrate and the Single Walled Carbon Nanotube.

4. the AND gate logical device with Single Walled Carbon Nanotube structure according to claim 1 is characterized in that: it is that the groove depositing noble metal that is provided with on the Si substrate constitutes that described two electrodes are positioned on the Single Walled Carbon Nanotube.

5. according to claim 1 or 2 or 3 described AND gate logical devices with Single Walled Carbon Nanotube structure, it is characterized in that: the thickness of insulating layer of grid is between 1 nanometer to 5 nanometer.Grid and distance between electrodes are between 5nm to 100 μ m.

6. according to claim 1 or 2 or 3 described AND gate logical devices, it is characterized in that: the straight placement of Single Walled Carbon Nanotube with Single Walled Carbon Nanotube structure.

7. the AND gate logical device with Single Walled Carbon Nanotube structure according to claim 1 and 2 is characterized in that: the insulating barrier upper surface of the upper surface of grid and substrate maintains an equal level.

8. the AND gate logical device with Single Walled Carbon Nanotube structure according to claim 1 and 2 is characterized in that: the upper surface of electrode and SiO ₂The upper surface of insulating barrier maintains an equal level.

9. one kind prepares the described method with AND gate logical device of Single Walled Carbon Nanotube structure of claim 1, it is characterized in that comprising the steps:

(i) on substrate, establish insulating barrier earlier, on insulating barrier, erode away the groove that is used for plated metal;

(ii) depositing conducting layer in groove again, and the conductive layer burning formed insulating barrier, thus form two grids;

(iii) the insulating barrier in two grid both sides erodes away the groove that is used for depositing conducting layer then, and deposits conductive layer formation electrode within it;

(iv) more just Single Walled Carbon Nanotube place perpendicular to electrode and grid, and contacting with grid with electrode;

(on v) first electrode and second electrode grounding, second electrode and substrate or the resistance in the external circuit link to each other, resistance connects constant pressure source again.Thereby form an AND gate logical device with Single Walled Carbon Nanotube structure.

10. the preparation method with AND gate logical device of Single Walled Carbon Nanotube structure according to claim 9 is characterized in that: the described SiO that is positioned on the substrate ₂Gash depth in the insulating barrier is between 10nm to 95 μ m; SiO ₂The thickness of insulating barrier is between 35nm to 100 μ m; The width of grid and electrode is between 10nm to 50 μ m.

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