CN1248313C - Carbon nano tube logic OR gate device and preparation method thereof - Google Patents

Abstract

The present invention relates to a carbon nano tube logic OR gate device and a preparation process thereof. The carbon nano tube logic OR gate device comprises a substrate, wherein an insulating layer, a carbon nano tube, grid electrodes, electrodes and a resistor are arranged on the substrate the two grid electrodes are arranged in a groove on the insulating layer; the two electrodes are arranged in the groove on the insulating layer of both sides of the two grid electrodes; the carbon nano tube contacts with the two grid electrodes and the two electrodes; one electrode of the two electrodes is connected with the earth, and the other electrode is connected with a constant voltage through the resistor. A logic OR function is realized by using the two grid electrodes to control the on-off of the carbon nano tube. Compared with other carbon nano tube logic circuits, the logic OR gate circuit of the present invention has the advantages of simple structure and easy fabrication and integration.

Description

Carbon nano tube logic OR gate device and preparation method thereof

Technical field

The invention belongs to micro-nano electronic device circuit, particularly relate to a kind of carbon nano-tube OR-gate logical device and preparation method thereof.

Background technology

The conventional semiconductors technical development has the time of decades till now, has obtained splendid fruits.Various semiconductor device have become indivisible important component part in people's life.Particularly near twenty or thirty is in year, along with reaching its maturity of semiconductor integrated circuit technology, is the every aspect that the various microelectronic products of representative have entered people's lives with the electronic computer, becomes people's important part of living.These semiconductor integrated circuit mainly are made of the digital circuit that " metal-oxide-semiconductor field " (MOSFET) formed.It is very ripe that this integrated circuit develops into present its technical matters, and device performance is stable, and integrated level is than higher.But, along with improving constantly to the requirement of integrated level and arithmetic speed.All inadequate natural endowments of conventional semiconductors integrated circuit also come out gradually.

At first, will give out a large amount of heats during the work of highdensity integrated device.If heat dissipation problem be mustn't go to good solution, the Performance And Reliability of integrated circuit will be influenced greatly.Secondly, be subjected to the restriction of semiconductor self character, the arithmetic speed of integrated circuit is difficult to increase again.With N raceway groove enhancing property insulating gate type field effect tube is example, and it is that (intrinsic postpones to be meant that charge carrier postpones by the caused large-signal of transporting of raceway groove to 111ps, and promptly raceway groove is charged to the needed time of raceway groove stable charging Qc from zero charge that its intrinsic postpones.)。In a very big system, the summation that postpones between each device can reach the order of magnitude of microsecond.So the deficiency of semiconductor field itself has hindered the raising of circuit speed.Moreover the conventional semiconductor process technology is based upon on the technologies such as photoetching, iontophoretic injection, doping, along with the raising of integrated level, difficulty of processing is also being improved constantly.Traditional semiconductor processing technology is subjected to the restriction of the light wavelength used in the photoetching, and is just incompetent unable to the device fabrication below the 10nm.

Exactly because traditional semiconductor device can not be satisfied the demand in the near future, so people seek a kind of semi-conductive substitute urgently.This substitute must have the characteristics that semi-conducting material does not have, to overcome semi-conductive many disadvantages.The development that appears as electronic device of new generation of nano material has launched a new road.It with carbon nano-tube and various semiconductor nanowires the nano material of representative is attracting people with its distinctive advantage attention.The electrical properties that nano material is good makes it become the first-selection of electronic device of future generation.

In the research of various nano electron devices, be the focus that various countries fall over each other to study based on the device of carbon nano-tube.The people such as R.Martel in IBM research center (" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, Vol 73, No.17,2447) produced the carbon nanotube field-effect pipe in 1998.This carbon nanotube field-effect pipe at room temperature has good electrical properties, and its every performance index can compare favourably with traditional semiconductor field fully.Field effect transistor is the base unit of integrated circuit, so the appearance of carbon nanotube field-effect pipe is to have stepped an important step to nanoscale logic circuit.On the basis of carbon nanotube field-effect pipe, people such as AdrianBachtold (" science " SCIENCE, 2001,294,1317.) successfully develop carbon nano tube logic " or the not " circuit of at room temperature working again.This logical circuit is made up of two carbon nano-tube, the conducting or the cut-off state of the grid controlling carbon nanotube below carbon nano-tube, thus realize the logical operation function.Its circuit theory diagrams such as Fig. 1.Simultaneously, people (" science " SCIENCE, 2001,294,1313.) such as Yu Huang also produces the logical "or" circuit based on semiconductor nanowires.Its schematic diagram as shown in Figure 2.8 is N type GaN nano wire among the figure, and 7 is P type Si nano wire, and 3,4,5 is metal electrode, and 4,5 is input terminal electrode, and 3 is output terminal electrode.Its operation principle is: doping type is that the semiconductor nanowires of P type and N type intersects mutually and contacts, thereby forms the P-N knot at contact point, utilizes the electrology characteristic of P-N knot to realize the logic function of circuit.

More than two kinds of logical circuits of Jie Shaoing at room temperature all have good performance, stable performance, reliability height.But we have seen the deficiency that these two kinds of circuit exist.At first, structures such as resistance, line and grid are arranged in the carbon nano tube logic gate circuit, the circuit structure more complicated is first problem that will solve so adopt the line design of which kind of form that these structures are organically combined.Secondly, carbon nano tube logic circuit and nano wire logical circuit all adopt two or more carbon nano-tube or nano wire to constitute, and this has brought very big difficulty with regard to the processing and fabricating of giving circuit.As everyone knows: in nanofabrication technique, the location of nano materials such as carbon nano-tube and semiconductor nanowires is a problem crucial in the nanometer technology always.Because nanometer diameter such as carbon nano-tube and nano wire is very little, generally in several nanometers, so accurately the location is very difficult.Present stage, the laboratory generally uses some special methods could solve orientation problem.As: use scanning tunnel microscope (STM) or atomic force microscope (AFM) that single nanotube or nano wire are controlled, drag it to the position that needs; Moreover just be to use " random orientation method " that nanotube or nano wire are in place.In above two kinds of circuit, all adopt plural carbon nano-tube and semiconductor nanowires.Especially the nano wire OR gate adopts three nanowire crossbars to arrange in circuit, and will keep excellent contact between the nano wire.This has just brought great difficulty for circuit production.The increase prize of circuit production difficulty influences the efficient of circuit production and the performance of circuit to a great extent.

Summary of the invention

The objective of the invention is to have problems such as complex structure, manufacture difficulty be big and performance and make efficiency in order to improve device in order to solve above-mentioned existing device; Thereby provide a kind of on the basis of carbon nanotube field-effect pipe, design a kind of and adopt a carbon nano-tube to make the double grid carbon nano tube logic OR gate device, that it is easy to make, integrated, reliability is high.

The present invention also aims to provide a kind of utilize made of carbon nanotubes double grid carbon nano tube logic " or " method of device.

Purpose of the present invention can realize by following measure:

A kind of carbon nano tube logic OR gate device that provides of the present invention comprises substrate, establishes insulating barrier, carbon nano-tube, grid, electrode and resistance on substrate; Establish two grids in the groove on insulating barrier, establish two electrodes in the groove on the insulating barrier of two grid both sides; One carbon nano-tube contacts with electrode with grid; Electrode grounding in two electrodes, another electrode links to each other with a constant voltage by resistance.

The thickness of described insulated substrate layer is 35nm to 100 μ m.

Gash depth on the described insulating barrier is 10nm to 95 μ m.

The width of described grid and electrode is 10nm to 50 μ m.

Distance between described grid and grid and grid and the adjacent electrode is 5nm to 100 μ m.

Described electrode places under the carbon nano-tube, or places on the carbon nano-tube.

Establish electrode on insulated substrate layer and carbon nano-tube, the height of electrode is 5nm to 200 μ m.

Also be provided with insulating barrier on grid, its thickness of insulating layer is 1nm to 5nm.

A kind of carbon nano tube logic of the present invention " or " the preparation of devices method, comprise the steps:

(i) on substrate, establish insulating barrier earlier, on insulating barrier, erode away two grooves that are used for plated metal;

(ii) depositing conducting layer in groove, and the conductive layer burning formed insulating barrier, thus form two grids;

(iii) again in the groove of the insulating barrier of two grid both sides another conductive noble metal layer of deposition form electrode;

Contact with grid (iv) then with straight being positioned on the substrate oxide layer of Single Walled Carbon Nanotube, and with electrode;

(v) allow an electrode grounding, link to each other with a constant voltage by a resistance on another electrode, thereby form a double grid structure carbon nano tube logical "or" device; By ending or conducting of grid controlling carbon nanotube; Thereby realize the logical "or" of device.

The present invention has following advantage compared to existing technology:

Carbon nano tube logic OR gate device of the present invention is compared with existing OR-gate device, uses comparatively general Single Walled Carbon Nanotube, has reduced the difficulty of element manufacturing from material; Structurally, only use a Single Walled Carbon Nanotube just can realize function, and used double-gate structure first, compared with prior art, greatly reduced gate area, further reduced the manufacture difficulty of device on the technology.The key of its manufacture method is to make thin as far as possible and gate insulator that insulating properties is good, further reduces grid voltage by the thickness that reduces insulating barrier, improves the Performance And Reliability of logical device.

Description of drawings

Fig. 1 is known carbon nano tube logic " or not " structural representation

Fig. 2 be known carbon nano tube logic " or " structural representation;

Fig. 3 is circuit theory diagrams of the present invention

Fig. 4 is a structural representation of the present invention;

Fig. 5 is an A-A cutaway view of the present invention;

Fig. 6 is the another embodiment of the present invention structural representation;

The drawing explanation:

1-carbon nano-tube 2,3-electrode 4,5-grid 6-resistance

9-constant voltage 10-insulating barrier 11-substrate

Embodiment

The present invention also will be described in further detail embodiment in conjunction with the accompanying drawings:

Electrical properties and schematic diagram of the present invention 3 below in conjunction with carbon nano-tube illustrate operation principle of the present invention.

The carbon nano-tube that the present invention selects for use is the P type semiconductor carbon nano-tube.The charge carrier of this carbon nano-tube is the hole, and resistance is about a hundreds of k Ω at normal temperatures.Add a positive bias on grid, the carrier concentration of carbon nano-tube 1 will reduce.When this positive bias increased to a certain degree, charge carrier-hole will be exhausted fully, and this moment, carbon nano-tube was in cut-off state.Carbon nanotube field-effect pipe and logical circuit have utilized this electrology characteristic of carbon nano-tube just.

In the design of Digital Logical Circuits, one of problem of most critical be exactly in the unified circuit logical value.Must stipulate in the overall logic scope that promptly unified magnitude of voltage is logical one and logical zero, can only there be two values in the input value of each device of circuit and output valve, the binary system standard that so just meets Digital Logical Circuits, and also simplified circuit structure, improved the operating efficiency of circuit.And the input voltage disunity of the control voltage of carbon nanotube field-effect tube grid in the past and source-drain electrode.When the thickness of insulating layer of grid was 140nm, the voltage of grid was generally about 6V when carbon nano-tube was exhausted, and the source-drain electrode input voltage generally is not less than 1.5V.If voltage is greater than 1.5V between source-drain electrode, the electronics in the carbon nano-tube 1 can be broken through the formed potential barrier of grid bias because having obtained enough energy and arrive drain electrode, thereby makes carbon nano-tube enter conducting state once more.For unified magnitude of voltage, will reduce the voltage that exhausts of grid.One of method is exactly the thickness that reduces gate insulator, to increase the action effect of grid voltage.

We determine the thickness of gate insulator by following calculating.

Known, there is following relationship in the voltage that blocks between carbon nano-tube 1 and the grid 4,5:

Q＝CV _G，T (1)

V _{G, T}For blocking voltage, Q is electrically charged by charge carrier, and C is the electric capacity between carbon nano-tube 1 and the grid 4,5.

Q and carrier concentration satisfy formula:

Q＝peL (2)

P is a carrier concentration; E is electrically charged by charge carrier, and charge carrier is the hole in p type carbon nano-tube, so e=+1.6 * 10 here ^-19Coulomb; L is the length of carbon nano-tube 1 and grid 4,5 contact portions.

Know that again the electric capacity between carbon nano-tube 1 and the grid 4,5 satisfies formula:

C≈2πεε ₀L/ln(2h/r) (3)

H is the distance between carbon nano-tube 1 and the grid 4,5, the i.e. thickness of gate insulator; R is carbon nano-tube 1 radius; ε is a dielectric constant, and here we get ε=2.5.

Formula (2), (3) are brought in the formula (1) and can be got:

peln(2h/r)＝2πεε ₀V _G，T

$h=\frac{1}{2}r{e}^{\left(\frac{2\mathrm{\π\ϵ}{\mathrm{\ϵ}}_0{V}_{G.T}}{\mathrm{pe}}\right)}---\left(4\right)$

It is 0.8nm that the present invention selects the carbon nano-tube radius, and carrier concentration is about 9 * 10 ⁶Cm ^-1Choose Y simultaneously ₀Be+1.2V, promptly in this Digital Logic circuit+1.2V is logical one.With 1.2V as grid 4,5 cut-ff voltage V _{G, T}Bring in the formula (4), can get: h ≈ 3nm.When grid 4,5 thickness of insulating layer were 3nm, grid 4,5 voltages of 1.2V just can allow the carbon mitron be in cut-off state.Simultaneously, also can know the discussion of the conduction property of carbon nano-tube, will not change the cut-off state of carbon nano-tube if add the voltage of 1.2V at carbon nano-tube 1 two ends this moment by the front.So just unified the magnitude of voltage in the circuit, so we can stipulate at this: magnitude of voltage+1.2V is logical value " 1 ", and magnitude of voltage 0V is a logical zero.

The operation principle of device is with reference to Fig. 3, and when the input of two inputs 4,5 is 0V, promptly during logical value " 0 ", carbon nano-tube 1 is in conducting state.This moment, output 3 did not have electrical potential difference, so output 3 output voltages are 0V, was logical value " 0 "; In two inputs 4,5 any or two inputs are 1.2V, and promptly during logical value " 1 ", carbon nano-tube is in cut-off state.At this moment, output 3 has identical electromotive force with constant pressure source 9.Because constant pressure source 9 voltages are+1.2V, so output output voltage this moment also is+1.2V i.e. logical value " 1 ".Like this, the conducting state by grid voltage change carbon nano-tube just can realize the logical "or" computing.Circuit logic truth table of the present invention is as shown in table 1.

X in1(5)	X in2(4)	Y out(3)
			1	1	1
1	0	1
			0	1	1
0	0	0

Specific embodiments of the invention are as follows:

Embodiment 1:

Press the OR-gate logical device that Fig. 3,4 and 5 makes carbon nano-tube double-gate structure of the present utility model.

The silicon of choosing (001) orientation is as substrate 11.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on substrate 11 ₂Layer 10.At first make grid 4,5: at SiO ₂Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier 10.Photoresist behind the electron beam exposure behind the photoresist of removal exposure, forms two wide 30nm, at a distance of the groove of 50nm through development, photographic fixing on photoresist layer.The SiO that uses dry etching method etching not have photoresist to cover ₂, at SiO ₂Form two wide 30nm on the insulating barrier, dark 30nm is at a distance of the groove of 50nm.Utilize the method for electron beam evaporation, at the thick Al of surface deposition one deck 30nm of entire device.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating ₂O ₃Insulating barrier.So just finished the preparation of grid 4,5.Prepare electrode 2,3 then: repeat above lithography step, evenly smear the photoresist that a layer thickness is 80nm on the entire device surface.Behind the resist exposure, on photoresist layer, form two outsides at two grids 4,5,, width parallel with grid apart from grid 50nm, direction is the groove of 30nm.Be used in the method etching, do not having the SiO of photoresist ₂Etch the groove of two wide 30nm, dark 30nm on the insulating barrier 10.Utilizing the method for electron beam evaporation again, is the gold of 30nm at whole surface deposition one layer thickness.Both finished the preparation of electrode 2,3 after then electric lithography glue being peeled off, cleaned.Choosing a diameter is that 1nm, length are 400nm, and Single Walled Carbon Nanotube 1, its carrier concentration are 9 * 10 ⁶Cm ^-1Be placed on the entire device with atomic force microscope.Requiring carbon nano-tube to place does not have bending, and direction is basic vertical with the grid direction with electrode, and will contact well with grid with electrode.After the device package, electrode 3 connects resistance 6 and constant pressure source 9, and electrode 2 ground connection are finished the making of device.The sectional view of device such as Fig. 5.

Embodiment 2:

Press the OR-gate logical device that Fig. 3,5 and 6 makes another kind of carbon nano-tube double-gate structure of the present utility model.

The silicon of choosing (001) orientation is as substrate 11.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on substrate 11 ₂Layer 10.At first make grid 4,5: at SiO ₂Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier 10.Photoresist behind the electron beam exposure through development, photographic fixing, remove the photoresist of exposure after, on photoresist layer, form two wide 30nm, at a distance of the groove of 50nm.The SiO that uses dry etching method etching not have photoresist to cover ₂, at SiO ₂Form two wide 30nm on the insulating barrier, the groove of dark 30nm.Utilize the method for electron beam evaporation, at the thick Al of entire device surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating ₂O ₃Insulating barrier.So just finished the preparation of grid 4,5.The Single Walled Carbon Nanotube 1 that to choose a length be 400nm, its carrier concentration is 9 * 10 ⁶Cm ^-1Be placed on the entire device with atomic force microscope.Require two grids 4,5 to be in carbon nano-tube 1 position intermediate substantially, carbon nano-tube 1 is placed straight, and direction is basic vertical with grid 4,5 directions with electrode, and carbon nano-tube 1 will contact well with grid 4,5.After carbon nano-tube 1 is in place, in grid 4,5 both sides, apart from the position of two grid 50nm, prepares two width and be 0.1 μ m, highly be the gold electrode 2,3 of 50nm with focused ion beam (FIB) method.Two electrode direction are parallel with grid.After device package finished, electrode 3 connected resistance 6 and constant pressure source 9, and electrode 2 ground connection are finished the making of device.

At this, the resistance value of resistance 6 should be approximately several M Ω.Constant pressure source 9 voltages should be Y ₀, this bias voltage should be the logical value " 1 " of this logical device regulation.

Claims (8)

1, a kind of carbon nano tube logic OR gate device comprises substrate (11), insulating barrier (10), carbon nano-tube (1), two grids, two electrodes (2), (3) and resistance (6), establishes insulating barrier (10) on substrate (11); It is characterized in that, on insulating barrier (10), establish two grids (4), (5), on the insulating barrier (10) of two grids (4), (5) both sides, establish two electrodes (2), (3); One carbon nano-tube (1) is placed on insulating barrier (10) and two electrodes (2), (3) perpendicular to two grids (4), (5) and two electrodes (2), (3), and contacts with two grids (4), (5) and two electrodes (2), (3); Perhaps a carbon nano-tube (1) is perpendicular to two grids (4), (5) and two electrodes (2), (3), is placed on the insulating barrier (10), under two electrodes (2), (3), and contacts with two grids (4), (5) and two electrodes (2), (3); Electrode (2) ground connection in two electrodes (2), (3), another electrode (3) links to each other with a constant pressure source (9) by resistance (6).

2, carbon nano tube logic OR gate device as claimed in claim 1, the thickness that it is characterized in that described insulating barrier (10) are 35nm to 100 μ m.

3, carbon nano tube logic OR gate device as claimed in claim 1 is characterized in that the width of described two grids (4), (5) and two electrodes (2), (3) is 10nm to 50 μ m, and is arranged in parallel.

4, carbon nano tube logic OR gate device as claimed in claim 1 is characterized in that between described grid and the grid or the distance between grid and the adjacent electrode is 5nm to 100 μ m.

5, carbon nano tube logic OR gate device as claimed in claim 1, it is characterized in that described two electrodes (2), (3) are placed on the insulating barrier (10), on the carbon nano-tube, be respectively to cover a noble metal bar at the carbon nano-tube two ends as two electrodes (2), (3), it highly is 5nm to 200 μ m.

6, carbon nano tube logic OR gate device as claimed in claim 1 is characterized in that described two electrodes (2), (3) are arranged under the carbon nano-tube to be made up of the groove of noble metal loading in the insulating barrier of two grid both sides.

7, a kind of method for preparing the described carbon nano tube logic OR gate device of claim 1 is characterized in that comprising the steps:

(i) on substrate (11), establish insulating barrier (10) earlier, on insulating barrier (10), erode away the groove that is used for plated metal;

(ii) depositing conducting layer in groove again, and the conductive layer burning formed insulating barrier, thus form two grids (4), (5);

(iii) the insulating barrier (10) in two grids (4), (5) both sides erodes away the groove that is used for depositing conducting layer then, and deposits a conductive layer within it and form two electrodes (2), (3);

(iv) again a carbon nano-tube (1) is placed perpendicular to two electrodes (2), (3) and two grids (4), (5), and contact with two electrodes (2), (3) and two grids (4), (5);

(v) allow an electrode (2) ground connection, another electrode (3) go up and link to each other, thereby form a double grid structure carbon nano tube logical "or" device with a constant pressure source (9) by a resistance (6).

8, the method for preparing carbon nano tube logic OR gate device as claimed in claim 7 is characterized in that the gash depth on the described insulating barrier (10) is 10nm to 95 μ m.

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