CN1236495C - Carbon nano tube NOR logic device - Google Patents

Abstract

The present invention relates to a carbon nano tube 'NOR' logic device. Si is used as a substrate, wherein a SiO2 oxidizing layer is arranged on the substrate; a carbon nano tube, a grid electrode and an electrode are arranged on a SiO2 insulating layer of the Si substrate; the grid electrode comprises two independent grid electrodes and is composed of Al which is deposited in two mutually adjacent grooves in the SiO2 insulating layer positioned on the Si substrate and a Al2O3 insulating layer which is formed from surface oxidation; the thickness of the insulating layer of the grid electrode is less than 3 nanometers; the electrode comprises two independent electrodes and is positioned above the SiO2 insulating layer on the Si substrate and the carbon nano tube or under the carbon nano tube; the carbon nano tube is horizontally placed on the surface of the SiO2 insulating layer and contacts with the surface of the Al2O3 insulating layer of the grid electrode and the surface of a noble metal layer of the electrode; constant bias voltage is added to one electrode, and the other electrode is an output end; a logic 'NOR' function is realized by using the two grid electrodes to control the turn-on or the turn-off of the carbon nano tube. Compared with other carbon nano tube 'NOR' logic devices, the present invention has the advantages of simple structure and easy fabrication.

Description

Carbon nano-tube " or not " logical device

Technical field

The invention belongs to a kind of logical device, particularly involve a kind of carbon nano-tube " or not " logical device of double-gate structure.

Background technology

Nano-technology Development speed is fast, makes common people attract attention.Along with the appearance of various novel nano-materials with to the deepening continuously of nano materials research, we almost can hear the soul-stirring progress of relevant nanometer technology every day.Because nano material has incomparable characteristics of many conventional semiconductor material and advantage, to add along with to the improving constantly of the requirement of size of devices and speed, the inadequate natural endowment that traditional semi-conducting material can't remedy comes out gradually.So substitute traditional semi-conducting material manufacturing device very tempting prospect is arranged with nano material.We have reason to believe that the semiconductor microactuator electronic device will be replaced by nano-device in the near future.Therefore, utilize the characteristic of nano material to make various transistors very important meaning and value are arranged.

Along with the world enters the information age, " digitlization " become the human existence mode.Various digital devices spreads all over the every aspect of people's life.Little household electrical appliance, the electronic computer of arriving arrives artificial satellite, space shuttle greatly, and none can not find the figure of digital device.And in these devices, be main part based on the digital logic device of semiconductor transistor.Present digital logic device is by semiconductor processing technologies such as photoetching, iontophoretic injection, doping basically, and a large amount of " metal---oxide---semiconductor field " (MOSFET) is integrated in and is made on the chip.This traditional semiconductor field effect transistor integrated device is from the time of decades occurring having had till now, its technology maturation, and device performance is stable, and integrated level is than higher.Use at present 0.13 micron process technology, can be on 1 square centimeter chip an integrated forty-two million transistor.But under so high integrated level, the conventional semiconductors integrated device also exposes many problems.For example: the heat dissipation problem during device work; Integrated level is difficult to further raising under the prior art condition; Be subjected to the restriction of semiconductor self character, arithmetic speed is difficult to increase or the like again.At these problems, people are constantly seeking various solutions.With the carbon nano-tube is the field effect transistor of basis making and the logical device of making on this basis, is attracting people's attention with its distinctive advantage.

1998 " Applied Physics wall bulletin " (APPLIED PHYSICS LETTERS) reported the people such as R.Martel (" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, Vol73, No.17,2447) in IBM research center.Produce field effect transistor with carbon nano-tube.This carbon nanotube field-effect pipe at room temperature has good electrical properties, and its every performance index can compare favourably with traditional semiconductor field fully.Field effect transistor is the basis of digital logic device, therefore we can say that the appearance of carbon nanotube field-effect pipe is the first step of nanometer logical device of marching toward.

After this, calendar year 2001 " science " (SCIENCE) has reported that people (" science " SCIENCE, 2001,294,1317.) such as Adrian Bachtold successfully design and produce out the logical device of at room temperature working on the basis of carbon nanotube field-effect pipe.In these logical devices, one of them is exactly (NOR) device of logic " or not ", it utilizes carbon nano-tube to change the principle of its conducting state under the control of bias voltage, and (carbon nano-tube has different electrical properties because of its structure is different, the carbon nano-tube of indication is in not on-state when not adding grid voltage herein, when adding certain grid voltage, be in conducting state), and use two carbon nano-tube, each carbon nano-tube all has an independently grid.Have only when two grid inputs are logical zero, when promptly two carbon nano-tube were cut-off state, output is output logic value " 1 "; And when having only a grid to be input as logical one when another grid is input as logical zero, be input as the nanotube that the grid of logical one controls and be in conducting state, output output logic value " 0 ", thus realized logic " or not " computing.This logical device at room temperature shows good electrical properties, and stable performance, and higher reliability is arranged.But we also see owing to used two carbon nano-tube in the device, and each carbon nano-tube all has an independently grid, thereby make the complex structure of device, for the fabrication and processing of device has been brought many difficulties.Wanting the while exactly with two carbon nanotubes positioned in the manufacturing process of device, is the most thorny issue that the double-carbon nanotube device is faced.In nanofabrication technique, the location of nano materials such as carbon nano-tube and semiconductor nanowires is the key link in the nanometer technology always.Because carbon nano-tube and nanowire diameter are very little, be generally several nanometers, so accurately the location is very difficult.Present stage, the laboratory generally uses some special methods could solve orientation problem.As: use STM (scanning tunnel microscope) or AFM (atomic force microscope) that single nanotube or nano wire are controlled, drag it to the position that needs; Moreover just be to use " random orientation method " that nanotube or nano wire are in place.So whether carbon nano-tube can accurately locate is the key factor that influences conventional efficient and device performance.In the logical device of double-carbon nanotube structure, use two carbon nano-tube, brought very big difficulty certainly will for the location of carbon nano-tube.

Summary of the invention

The objective of the invention is to have used two carbon nano-tube, and each carbon nano-tube all there is an independently grid, causes the device architecture complexity, make the defective of difficulty in order to overcome existing logical device; In order to solve the device manufacture difficulty, reduce the structural complexity of carbon nano-tube " or not " logical device, thereby a kind of carbon nano-tube " or not " logical device is provided.

Carbon nano-tube provided by the invention " or not " logical device comprises that with Si as substrate, this substrate is provided with a SiO ₂Oxide layer is at the SiO of Si substrate ₂Insulating barrier is provided with carbon nano-tube, grid and electrode; It is characterized in that: described grid comprises two independently grids, is being positioned at SiO on the Si substrate ₂The Al that deposits among two grooves adjacent one another are in the insulating barrier, and the Al that forms through surface oxidation ₂O ₃Insulating barrier constitutes, and the thickness of insulating layer of grid is less than 3 nanometers; Described electrode comprises two independently electrodes, is positioned at SiO on the Si substrate ₂On insulating barrier and the carbon nano-tube, or under the carbon nano-tube; The straight SiO that is placed on of carbon nano-tube ₂On the surface of insulating barrier, with the Al of grid ₂O ₃The layer of precious metal surface of surface of insulating layer and electrode contacts; An electrode is connected with constant source, and another electrode is an output; Grid is as input.

Described two independently electrode be to be positioned at SiO on the Si substrate under the carbon nano-tube ₂Etch two grooves in the insulating barrier, and the depositing noble metal layer constitutes among groove, this electrode is in the outside of two grids.

Comprise that also electrode is positioned at Single Walled Carbon Nanotube and SiO ₂Be thereon on the surface of insulating layer, be positioned at the Single Walled Carbon Nanotube two ends and cover a layer of precious metal.

The layer of precious metal of described making electrode is as gold and platinum etc.

Described grid and electrode are arranged in parallel, and the orientation of carbon nano-tube is vertical substantially with electrode with grid.

Described SiO ₂The thickness of insulating barrier is between 35nm to 100 μ m.

The degree of depth of described groove is between 10nm to 95 μ m.

Described grid and distance between electrodes are between 5nm to 100 μ m, and the width of grid and electrode is between 10nm to 90 μ m.

The thickness of insulating layer of described grid is between 1nm to 5nm.

The insulating barrier upper surface of the upper surface of described grid and substrate maintains an equal level.

The upper surface of described electrode and SiO ₂The upper surface of insulating barrier maintains an equal level.

The invention has the advantages that:

The present invention has compared following difference with existing " or not " logical device: used double-gate structure and a Single Walled Carbon Nanotube combination from structure, just realized logic " or not " function, so device architecture has been simple, is easy to making and integrated.The present invention has used comparatively general Single Walled Carbon Nanotube, makes the manufacturing materials of device be easy to realize.

Description of drawings

Fig. 1 is carbon nano-tube " or the not " logical device that people such as Adrian Bachtold makes;

Fig. 2 is the schematic diagram of carbon nano-tube of the present invention " or not " logical device;

Fig. 3 is the structure chart according to the carbon nano-tube of the embodiment of the invention 1 " or not " logical device;

Fig. 4 is the sectional view according to the carbon nano-tube of the embodiment of the invention 1 " or not " logical device;

Fig. 5 is the structure chart according to the carbon nano-tube of the embodiment of the invention 2 " or not " logical device;

Indicate among the figure: 1, Single Walled Carbon Nanotube, 2, first electrode, 3, second electrode, 4, first grid, 5, second grid, 6, resistance, 7, SiO ₂Insulating barrier, 8, the Si substrate.

Embodiment

Embodiment 1:

With reference to Fig. 2,3 and 4, carbon nano-tube of the present invention " or not " logical device structure is elaborated in conjunction with manufacture method and execution mode:

The silicon of selecting (001) orientation for use is as substrate 8.Utilize organic vapor phase deposition method (PECVD), form the thick SiO of 300nm ₂Insulating barrier 7.At SiO ₂Even cladding thickness is the electric lithography glue (PMMA) of 80nm on the insulating barrier 7.Behind the resist exposure, on photoresist, form two wide 30nm, at a distance of the groove of 50nm.Use dry etching, the SiO that exposes at photoresist ₂Etch wide 30nm on the insulating barrier 7, dark 30nm is used to make grid 4,5 grooves.Utilize electron beam evaporation method, at the thick Al of surface deposition one deck 30nm.After peeling off, cleaning, utilize the intrinsic oxidizing process again, make the Al surface form the thick Al of 2-3nm ₂O ₃Insulating barrier is as the preparation of first grid 4 and second grid 5.Repeat above lithography step, smear the photoresist that a layer thickness is 80nm on the entire device surface.Utilize the alignment method of electron beam lithography, to resist exposure.After development and photographic fixing, on photoresist, form the groove of two wide 30nm.Article two, the position of groove is in the outside of the grid that has completed, respectively apart from two grid 50nm.Use dry etching, etching SiO ₂Insulating barrier 7, the SiO under the no photoresist ₂Layer is etched, and etching depth is 30nm.Promptly form the groove that is used to make electrode of wide 30nm, dark 30nm; Utilizing electron beam evaporation method again, is the gold of 30nm at whole surface deposition one layer thickness; Then through peeling off, clean formation first electrode 2 and second electrode 3.Select a Single Walled Carbon Nanotube 1 that length is 300nm, be placed on the entire device, and guarantee that carbon nano-tube is in the same plane, contact with two grids and two electrodes with atomic force microscope.The requirement carbon nano-tube is straight, influences device performance to avoid carbon nano-tube to be bent to form tunnel junctions.The direction of carbon nano-tube is basic vertical with the direction of grid 4,5 with electrode 2,3, and will contact well with two grids with two electrodes; At last device is encapsulated.Then as shown in Figure 3 and Figure 4, logical constant voltage Y on first electrode 2 ₀, second electrode 3 is as output; First grid 4 and second grid 5 are respectively as input.

After device was finished, the outward appearance of entire device should be made up of two electrodes and two grids.For fear of the crooked tunnel junctions that produces of carbon nano-tube, electrode and grid all should and SiO ₂Insulating barrier 7 maintains an equal level.Carbon nano-tube is positioned on grid and the electrode.

Below in conjunction with figure principle Fig. 2 the operation principle of " or not " logical device of carbon nano tube structure is elaborated: first grid 4 and second grid 5 are distinguished two as input in the schematic diagram, second electrode 3 is as output, and first electrode 2 connects a constant pressure source.As can be seen, have only when 5 inputs of first grid 4 and second grid are logical zero from schematic diagram, when promptly two carbon nano-tube were cut-off state, output is output logic value " 1 "; And when having one to be input as " 1 " in first grid 4 and the second grid 5, the nanotube of its control will be in conducting state, and at this moment output is " 0 " just.

The schematic diagram of the carbon nano-tube of double-gate structure of the present invention " or not " logical device as shown in Figure 2.Selecting electric conductivity for use is the Single Walled Carbon Nanotube of semiconductive.The character of the Single Walled Carbon Nanotube of this semiconductive is: good electrical conductivity is arranged at normal temperatures, and its resistance is generally a hundreds of K Ω.Its charge carrier is the hole as can be known by experiment, so conduction type is the p type.Its electric conductivity changes with the change of grid voltage.Make the carbon nanotube field-effect pipe and utilized this electrology characteristic of carbon nano-tube just, change conductivity, thereby realize and the same function of conventional semiconductors field effect transistor by grid voltage.As shown in the figure: logical constant voltage Y on first electrode 2 ₀, second electrode 3 is as output.And we arrange: in this digital logic device, and voltage Y ₀Be logical one, voltage is 0 to be logical zero.First grid 4 and second grid 5 are respectively as input.With in two grids any one is example, and when adding a positive bias on grid, owing to insulate between grid and the carbon nano-tube, the charge carrier owing to carbon nano-tube is the hole again, so bias voltage will reduce the concentration of charge carrier in the carbon nano-tube.As can be known when bias voltage increases to certain value, the charge carrier in the carbon nano-tube---hole will be exhausted fully by experiment, and carbon nano-tube is in cut-off state.We determine the thickness of gate insulator by following column count.

Select the carbon nano-tube carrier concentration to be approximately 9 * 10 ⁶Cm ^-1, there is following relationship in the voltage that blocks between carbon nano-tube and the grid:

Q＝CV _G，T (1)

V _{G, T}For blocking voltage, Q is electrically charged by charge carrier, and C is the electric capacity between carbon nano-tube and the grid.

Q and carrier concentration satisfy formula:

Q＝peL (2)

P is a carrier concentration; E is electrically charged by charge carrier, and charge carrier is the hole in p type carbon nano-tube, so e=+1.6 * 10 here ^-19Coulomb; L is the length of carbon nano-tube and grid contact portion.

Know that again the electric capacity between carbon nano-tube and the grid satisfies formula:

C≈2πεε ₀L/ln(2h/r) (3)

H is the distance between carbon nano-tube and the grid, i.e. the thickness of gate insulator; R is the carbon nano-tube radius; ε is a dielectric constant, and here we get ε=2.5.

Formula (2), (3) are brought in the formula (1) and can be got:

peln(2h/r)＝2πεε _OV _G，T

Can get at last:

$h=\frac{1}{2}{\mathrm{re}}^{\left(\frac{2\mathrm{\π\ϵ}{\mathrm{\ϵ}}_0{V}_{G.T}}{\mathrm{pe}}\right)}---\left(4\right)$

We choose the Single Walled Carbon Nanotube radius is 0.8nm, Y ₀Be+1.2V, promptly in this Digital Logic device+1.2V is logical one.1.2V is brought in the formula (4) as grid cut-off voltage, can get: h ≈ 3nm.When the gate insulator layer thickness was 3nm, the grid voltage of 1.2V just can allow Single Walled Carbon Nanotube enter cut-off state.Simultaneously, we also can know by the conduction property of Single Walled Carbon Nanotube, will not change the cut-off state of carbon nano-tube if add the voltage of 1.2V at the carbon nano-tube two ends this moment.This illustrates that we select 1.2V is that logical value " 1 " is rational.

As can be seen from Figure 2, when first grid 4 and second grid 5 were input as " 0 " simultaneously, carbon nano-tube was in conducting state.At this moment, output end voltage equals constant pressure source Y ₀, i.e. 1.2V, output valve is logical value " 1 "; In two grids any one or two voltages are imported 1.2V simultaneously, and promptly during logical one, carbon nano-tube is in cut-off state, and output is " 0 ".Its truth table is as shown in table 1.From truth table as can be seen, by grid the control of carbon nano-tube conducting state has been realized logic " or not " computing function.

Table 1

X in1(4)	X in2(5)	Y(3)
			0	0	1
1	0	0
			0	1	0
1	1	0

Embodiment 2:

With reference to Fig. 3,4 and Fig. 5, be described in detail in conjunction with the structure of manufacture method to present embodiment:

The silicon of selecting (001) orientation for use is as substrate 8.Utilize organic vapor phase deposition side (PECVD), form the thick SiO of 300nm ₂Insulating barrier 7.At SiO ₂Even cladding thickness is the electric lithography glue (PMMA) of 80nm on the insulating barrier 7; Behind the resist exposure, on photoresist, form two wide 30nm, at a distance of the groove of 50nm.Use dry etching, the SiO that exposes at photoresist ₂Etch wide 30nm on the insulating barrier 7, the groove of dark 30nm.Utilize electron beam evaporation method, at the thick Al of surface deposition one deck 30nm.After peeling off, cleaning, utilize the intrinsic oxidizing process again, make the Al surface form the thick Al of 2-3nm ₂O ₃Insulating barrier.So just finished the preparation of first grid 4 and second grid 5.Select a Single Walled Carbon Nanotube 1 that length is 500nm, utilize atomic force microscope (AFM) technology that it is positioned on two grids.Require two grids should approximately be in the centre position of carbon nano-tube, two grids contact well with carbon nano-tube, and carbon nano-tube is straight, and direction is vertical with two grids.After carbon nano-tube is in place,, on carbon nano-tube, prepares two width with focused ion beam (FIB) method and be 0.1 μ m, highly be first electrode 2 of 200nm and second electrode 3 in the position of the outside of two grids 50nm.Finish the encapsulation of device at last.

As shown in Figure 5, after encapsulation finished, the monnolithic case of device should be to place SiO by two grids that maintain an equal level with SiO2 insulating barrier 7 and two ₂Electrode on the insulating barrier 7 is formed.Carbon nano-tube is put on the grid, and two ends are fixed by two electrodes.

According to carbon nano-tube " or the not " logical device of double-gate structure of the present invention, the key in its manufacture craft is to make thin as far as possible gate insulator, guarantees that again insulating barrier has good insulation performance simultaneously.The thickness that reduces insulating barrier can further reduce grid voltage, improves the Performance And Reliability of device.

Claims (8)

1. " or not " logical device of a carbon nano tube structure comprises that with Si as substrate, this substrate is provided with SiO ₂Insulating barrier is at the SiO of Si substrate ₂Carbon nano-tube, grid and electrode are set on the insulating barrier; It is characterized in that: described grid comprises two independently grids, is being positioned at SiO on the Si substrate ₂The Al that deposits among two grooves adjacent one another are in the insulating barrier, and the Al that forms through surface oxidation ₂O ₃Insulating barrier constitutes, the Al of grid ₂O ₃Thickness of insulating layer is the 2-3 nanometer; Described electrode comprises two independently electrodes, is positioned at SiO on the Si substrate ₂Etch two grooves in the insulating barrier, and the depositing noble metal layer constitutes among groove, two absolute electrodes are in the outside of two independent gates; Carbon nano-tube is straight to be placed on described SiO ₂On the surface of insulating barrier, with the Al of grid ₂O ₃The layer of precious metal surface of surface of insulating layer and described two absolute electrodes contacts, and an electrode is connected with constant pressure source, and another electrode is an output; Grid is as input.

2. " or not " logical device of carbon nano tube structure according to claim 1 is characterized in that: the upper surface of electrode and SiO ₂The upper surface of insulating barrier maintains an equal level.

3. " or not " logical device of carbon nano tube structure according to claim 1, it is characterized in that: the degree of depth of described groove is between 10nm to 95 μ m.

4. " or not " logical device of a carbon nano tube structure comprises that with Si as substrate, this substrate is provided with SiO ₂Insulating barrier is at the SiO of Si substrate ₂Carbon nano-tube, grid and electrode are set on the insulating barrier; It is characterized in that: described grid comprises two independently grids, is being positioned at SiO on the Si substrate ₂The Al that deposits among two grooves adjacent one another are in the insulating barrier, and the Al that forms through surface oxidation ₂O ₃Insulating barrier constitutes, the Al of grid ₂O ₃Thickness of insulating layer is the 2-3 nanometer; Described electrode comprises two independently electrodes; The straight SiO that is placed on of carbon nano-tube ₂On the surface of insulating barrier, with the Al of grid ₂O ₃Surface of insulating layer contacts, and prepares two independently electrodes on carbon nano-tube, and an electrode is connected with constant pressure source, and another electrode is an output; Grid is as input.

5. according to " or not " logical device of claim 1 or 4 described carbon nano tube structures, it is characterized in that: described SiO ₂The thickness of insulating barrier is between 35nm to 100 μ m.

6. according to " or not " logical device of claim 1 or 4 described carbon nano tube structures, it is characterized in that: described grid and distance between electrodes are between 5nm to 100 μ m, and the width of grid and electrode is between 10nm to 90 μ m.

7. according to " or not " logical device of claim 1 or 4 described carbon nano tube structures, it is characterized in that: the Al of grid ₂O ₃Thickness of insulating layer is between 1nm to 5nm.

8. according to " or not " logical device of claim 1 or 4 described carbon nano tube structures, it is characterized in that: the SiO of the upper surface of grid and Si substrate ₂The insulating barrier upper surface maintains an equal level.

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