CN1236493C - Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method - Google Patents
Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method Download PDFInfo
- Publication number
- CN1236493C CN1236493C CN 02131272 CN02131272A CN1236493C CN 1236493 C CN1236493 C CN 1236493C CN 02131272 CN02131272 CN 02131272 CN 02131272 A CN02131272 A CN 02131272A CN 1236493 C CN1236493 C CN 1236493C
- Authority
- CN
- China
- Prior art keywords
- tube
- carbon
- carbon nano
- carbon nanometer
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a single electron memory using vertical stratification carbon nanometer tube transistors for design and a manufacturing method thereof. The single electron memory comprises a substrate, wherein a SiO2 insulating layer is formed on the substrate through oxidation; a vertical stratification carbon nanometer tube transistor is prepared on the SiO2 insulating layer, and a semiconductor single-wall carbon nanometer tube is arranged on the carbon nanometer tube; a source electrode and a drain electrode are prepared on both sides of the SiO2 insulating layer and generate ohmic contact with the SiO2 insulating layer; a very thin grid electrode insulating layer is prepared above the carbon nanometer tube, and a grid electrode of the carbon nanometer tube transistor is arranged on the grid electrode insulating layer; a metal word line of the single electron memory is arranged on the grid electrode insulating layer on one side of the grid electrode; the metal word line and the grid electrode are connected together through a metal carbon nanometer tube; at least two tunnel through junctions are prepared on the metal carbon nanometer tube. Quantum dots prepared by the method can generate a coulomb blockade phenomenon at a room temperature, so the single electron memory can work at room the temperature. By measuring the current of the drain electrode of the carbon nanometer tube transistor, the date of the single electron memory can be read out.
Description
Technical field
The invention belongs to memory, particularly relate to a kind of single-electron memory with high integration and preparation method that can at room temperature work who utilizes quantum dot coulomb blockade effect and have the carbon nanometer transistor design preparation of vertical stratification.
Background technology
In the past few decades, microelectronics and computer technology have obtained development at full speed, and according to so-called Moore's Law, the chip integration that characterizes memory technology quadrupled in per 3 years.But along with the device that chip is integrated is more and more, the yardstick of device is just moving closer to its physics limit.Therefore, seek that size is little, cost is low, speed is fast, the memory device of good stability, and the Highgrade integration of realization device, the critical problem that has become semi-conductor industry and faced.
At present, people have begun the memory device of nanometer scale is studied, and hope can be found the way of dealing with problems.In the past few years, research work mainly concentrates on the single-electron device, and some devices based on the single electron phenomenon are produced out, and demonstrates stable operating state under certain condition.These Monoelectron memory devices can be divided into following three classes by the difference of structure: (1) quantum dot is as the floating boom of device, utilize the drift of threshold voltage realize information storage (Jpn.J.Appl.Phys.2000, Part 2,39, L792); Integrated between (2) two single-electronic transistors (SET), SET is used for controlling the charge number in the quantum dot, another plays electrometer, be used for surveying the extra electron number of storing in the storage node, realize the read-write capability (Appl.Phys.Lett.1998 of memory like this, 73,2134); (3) single-electronic transistor and conventional MOS FET's is integrated, read (Appl.Phys.Lett., 1999,74,1293) that rely on MOSFET to realize data.Although these devices have solved the difficulty that some single-electron memories run into, also there are some difficulties.First kind device is stranded for the size of quantum dot can therefore can realize the storage of data at normal temperatures, but device stores character is subjected to the influence of quantum dot position and its size fluctuation, and the holding time be very short below 10 nanometers, have only hundreds of second usually.A single-electronic transistor in the second class memory is as electrometer, the source drain bias is very big during work, the size of its drain current presents linear relationship to the extra electron number of storing in the storage node, but the gain of device work this moment is very little, is unfavorable for reading of device data; The working temperature of sort memory is very low in addition.Utilize single-electronic transistor and traditional MOSFET can solve data and read the little problem of gain, but the number of electrons of device need of work has increased, at least need up to a hundred, in fact because the existence of MOSFET makes the problem of puzzlement conventional semiconductors industry still not obtain solution fundamentally, the integrated level that is to say device will be subjected to the restriction of MOSFET, and device still is difficult to realize the work under the normal temperature in addition.This shows, must find have more high integration, more high workload frequency and the more single-electron memory and the preparation method of elevated operating temperature.
Summary of the invention
The objective of the invention is in order to solve the difficulty that the development of legacy memory and single-electron memory is faced; In order to improve the working temperature of memory; For storage density and the operating frequency that improves memory, finally realize the ultrahigh density storage of information; Thereby provide a kind of single-electron memory that utilizes the coulomb blockade effect of quantum dot in the carbon nano-tube and have the carbon nanometer transistor structural design high integration of vertical stratification.
The object of the present invention is achieved like this:
Single-electron memory with the design of vertical stratification carbon nano-tube provided by the present invention comprises: as substrate, oxidation forms a silicon dioxide insulating layer on it with silicon; Prepare the carbon nanometer transistor of a vertical stratification on insulating barrier, it is included in a single wall semiconductive carbon nano tube is set on the silicon dioxide insulating layer, prepares source electrode and drain electrode at its two ends, and with this carbon nano-tube generation ohmic contact; On the whole silicon dioxide insulating layer above this carbon nano-tube, source electrode and the drain electrode, prepare one deck gate insulator, and in the square-shaped gate that carbon nanometer transistor is set on the gate insulator above this carbon nano-tube, between source electrode and the drain electrode; The metal word lines of one memory is set on the gate insulator of the corresponding side of square-shaped gate, metal word lines and square-shaped gate link together by second carbon nano-tube ohmic contact, it is vertical with first carbon nano-tube direction that its second carbon nano-tube is provided with direction, and have at least two tunnel junctions on second carbon nano-tube.
Described backing material comprises p type or n type silicon.
Silicon dioxide layer thickness on the described substrate is 1 nanometer to 100 micron;
Carbon nano-tube in the described carbon nanometer transistor is the single wall semiconductive carbon nano tube, and its diameter is less than 3 nanometers.
The material of described gate insulator comprises: silicon dioxide, Si
3N
4Deng, because just playing buffer action, this gate insulator gets final product.
The source electrode of described carbon nanometer transistor and drain electrode are prepared by metals such as Al, Au, Pt or Ti, and thickness does not have strict requirement, and the effect of only playing electrode gets final product; Wherein the distance between source electrode and the drain electrode is 1 nanometer to 1 millimeter.
The grid material of described carbon nanometer transistor is that metal comprises: metals such as Al, Au, Pt or Ti, or the silicon after mixing, its thickness are 1 nanometer to 1 micron; The area of described grid is less than 1 square millimeter.
Carbon nano-tube between described metal word lines and the grid is a metallic carbon nanotubes, and its diameter is not placed restrictions on.
Described metal word lines comprises: the preparation of metals such as Al, Au, Pt or Ti, its thickness is identical with grid; Wherein the distance between metal word lines and the grid is 1 nanometer to 1 millimeter.
Tunnel junctions on the described carbon nano-tube forms carbon nano-tube generation local deformation by the scan-probe technology; Two adjacent on carbon nano-tube tunnel junctions spacings are less than 100 nanometers;
The preparation method of the single-electron memory of the carbon nanometer transistor design of usefulness vertical stratification of the present invention comprises the steps:
(1) with silicon chip as substrate, by conventional semiconductor technology silicon chip is mixed, form the silicon substrate of p type or n type; Utilize the method for conventional dried oxygen or wet oxygen to prepare the layer of silicon dioxide insulating barrier thereon, its thickness is 1 nanometer-100 micron;
(2) on silicon dioxide insulating layer, utilize the single wall semiconductive carbon nano tube in atomic force microscope location, and routine utilizes photoetching and lift-off technology to prepare the source electrode and the drain electrode of carbon nanometer transistor at the two ends of carbon nano-tube;
(3) and then above semiconductive carbon nano tube, source electrode and drain electrode, prepare a gate insulator, its thickness is less than 500 nanometers; And utilize electron beam lithography and lift-off technology thereon above this root carbon nano-tube, prepare thickness and be 1 nanometer-100 micron carbon nanometer transistor grid and and prepare a metal word lines at corresponding another side of grid;
(4) metallic carbon nanotubes in location between metal word lines and grid, and utilize the scan-probe technology on metallic carbon nanotubes, make carbon nano-tube generation local deformation form tunnel junctions, be no less than two tunnel junctions on this carbon nano-tube, the spacing of adjacent two tunnel junctions is less than 100 nanometers; At last device is encapsulated the preparation of just having finished memory of the present invention.
The described method for preparing tunnel junctions on metallic carbon nanotubes is to utilize probe to make the local generation of metallic carbon nanotubes deformation, and the carbon nanotube properties of deformation place changes, and so just forms a tunnel junctions.
Single-electron memory with high integration of the present invention has two carbon nano-tube, wherein metallic carbon nanotubes has the quantum dot of one or more nanoscales, utilize the coulomb blockade effect of quantum dot, the grid voltage of controlling filed effect transistor is realized the storage of data; Another root semiconductive carbon nano tube has then constituted the carbon nanometer transistor structure.
Memory operate as normal of the present invention has two primary conditions: (1) the coulomb blockade zone can occur to such an extent as to the quantum dot between two tunnel junctions is enough little on the metallic carbon nanotubes, and this coulomb blockade zone wants enough big; (2) grid of carbon nanometer transistor can have two stable store statuss as the storage area of memory extra electron, it is enough big that the difference of the carbon nanometer transistor drain current of these two stable storage state correspondences is wanted, with the assurance memory data and the information that deposit in of read-out system exactly.
The invention has the advantages that:
Memory of the present invention utilizes carbon nanometer transistor to replace traditional MOSFET just and obtains higher integrated level.Device uses traditional many tunnel junctions (MTJ) structure of the replacement of the quantum dot between two tunnel junctions on the metallic carbon nanotubes, the large-area grid that exhaust have been saved, can make full use of unique electrical, mechanics and the chemical property of carbon nano-tube, therefore the memory construction of designing has higher storage density than the single-electron memory that designs based on MTJ/MOSFET in the past, and operate as normal at room temperature, so sort memory has not only solved the difficulty that legacy memory faces, also improved the performance of Monoelectron memory device; Simultaneously, the chemical inertness of carbon nano-tube and good toughness have determined device to have very long useful life, these advantages make the predicament that the present invention is faced in can the evolution of fine solution memory, compare with the memory of other type, have many-sided advantage.In a word, single-electron memory of the present invention has the following advantages than legacy memory: 1) simple in structure; 2) be easy to integrated; 3) operating frequency height; 4) storage density is big; 5) low in energy consumption; 6) heat dissipation capacity is little; 7) working temperature is a room temperature; 8) preparation method is simple, is easy to suitability for industrialized production.
Description of drawings
The perspective view of Fig. 1 memory device of the present invention.
The sectional side view of Fig. 2 memory device of the present invention.
Metallic carbon nanotubes generation deformation forms the schematic diagram of tunnel junctions in Fig. 3 memory device of the present invention.
The triangular pulse voltage of Fig. 4 memory input of the present invention different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor.
The square wave pulse voltage of Fig. 5 memory input of the present invention different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor.
Indicate among the figure:
1. substrate 2. silicon dioxide insulating layers 3. source electrodes 4. drain electrodes
5. semiconductive carbon nano tube 6. gate insulators 7. grids 8. metal word lines
9. metallic carbon nanotubes 10. tunnel junctions 11. quantum dots
Embodiment
Embodiment 1:
Press the structure fabrication of Fig. 1, and structure of the present invention be elaborated in conjunction with manufacture method:
The p type monocrystalline silicon of selecting (100) direction for use is as substrate 1, and resistivity is 0.005-0.01 Ω cm.Utilize conventional dry-oxygen oxidation method, oxidizing temperature is 900 ℃, and oxidation goes out the silicon dioxide insulating layer 2 of one 120 nanometer thickness on substrate 1.Utilize atomic force microscope with one long be that 400 nanometers, diameter are that the single wall semiconductive carbon nano tube 5 of 2 nanometers is positioned on the silicon dioxide insulating layer 2, one side and with the be arrangeding in parallel of substrate.Adopt conventional filming technology, preparing a thickness is the metal Ti/Au layer of 100 nanometer thickness, utilize electron beam lithography and lift-off technology again, prepare the Ti/Au metal source 3 and the drain electrode 4 of carbon nanometer transistor at the two ends of semiconductive carbon nano tube 5, the two poles of the earth are leaked at a distance of 300 nanometers in the source; Wherein the length of source-drain electrode is 50 microns, and wide is 50 microns, and height is 70 nanometers.Then, adopt common process, deposit the SiO of one deck 15 nanometer thickness
2As gate insulator 6, as shown in Figure 2.Above the gate insulator 6 of semiconductive carbon nano tube 5 correspondences, the material that re-uses is that Au prepares the Au metal level, utilize electron beam lithography and lift-off technology to prepare the metal A u grid 7 of carbon nanometer transistor and prepare metal A u word line 8 at grid 7 corresponding another sides; Wherein grid 7 length are 50 nanometers, and metal word lines length is 500 microns, and metal word lines 8 and grid 7 spacings are 500 nanometers, and as shown in Figure 1, wherein grid is identical with word line thickness.
Utilize atomic force microscope to be decided to be a metallic carbon nanotubes 9 between metal word lines 8 and grid 7, length is 600 nanometers, and diameter is 2 nanometers; Utilize the scan-probe technology to make twice deformation takes place on the carbon nano-tube 9, the deformation of every place has formed a tunnel junctions, and the spacing of two tunnel junctions 10 is 25 nanometers, has so just formed quantum dot 11, as shown in Figure 3.At last device package has just been finished the preparation of the utility model memory.
Embodiment 2:
The n type monocrystalline silicon of selecting (100) direction for use is as substrate 1, and resistivity is 0.005-0.01 Ω cm.On substrate 1, utilize conventional dry-oxygen oxidation method, prepare the silicon dioxide insulating layer 2 of one 10 micron thickness, its upper edge directions X be provided with one long be that 400 nanometers, diameter are the single wall semiconductive carbon nano tube 5 of 3 nanometers; With source electrode 3 and the drain electrode 4 of metal Ti/Au preparation at the carbon nanometer transistor at semiconductive carbon nano tube two ends, source-drain electrode is at a distance of 300 nanometers; Wherein the length of source-drain electrode is 50 microns, and wide is 50 microns, and height is 700 nanometers; The gate insulator 6 that layer of silicon dioxide is arranged on this carbon nano-tube 5, its thickness are 40 nanometers.Above the gate insulator of semiconductive carbon nano tube 5 correspondences, the Ti metal gates 7 and the word line 8 of this carbon nanometer transistor is set, wherein grid 7 length are 50 nanometers, its thickness is 800 nanometers; Word line length is 500 microns, and word line 8 and grid 7 spacings are 500 nanometers, and it is highly fair; As shown in Figure 1.
Utilize atomic force microscope to be set at a metallic carbon nanotubes 9 between word line 8 and grid 7, length is 600 nanometers, and diameter is 2 nanometers; Utilize the scan-probe technology to make twice deformation takes place on the carbon nano-tube 9, the deformation of every place has formed a tunnel junctions, and the spacing of two tunnel junctions 10 is 25 nanometers, has so just formed quantum dot 11, as shown in Figure 3.At last device package has just been finished the preparation of memory of the present invention.
The operation principle of the single-electron memory of the carbon nanometer transistor design with vertical stratification of the present invention is described as follows:
Utilize atomic force microscope (AFM) to make metallic carbon nanotubes 9 many places that local deformation take place, according to the electronic transport characteristic of carbon nano-tube as can be known: each deformation place of carbon nano-tube can form a tunneling barrier.The material of supposing gate insulator 6 and oxidation insulating layer 2 is silicon dioxide, only prepare two tunnel junctions (spacing is usually between several nanometers to tens nanometer) on the metallic carbon nanotubes 9, and the exchange of electronics can only realize by the tunnel junctions on the tunnelling metallic carbon nanotubes 9 in word line and the grid 7, has formed the quantum dot 11 of a nanoscale on this moment carbon nano-tube between two tunnel junctions.The energy that increasing an extra electron in this quantum dot 11 needs is:
C wherein
∑ 2Be the total capacitance of the quantum dot 11 that forms between two tunnel junctions on the metallic carbon nanotubes 9, Δ E is the spacing of quantum dot 11 discrete energy levelss.If by the spacing of two tunnel junctions on the controlling carbon nanotube, make C
∑ 2Enough Grain Full foot E
Add＞k
BT, wherein k
BBe Boltzmann constant, T is an absolute temperature, so just can observe the coulomb blockade effect on metallic carbon nanotubes 9.The coulomb blockade zone of supposing quantum dot 11 on the metallic carbon nanotubes 9 is (V
C,+V
C), if system exceeds the coulomb blockade zone, then need to satisfy condition | V
W(t) |＞V
C, this moment metallic carbon nanotubes 9 to can be regarded as a resistance be R
2Lead (supposing that the contact between electrode and the carbon nano-tube is ohmic contact completely), word line, metallic carbon nanotubes 9 and the grid 7 of this moment will have identical current potential.As the voltage V that is applied on the word line
WWhen (t) being in the coulomb blockade zone, the variation of word line potential will can not cause the variation of grid 7 current potentials, i.e. the number of electrons of grid 7 storages can not change, and the grid 7 of this moment can be regarded as an isolated charge storage part.If on word line, apply a triangular pulse voltage V
W(t), when the system under this voltage is in the coulomb blockade zone, grid 7 current potential V
MCan not change, when word line voltage exceeds the coulomb blockade zone, grid 7 current potential V
MTo satisfy constantly:
V
M(t)＝V
W(t)
Specifically, if apply as shown in Figure 4 the voltage of writing, rise to+V by 0 at voltage
CProcess in, system is in the coulomb blockade zone, the attitude of will remaining stationary of the current potential in the grid 7; At current potential by+V
CRising to maximum also reduces to+V once more
CProcess in, because system has exceeded the coulomb blockade zone of quantum dot 11, so device grids 7 is in the identical state of current potential constantly with word line, if grid 7 Central Plains current potentials are 0, this moment, electronics will be entered in the word line by metallic carbon nanotubes 9 by grid 7, the electric capacity of word line can be thought infinity, and the change of wherein limited number of electrons can not cause the change of its Fermi level; But when word line voltage by+V
CWhen dropping to 0 current potential, system is in the coulomb blockade state once more, so in the process of word line voltage decline, the electronics in the word line can't enter grid 7 by metallic carbon nanotubes 9, this moment, grid 7 became an isolated charge storage part, and its current potential will remain on+V
C, as Fig. 4.In like manner, utilize reciprocal potential pulse just can realize that grid 7 current potentials are-V
CStore status.Utilize square wave can realize writing of data equally, its detailed process can be described with Fig. 5.The part that grid 7 current potentials dot in Fig. 4 and Fig. 5 is not represented actual change procedure, determine that dotted line has represented that just a kind of of grid 7 current potentials may change because the change procedure of dotted portion representative is by the storage history of this memory cell and the voltage on the word line is common.
This shows, when grid 7 is in+V
CCurrent potential the time, memory cell is in a stable store status, grid 7 during with respect to electric neutrality the change amount of number of electrons be:
C in the formula
∑ MBe the total capacitance of grid 7, can be expressed as:
Wherein ε is the dielectric constant of silicon dioxide, and S is the area of grid 7, and d is the distance of grid 7 and substrate 1, C
0Be other some electric capacity, as the electric capacity of: grid 7 with semiconductive carbon nano tube 5 and metallic carbon nanotubes 9, the electric capacity between grid 7 and two electrodes and the word line etc., these electric capacity are very little, can ignore, so equation (1) can be written as:
The number of electrons that this shows need of work depends mainly on the size in quantum dot 11 coulomb blockade zones on the size of distance between grid 7 and the silicon substrate 1, grid 7 and the metallic carbon nanotubes 9.Therefore can draw electronics of control just can realize the memory cell operate as normal the condition that should satisfy be:
In like manner, the memory cell that satisfies above-mentioned condition reaches grid 7 current potentials and is-V
CExtra electron number during pairing store status in the grid 7 is one.The number of electrons that need control during memory cell work is few more, and the power consumption of device is just low more, and operating frequency is also just fast more.If on the metallic carbon nanotubes 9 between two tunnel junctions coulomb blockade of quantum dot 11 zone magnitude be 10-
1V, grid is 10 to the magnitude apart from d of silicon substrate
-8M, grid 7 areas are near 1000nm in the time of can knowing that according to equation (2) electronics of memory control is realized state-transition
2
Memory device of the present invention is to utilize the carbon nanometer transistor with vertical stratification to realize reading of data, the storage area of the extra electron of device stores unit is the grid of carbon nanometer transistor, the current potential of change grid 7 can change the carrier concentration in the carbon nano-tube, therefore under the same source drain bias, the size of drain current can reflect the difference of grid potential, be to have stored how many extra electrons in the grid 7, which kind of store status is memory cell be in.If the carbon nano-tube in the carbon nanometer transistor is not mixed, the charge carrier among the CNT is based on the hole.In order to guarantee the reliability of data read, must improve the mutual conductance of carbon nanometer transistor, just like this in the grid 7 change of voltage can cause enough changes of tangible drain current, the realization device is to the read functions of information.Electric capacity between semiconductive carbon nano tube 5 and the grid 7 can be similar to and be written as:
C
Ml＝2πεL/log(2h/r)
Wherein L is the width of grid 7 near that side of semiconductive carbon nano tube 5, and ε is a dielectric constant, and r is the diameter of semiconductive carbon nano tube 5, and h is the distance between semiconductive carbon nano tube 5 and the grid 7.The hole distribution of supposing semiconductive carbon nano tube 5 in the carbon nanometer transistor is that the length of carbon nano-tube is L between two electrodes uniformly
1, the hole line density is τ, then grid 7 is at+V
CWith-V
CThe change amount of carrier concentration is when changing between the two states:
Can simply think L ≈ L
1, so the relative increment of carrier concentration is main relevant with following three factors: the big or small V in quantum dot 11 coulomb blockade zones in the size of memory cell, semiconductive carbon nano tube 5 and grid 7 spacing h and the metallic carbon nanotubes 9
CThe raising that this shows memory device stores performance of the present invention mainly relies on two aspects: on the one hand be the distance that reduces on the metallic carbon nanotubes 9 between two tunnel junctions, increase the width in quantum dot 11 coulomb blockade zones, this is because can reduce its total capacitance by the size that reduces quantum dot 11, and the size in coulomb blockade zone and quantum dot 11 total capacitances are inversely proportional to; Be the distance that reduces between grid 7 and the semiconductive carbon nano tube 5 on the other hand, improve the mutual conductance of carbon nanometer transistor, improve the accuracy of data read.The increase of number of electrons if keep the less work number of electrons, just must further reduce the size of grid 7 in the memory cell when yet the effort of these two aspects all can cause memory operation of the present invention as can be seen by equation (1).The memory property that this shows device 1 is determined by three aspects: the size of grid 7; The spacing of grid 7 and semiconductive carbon nano tube 5; The spacing of two tunnel junctions on the metallic carbon nanotubes 9.
Memory operation frequencies of the present invention can be represented with following formula:
f∝(R
tC
M)
-1 (3)
R wherein
tThe tunnelling resistance of metallic carbon nanotubes 9 when exceeding the coulomb blockade zone for system, C
MTotal capacitance for grid 7.Suppose that grid 7 total capacitances can be expressed as when system exceeded the coulomb blockade zone:
C
M∝AD
-1 (4)
Wherein A is the area of grid 7, and D is the distance between grid 7 and the conductive substrates.Therefore the operating frequency of device can be expressed as:
f∝(R
tA)
-1D
This shows that the operating frequency of device is relevant with the resistance of metallic carbon nanotubes 9, and is relevant with the area of grid 7, and the distance dependent between grid 7 and the conductive substrates.If D is very big, the C in the equation (3)
MCan not represent with equation (4) because this moment grid 7 electric capacity be mainly it from holding.If will improve the operating frequency of memory of the present invention, mainly consider during preparation: reduce the physical dimension of grid 7 on the one hand by the level that improves preparation technology, the number of electrons of the required control of minimizing work from following two aspects; On the other hand, reduce the tunnelling resistance of metallic carbon nanotubes 9.For the holding time of data, mainly be by the macroscopical tunneling effect decision of metallic carbon nanotubes 9 quantum dots, improve the data holding time and mainly be by on metallic carbon nanotubes 9, preparing a plurality of tunnel junctions and form a plurality of quantum-dot structures and realize, because such structure can effectively suppress macroscopical tunneling effect of quantum, thereby reach the purpose of the holding time of improving data.
Claims (10)
1. single-electron memory with vertical stratification carbon nano-crystal body pipe design comprises: with silicon as substrate, silicon dioxide insulating layer of oxidation formation it on; Prepare a carbon nanometer transistor on insulating barrier, it is included in a Single Walled Carbon Nanotube is set on the silicon dioxide insulating layer, prepares source electrode and drain electrode at its two ends, and with this carbon nano-tube generation ohmic contact; It is characterized in that: on the whole silicon dioxide insulating layer above this carbon nano-tube, source electrode and the drain electrode, prepare one deck gate insulator, and in the square-shaped gate that carbon nanometer transistor is set on the gate insulator above this carbon nano-tube, between source electrode and the drain electrode; The metal word lines of one memory is set on the gate insulator of the corresponding side of square-shaped gate, metal word lines and square-shaped gate link together by second carbon nano-tube ohmic contact, it is vertical with first carbon nano-tube direction that its second carbon nano-tube is provided with direction, has at least two tunnel junctions on second carbon nano-tube.
2. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: described silicon substrate material comprises p type or n type monocrystalline silicon.
3. by the single-electron memory of the described carbon nanometer transistor design with vertical stratification of claim 1, it is characterized in that: the silicon dioxide layer thickness on the described substrate is 1 nanometer to 100 micron.
4. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: the source electrode of described carbon nanometer transistor and drain material comprise what Al, Au, Pt or Ti metal material prepared.
5. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: the grid material of described carbon nanometer transistor comprises: the silicon after Al, Au, Pt, Ti metal or the doping; Its thickness is 1 nanometer to 1 micron; The area of its grid is less than 1 square millimeter.
6. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: the carbon nano-tube in the described carbon nanometer transistor is the single wall semiconductive carbon nano tube, and its diameter is less than 3 nanometers.
7. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: the carbon nano-tube between described word line and the grid is a metallic carbon nanotubes.
8. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: two adjacent on described carbon nano-tube tunnel junctions spacings are less than 100 nanometers.
9. by the described single-electron memory that designs with the carbon nanometer transistor of vertical stratification of claim 1, it is characterized in that: the material of described gate insulator comprises: silicon dioxide, Si
3N
4
10. method for preparing the single-electron memory of the described carbon nanometer transistor design with vertical stratification of claim 1 is characterized in that: may further comprise the steps:
(1) with silicon chip as substrate, by conventional semiconductor technology silicon chip is mixed, form the silicon substrate of p type or n type; Utilize the method for conventional dried oxygen or wet oxygen to prepare the layer of silicon dioxide insulating barrier thereon, its thickness is 1 nanometer-100 micron;
(2) on silicon dioxide insulating layer, utilize the single wall semiconductive carbon nano tube in atomic force microscope location, and utilize conventional photoetching and lift-off technology to prepare the source electrode and the drain electrode of carbon nanometer transistor at the two ends of carbon nano-tube;
(3) adopt and then above semiconductive carbon nano tube, source electrode and drain electrode conventional filming technology to prepare a gate insulator, its thickness is less than 500 nanometers; And utilize electron beam lithography and lift-off technology thereon above this root carbon nano-tube, prepare thickness and be 1 nanometer-100 micron carbon nanometer transistor grid and and prepare a strip metal word line at corresponding another side of grid;
(4) second metallic carbon nanotubes in location between metal word lines and grid, this carbon nano-tube and first perpendicular setting of carbon nano-tube, and utilize the scan-probe technology on this metallic carbon nanotubes, make carbon nano-tube generation local deformation form tunnel junctions, be no less than two tunnel junctions on this carbon nano-tube, the spacing of adjacent two tunnel junctions is less than 100 nanometers; At last device is encapsulated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02131272 CN1236493C (en) | 2002-09-24 | 2002-09-24 | Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02131272 CN1236493C (en) | 2002-09-24 | 2002-09-24 | Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1485915A CN1485915A (en) | 2004-03-31 |
| CN1236493C true CN1236493C (en) | 2006-01-11 |
Family
ID=34144866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02131272 Expired - Fee Related CN1236493C (en) | 2002-09-24 | 2002-09-24 | Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1236493C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882621A (en) * | 2010-05-27 | 2010-11-10 | 复旦大学 | Carbon nanotube network storage and preparation method thereof |
| CN104851900B (en) * | 2015-04-13 | 2019-06-18 | 南昌大学 | A kind of resistance-variable storing device and preparation method based on field-effect tube structure |
-
2002
- 2002-09-24 CN CN 02131272 patent/CN1236493C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1485915A (en) | 2004-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| McEuen | Single-wall carbon nanotubes | |
| US7826336B2 (en) | Data storage nanostructures | |
| Chaudhury et al. | Carbon nanotube and nanowires for future semiconductor devices applications | |
| CN1236493C (en) | Single electron memory using vertical stratification carbon nanometer transistor for design and its manufacturing method | |
| CN1262013C (en) | Single electron memory using vertical stratification carbon nanometer transistor at double ends and its manufacturing method | |
| CN1252817C (en) | Single electron memory having carbon nano tube structure and process for making it | |
| CN1228855C (en) | Single-electron storage designed based on coulomb damping principle and its preparing method | |
| CN2570984Y (en) | High integration density single electron memory designed with nanometer carbon tube transistor | |
| Ramezani et al. | Fundamental phenomena in nanoscale semiconductor devices | |
| CN1262011C (en) | Single electron memory workable under room temperature and method for making the same | |
| CN2552169Y (en) | Single electronic memory with carbon nano-tube structure | |
| CN2575853Y (en) | Improved connector | |
| CN1262007C (en) | Single electron memory having carbon nano tube structure and process for making it | |
| CN2562370Y (en) | One electron memory at ambient temperature | |
| CN1253941C (en) | Single electron memory having high integration level and method for making the same | |
| Mizuta et al. | Bottom-up approach to silicon nanoelectronics | |
| CN1262006C (en) | Single electron memory having carbon nano tube structure and process for making it | |
| CN2566464Y (en) | Single electronic memory with high integrated level capable of working under room temp | |
| Chen | Nanotubes for nanoelectronics | |
| CN2567781Y (en) | Memory designed with carbon nano-pipe one-electron transistor and carbon nano-pipe transistor | |
| Tsuya et al. | Quantum dots and their tunnel barrier in semiconducting single-wall carbon nanotubes with a p-type behavior | |
| CN2567780Y (en) | One-electron memory based on carbon nano-pipe one-electron transistor | |
| CN1472814A (en) | Mono-electron memory based on carbon nanometre tube Mono-electron transistor design and manufacture thereof | |
| CN1248313C (en) | Carbon nano tube logic OR gate device and preparation method thereof | |
| CN1236495C (en) | Carbon nano tube NOR logic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060111 Termination date: 20120924 |