CN2570984Y - High integration density single electron memory designed with nanometer carbon tube transistor - Google Patents
High integration density single electron memory designed with nanometer carbon tube transistor Download PDFInfo
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- CN2570984Y CN2570984Y CN 02257077 CN02257077U CN2570984Y CN 2570984 Y CN2570984 Y CN 2570984Y CN 02257077 CN02257077 CN 02257077 CN 02257077 U CN02257077 U CN 02257077U CN 2570984 Y CN2570984 Y CN 2570984Y
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Abstract
The utility model relates to a high integration density single electron memory designed with a nanometer carbon tube transistor, which comprises a substrate which is made of silicon, a silicon dioxide insulating layer which is oxygenized on the substrate, and the nanometer carbon tube transistor prepared on the insulating layer. The utility model also comprises a single-walled nanometer carbon tube which is arranged on the silicon dioxide insulating layer, wherein, a source electrode and a drain electrode which are arranged on both sides of the single-walled nanometer carbon tube and have ohmic contact with the nanometer carbon tube above which a gate insulation layer is prepared, and a gate of the nanometer carbon tube transistor is arranged on the gate insulation layer; the gate insulation layer on one side of the gate is provided with a word line of the memory, and the word line and the gate are connected by a metal nanometer carbon tube which is provided with at least two tunneling junctions. The coulomb blockade phenomenon of the quantum dots prepared by the utility model can occur at room temperature, so the utility model can work at room temperature, and the data in the memory can be read by measuring the drain current of the nanometer carbon tube transistor.
Description
Technical field
The utility model belongs to memory, particularly relates to a kind of single-electron memory with high integration that can at room temperature work that utilizes quantum dot coulomb blockade effect and have the carbon nanometer transistor design preparation of vertical stratification.
Background technology
In the past few decades, microelectronics and computer technology have obtained development at full speed, and according to so-called Moore's Law, the chip integration that characterizes memory technology quadrupled in per 3 years.But along with the device that chip is integrated is more and more, the yardstick of device is just moving closer to its physics limit.Therefore, seek that size is little, cost is low, speed is fast, the memory device of good stability, and the Highgrade integration of realization device, the critical problem that has become semi-conductor industry and faced.
At present, people have begun the memory device of nanometer scale is studied, and hope can be found the way of dealing with problems.In the past few years, research work mainly concentrates on the single-electron device, and some devices based on the single electron phenomenon are produced out, and demonstrates stable operating state under certain condition.These Monoelectron memory devices can be divided into following three classes by the difference of structure: (1) quantum dot is as the floating boom of device, utilize the drift of threshold voltage realize information storage (Jpn.J.Appl.Phys.2000, Part 2,39, L792); Integrated between (2) two single-electronic transistors (SET), SET is used for controlling the charge number in the quantum dot, another plays electrometer, be used for surveying the extra electron number of storing in the storage node, realize the read-write capability (Appl.Phys.Lett.1998 of memory like this, 73,2134); (3) single-electronic transistor and conventional MOS FET's is integrated, read (Appl.Phys.Lett., 1999,74,1293) that rely on MOSFET to realize data.Although these devices have solved the difficulty that some single-electron memories run into, also there are some difficulties.First kind device be because the size of quantum dot can therefore can realize the storage of data at normal temperatures, but device stores character is subjected to the influence of quantum dot position and its size fluctuation, and the holding time be very short below 10 nanometers, has only hundreds of second usually.A single-electronic transistor in the second class memory is as electrometer, the source drain bias is very big during work, the size of its drain current presents linear relationship to the extra electron number of storing in the storage node, but the gain of device work this moment is very little, is unfavorable for reading of device data; The working temperature of sort memory is very low in addition.Utilize single-electronic transistor and traditional MOSFET can solve data and read the little problem of gain, but the number of electrons of device need of work has increased, at least need up to a hundred, in fact because the existence of MOSFET makes the problem of puzzlement conventional semiconductors industry still not obtain solution fundamentally, the integrated level that is to say device will be subjected to the restriction of MOSFET, and device still is difficult to realize the work under the normal temperature in addition.This shows, must find have more high integration, more high workload frequency and the more single-electron memory and the preparation method of elevated operating temperature.
Summary of the invention
The purpose of this utility model is in order to solve the difficulty that the development of legacy memory and single-electron memory is faced; In order to improve the working temperature of memory; For storage density and the operating frequency that improves memory, finally realize the ultrahigh density storage of information; Thereby provide a kind of single-electron memory that utilizes the coulomb blockade effect of quantum dot in the carbon nano-tube and have the carbon nanometer transistor structural design high integration of vertical stratification.
The purpose of this utility model is achieved in that
High integration single-electron memory with the carbon nano-tube design provided by the utility model comprises: as substrate, oxidation forms a silicon dioxide insulating layer on it with silicon; Prepare the carbon nanometer transistor of a vertical stratification on insulating barrier, it is included in a single wall semiconductive carbon nano tube is set on the silicon dioxide insulating layer, prepares source electrode and drain electrode at its two ends, and with this carbon nano-tube generation ohmic contact; On the whole silicon dioxide insulating layer above this carbon nano-tube, source electrode and the drain electrode, prepare one deck gate insulator, and in the square-shaped gate that carbon nanometer transistor is set on the gate insulator above this carbon nano-tube, between source electrode and the drain electrode; The metal word lines of one memory is set on the gate insulator of the corresponding side of square-shaped gate, metal word lines and square-shaped gate link together by second carbon nano-tube ohmic contact, it is vertical with first carbon nano-tube direction that its second carbon nano-tube is provided with direction, and have at least two tunnel junctions on second carbon nano-tube.
Described backing material comprises p type or n type silicon.
Silicon dioxide layer thickness on the described substrate is 1 nanometer to 100 micron;
Carbon nano-tube in the described carbon nanometer transistor is the single wall semiconductive carbon nano tube, and its diameter is less than 3 nanometers.
The material of described gate insulator comprises: silicon dioxide, Si
3N
4Deng, because just playing buffer action, this gate insulator gets final product.
The source electrode of described carbon nanometer transistor and drain electrode are prepared by metals such as Al, Au, Pt or Ti, and thickness does not have strict requirement, and the effect of only playing electrode gets final product; Wherein the distance between source electrode and the drain electrode is 1 nanometer to 1 millimeter.
The grid material of described carbon nanometer transistor is that metal comprises: metals such as Al, Au, Pt or Ti, or the silicon after mixing, its thickness are 1 nanometer to 1 micron; The area of described grid is less than 1 square millimeter.
Carbon nano-tube between described metal word lines and the grid is a metallic carbon nanotubes, and its diameter is not placed restrictions on.
Described metal word lines comprises: the preparation of metals such as Al, Au, Pt or Ti, its thickness is identical with grid; Wherein the distance between metal word lines and the grid is 1 nanometer to 1 millimeter.
Tunnel junctions on the described carbon nano-tube forms carbon nano-tube generation local deformation by the scan-probe technology; Two adjacent on carbon nano-tube tunnel junctions spacings are less than 100 nanometers;
The described method for preparing tunnel junctions on metallic carbon nanotubes is to utilize probe to make the local generation of metallic carbon nanotubes deformation, and the carbon nanotube properties of deformation place changes, and so just forms a tunnel junctions.
Single-electron memory with high integration of the present utility model has two carbon nano-tube, wherein metallic carbon nanotubes has the quantum dot of one or more nanoscales, utilize the coulomb blockade effect of quantum dot, the grid voltage of controlling filed effect transistor is realized the storage of data; Another root semiconductive carbon nano tube has then constituted the carbon nanometer transistor structure.
Memory operate as normal of the present utility model has two primary conditions: (1) the coulomb blockade zone can occur to such an extent as to the quantum dot between two tunnel junctions is enough little on the metallic carbon nanotubes, and this coulomb blockade zone wants enough big; (2) grid of carbon nanometer transistor can have two stable store statuss as the storage area of memory extra electron, it is enough big that the difference of the carbon nanometer transistor drain current of these two stable storage state correspondences is wanted, with the assurance memory data and the information that deposit in of read-out system exactly.
Advantage of the present utility model is:
Memory of the present utility model utilizes carbon nanometer transistor to replace traditional MOSFET just and obtains higher integrated level.Device uses traditional many tunnel junctions (MTJ) structure of the replacement of the quantum dot between two tunnel junctions on the metallic carbon nanotubes, the large-area grid that exhaust have been saved, can make full use of unique electrical, mechanics and the chemical property of carbon nano-tube, therefore the memory construction of designing has higher storage density than the single-electron memory that designs based on MTJ/MOSFET in the past, and operate as normal at room temperature, so sort memory has not only solved the difficulty that legacy memory faces, also improved the performance of Monoelectron memory device; Simultaneously, the chemical inertness of carbon nano-tube and good toughness have determined device to have very long useful life, these advantages make the predicament that the utility model is faced in can the evolution of fine solution memory, compare with the memory of other type, have many-sided advantage.In a word, single-electron memory of the present utility model has the following advantages than legacy memory: 1) simple in structure; 2) be easy to integrated; 3) operating frequency height; 4) storage density is big; 5) low in energy consumption; 6) heat dissipation capacity is little; 7) working temperature is a room temperature; 8) preparation method is simple, is easy to suitability for industrialized production.
The perspective view of description of drawings Fig. 1 the utility model memory device.The sectional side view of Fig. 2 the utility model memory device.Metallic carbon nanotubes generation deformation forms the schematic diagram of tunnel junctions in Fig. 3 the utility model memory device.The triangular pulse voltage of Fig. 4 the utility model memory input different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor.The square wave pulse voltage of Fig. 5 the utility model memory input different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor.Indicate among the figure: 1. substrate 2. silicon dioxide insulating layers 3. source electrodes 4. drain electrode 5. semiconductive carbon nano tubes 6. gate insulators 7. grids 8. metal word lines 9. metallic carbon nanotubes 10. tunnel junctions 11. quantum dots
Embodiment
Embodiment 1:
Press the structure fabrication of Fig. 1, and structure of the present utility model be elaborated in conjunction with manufacture method:
The p type monocrystalline silicon of selecting (100) direction for use is as substrate 1, and resistivity is 0.005-0.01 Ω cm.Utilize conventional dry-oxygen oxidation method, oxidizing temperature is 900 ℃, and oxidation goes out the silicon dioxide insulating layer 2 of one 120 nanometer thickness on substrate 1.Utilize atomic force microscope with one long be that 400 nanometers, diameter are that the single wall semiconductive carbon nano tube 5 of 2 nanometers is positioned on the silicon dioxide insulating layer 2, one side and with the be arrangeding in parallel of substrate.Adopt conventional filming technology, preparing a thickness is the metal Ti/Au layer of 100 nanometer thickness, utilize electron beam lithography and lift-off technology again, prepare the Ti/Au metal source 3 and the drain electrode 4 of carbon nanometer transistor at the two ends of semiconductive carbon nano tube 5, the two poles of the earth are leaked at a distance of 300 nanometers in the source; Wherein the length of source-drain electrode is 50 microns, and wide is 50 microns, and height is 70 nanometers.Then, adopt common process, deposit the SiO of one deck 15 nanometer thickness
2As gate insulator 6, as shown in Figure 2.Above the gate insulator 6 of semiconductive carbon nano tube 5 correspondences, the material that re-uses is that Au prepares the Au metal level, utilize electron beam lithography and lift-off technology to prepare the metal A u grid 7 of carbon nanometer transistor and prepare metal A u word line 8 at grid 7 corresponding another sides; Wherein grid 7 length are 50 nanometers, and metal word lines length is 500 microns, and metal word lines 8 and grid 7 spacings are 500 nanometers, and as shown in Figure 1, wherein grid is identical with word line thickness.
Utilize atomic force microscope to be decided to be a metallic carbon nanotubes 9 between metal word lines 8 and grid 7, length is 600 nanometers, and diameter is 2 nanometers; Utilize the scan-probe technology to make twice deformation takes place on the carbon nano-tube 9, the deformation of every place has formed a tunnel junctions, and the spacing of two tunnel junctions 10 is 25 nanometers, has so just formed quantum dot 11, as shown in Figure 3.At last device package has just been finished the preparation of the utility model memory.
As shown in Figure 4, the triangular pulse voltage of the utility model memory input different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor.
As shown in Figure 5, the square wave pulse voltage of the utility model memory input different directions is to the influence of carbon nano-tube grid potential, wherein V
WBe word line voltage, V
MGrid voltage for carbon nanometer transistor
Embodiment 2:
The n type monocrystalline silicon of selecting (100) direction for use is as substrate 1, and resistivity is 0.005-0.01 Ω cm.On substrate 1, utilize conventional dry-oxygen oxidation method, prepare the silicon dioxide insulating layer 2 of one 10 micron thickness, its upper edge directions X be provided with one long be that 400 nanometers, diameter are the single wall semiconductive carbon nano tube 5 of 3 nanometers; With source electrode 3 and the drain electrode 4 of metal Ti/Au preparation at the carbon nanometer transistor at semiconductive carbon nano tube two ends, source-drain electrode is at a distance of 300 nanometers; Wherein the length of source-drain electrode is 50 microns, and wide is 50 microns, and height is 700 nanometers; The gate insulator 6 that layer of silicon dioxide is arranged on this carbon nano-tube 5, its thickness are 40 nanometers.Above the gate insulator of semiconductive carbon nano tube 5 correspondences, the Ti metal gates 7 and the word line 8 of this carbon nanometer transistor is set, wherein grid 7 length are 50 nanometers, its thickness is 800 nanometers; Word line length is 500 microns, and word line 8 and grid 7 spacings are 500 nanometers, and it is highly fair; As shown in Figure 1.
Utilize atomic force microscope to be set at a metallic carbon nanotubes 9 between word line 8 and grid 7, length is 600 nanometers, and diameter is 2 nanometers; Utilize the scan-probe technology to make twice deformation takes place on the carbon nano-tube 9, the deformation of every place has formed a tunnel junctions, and the spacing of two tunnel junctions 10 is 25 nanometers, has so just formed quantum dot 11, as shown in Figure 3.At last device package has just been finished the preparation of the utility model memory.
Claims (9)
1. high integration single-electron memory with carbon nano-crystal body pipe design comprises: with silicon as substrate, silicon dioxide insulating layer of oxidation formation it on; Prepare a carbon nanometer transistor on insulating barrier, it is included in a Single Walled Carbon Nanotube is set on the silicon dioxide insulating layer, prepares source electrode and drain electrode at its two ends, and with this carbon nano-tube generation ohmic contact; It is characterized in that: on the whole silicon dioxide insulating layer above this carbon nano-tube, source electrode and the drain electrode, prepare one deck gate insulator, and in the square-shaped gate that carbon nanometer transistor is set on the gate insulator above this carbon nano-tube, between source electrode and the drain electrode; The metal word lines of one memory is set on the gate insulator of the corresponding side of square-shaped gate, metal word lines and square-shaped gate link together by second carbon nano-tube ohmic contact, it is vertical with first carbon nano-tube direction that its second carbon nano-tube is provided with direction, has at least two tunnel junctions on second carbon nano-tube.
2. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: described backing material comprises p type or n type monocrystalline or polysilicon.
3. by the described high integration single-electron memory with carbon nanometer transistor design of claim 1, it is characterized in that: the silicon dioxide layer thickness on the described substrate is 1 nanometer to 100 micron;
4. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the source electrode of described carbon nanometer transistor and drain material comprise what Al, Au, Pt or Ti metal material prepared.
5. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the grid material of described carbon nanometer transistor comprises: the silicon after Al, Au, Pt, Ti metal or the doping; Its thickness is 1 nanometer to 1 micron; The area of its grid is less than 1 square millimeter.
6. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the carbon nano-tube in the described carbon nanometer transistor is the single wall semiconductive carbon nano tube, and its diameter is less than 3 nanometers.
7. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the carbon nano-tube between described word line and the grid is a metallic carbon nanotubes.
8. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the tunnel junctions on the described carbon nano-tube has 2 at least, and two adjacent tunnel junctions spacings are less than 100 nanometers.
9. by the described high integration single-electron memory with the carbon nanometer transistor design of claim 1, it is characterized in that: the material of described gate insulator comprises: silicon dioxide, Si
3N
4
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02257077 CN2570984Y (en) | 2002-09-24 | 2002-09-24 | High integration density single electron memory designed with nanometer carbon tube transistor |
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| CN 02257077 CN2570984Y (en) | 2002-09-24 | 2002-09-24 | High integration density single electron memory designed with nanometer carbon tube transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582446B (en) * | 2008-05-14 | 2011-02-02 | 鸿富锦精密工业（深圳）有限公司 | Thin film transistor |
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2002
- 2002-09-24 CN CN 02257077 patent/CN2570984Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582446B (en) * | 2008-05-14 | 2011-02-02 | 鸿富锦精密工业（深圳）有限公司 | Thin film transistor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20060111 |
|
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20060111 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |