CN101174637A - Silicon based single electronic memory device with side grid structure and production method thereof - Google Patents
Silicon based single electronic memory device with side grid structure and production method thereof Download PDFInfo
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Abstract
The invention discloses a silicon based single electron memory with a side gate structure, comprising a silicon nanometer crystal coulomb island and a silicon quantum wire conductor, wherein, the silicon nanometer crystal coulomb island is used to store charge and arranged on a top silicon of a SOI base; the silicon quantum wire conductor is used for detecting storage charge. The invention is characterized in that the silicon nanometer crystal coulomb island is adjacent to the silicon quantum wire conductor, and current of the silicon nanometer crystal coulomb island and the silicon quantum wire conductor is controlled by the a floating gate covered on the surface; current of the silicon quantum wire conductor can also be controlled by a side gate separately; the charge enters into the silicon nanometer crystal coulomb island through a silicon nanometer wire passage; two adjacent nanometer metal enclosure gate for controlling entry of single charge and a nanometer metal enclosure gate for storing charge erasing are arranged on the silicon nanometer wire passage. The invention also discloses a manufacture method of silicon base single electron memory with a side gate structure. The invention has the advantages that storage process of each electron depends on quantum coulomb blocking effect, and the storage charge potential field acts on signal current via capacitor coupling, thus detecting storage information of a single charge.
Description
Technical field
The present invention relates to single electronic memory device technical field in the nanoelectronics, relate in particular to a kind of silicon based single electronic memory device and preparation method thereof with side grid structure.
Background technology
Nanoelectronics is one of key areas of nanosecond science and technology, is that microelectronics continues development and the extension to microscopic fields.At present, the characteristic size of very lagre scale integrated circuit (VLSIC) has entered into nanoscale (＜100nm) scope, in the process of cmos device scaled down, the influence of quantum effect has become more and more outstanding.And the nano-solid structural table that the thin film epitaxial growth technology of monoatomic layer, tunnel probe technology, advanced photoetching technique are produced reveals peculiar quantum effect, and people have invented novel quantum devices such as resonant tunneling device, single-electron device, quantum dot device on the basis of these effects.
Single-electron device is to control transporting of single electronics by the coulomb island of nano-scale to carry out work.Along with the development of nanofabrication technique, scientist can be at the size and dimension on nanoscale scope inner control coulomb island, and the thickness of tunnel junctions potential barrier and shape.
On the coulomb island, electron transport bulk is reduced to nanometer scale, causes the remarkable enhancing of quantum limitation effect, and electronics enters coulomb island must tunnelling be passed through.Electric charge potential energy in the coulomb island will repel entering of extraneous electronics, if electronics enters the required charge energy in coulomb island greater than environment thermal energy, this electronics will get clogged.The grid electric field can carry out the electromotive force modulation to the coulomb island by capacitive coupling, and when the energy level in the coulomb island was positioned at the energy window of source electric leakage word bank Fermi level formation, electronics will be by resonance tunneling effect high penetration ground by a coulomb island.Like this, the momentum of electron variation by the coulomb island is shown as the current peak with discrete energy levels feature significantly.
Single electron enters coulomb island can be considered as storing an electric charge, flows out a coulomb island and can be considered as discharging an electric charge.The coulomb island is in the process of this single electron turnover, and electromotive force will have the fluctuating of e/Ctt (wherein Ctt is the whole capacitor on coulomb island).Single electronic memory device is exactly to be used for surveying this device that transports the coulomb potential fluctuating that causes coulomb island owing to single electron so.
Traditional memory is to finish transmission of Information and storage by handling flow of charge, and single-electron memory is exactly to utilize single electron coulomb blockade effect accurately to control several even single electronics just can finish same function.It has the advantage of the following aspects.At first, because this device depends on interelectric repulsive interaction and realize its operation, so it can work under very little size, makes extensive integrated and complicated wiring become possibility.Secondly, it can utilize several electrons seldom to finish basic functions, so the consumption of energy is very little.If can high density integrated, its power consumption will only be 100,000 of present microelectronic transistors circuit/.Be because device size is little at last, only need the tunnelling of several electrons just can finish the transmission of a bit information, than traditional needs about 10
5Electronics about individual participates in the device of tunnelling, and its response speed also is quickish.These advantages of single-electron memory form exactly that the device of integrated circuit is required to be possessed, and are being used for extensive and ultra-large good development potentiality being arranged aspect integrated.
The research in single-electron device field be since Lambe in 1969 and Jaklevic in the structure of similar single electron box, observe electronics quantization phenomenon (specifically please refer to document " Lambe and R.C.Jaklevic; " Charge-quantization studies using tunnel capacitor, the content that " Phys.Rev.Lerr.; vol.22; no.25; pp.1371-1375, June 1969. " put down in writing).
Characteristic and ripe process advantages such as silica-based single-electron device dependence silicon materials are oxidable, in less than the time in 10 years, realized working and room temperature with regard to having obtained diameter less than the crystalline silicon quantum dot of 10nm, and the preparation method of most of silicon based single electron devices can be compatible better with existing silicon CMOS technology, makes the extensive quantum digital integrated circuit of preparation become possibility.
At present semiconductor single-electronic transistor that in the world can working and room temperature is mainly all made successfully on the SOI of thin silicon films substrate.Relative body silicon materials, the oxide isolated buried regions of SOI is opened device and substrate isolation, has alleviated the influence of substrate charge carrier to device, has reduced the parasitic capacitance effect of silicon device, is easy to realize full dielectric isolation, has avoided the interaction between device and the substrate.The silicon fiml of SOI substrate that is used to make single-electron device is all enough thin, is beneficial to and makes small tunnel junction and quantum dot.Along with constantly dwindling of transistor size, the advantage of SOI technology is more and more outstanding.When the transistor on the thin silicon films was opened, the buried oxide interface was in spent condition, and silicon fiml all exhausts.Have anti-irradiation, high temperature resistant, low electric field, high transconductance, good short channel and narrow channel characteristic, be particularly suitable for the application of high speed, low pressure, low consumption circuit.
By 1993, first single-electron memory that at room temperature can observe the single electron storage is succeeded in developing by people such as Yano and Ishii and (specifically be please refer to document " K.Yano; T.Ishii; T.Hashimoto; T.Kobayashi; F.Murai; and K.Seki, " Room-temperaturesingle-electron memory using fine-grain polycrystalline silicon; " in Proc.IEEEInt.Electron Devices Meeting, 1993, pp.541-545. " content put down in writing), the application prospect of single-electron memory just displays.But, only realize under the room temperature single electron storage and do not mean that it just can use in practice, the application that realizes single-electron memory also has a lot of problems to need to solve, as: the compatibility of technology, program speed, memory times etc., in recent years, scientists had been carried out a large amount of work at the aspect of performance that improves single-electron memory.Below listed the design of several typical single-electron memories:
(1) has the single-electron memory of floating gate structure
As shown in Figure 1, Fig. 1 for the structural representation that has the single-electron memory of floating gate structure in the prior art (specifically please refer to document " Shin-ichi O ' UCHI; Takeshi TSUBOKURA; TakuroTAJIMA; Shuhei AMAKAWA; Minoru FUJISHIMA1 and KoichiroHOH1; " Charging and Retention Times in Silicon-Floating-Dot-Single-Electron Memory, the content that " Jpn.J.Appl.Phys.Vol.40 (2001) pp.2041-2045. " put down in writing).It is to put into quantum dot or the quantum dot array of can stored charge using between the raceway groove of common MOSFET and grid, isolate by the thin layer dielectric between quantum dot and raceway groove, electronics passes in and out quantum dot in the mode of tunnelling, owing to there is bigger electric charge coulomb energy, by grid voltage the number of electric charge in the controllable amounts point.Utilize the different potentials on the quantum dot just can control corresponding channel current, so as to influencing the size of channel current.Can know the different conditions of device by measuring this electric current like this.
(2) granular thin film is as the single-electron memory of tunnel junctions
As shown in Figure 2, Fig. 2 is with the single-electron memory structural representation of granular thin film as tunnel junctions in the prior art.It is a kind of design that is put forward by Yano etc., specifically please refer to the content that document " K.Yano; T.Ishii, T.Sano, T.Mine; F.Murai; and K.Seki, " Singleelectron-memory integrated circuit for giga-to-tera bit storage, " IEEE Int.Solid-State Circuits Conf.; 1996, pp.266-267. " is put down in writing.Three main principles have been followed in this design: can at room temperature work; Can suppress the influence of background charge effectively; And can utilize existing processes to make.Its operation principle is similar to the principle of the single-electron memory of floating gate structure, all is to utilize the store status of electric charge in the memory point to come the electric current of Controlling Source between leaking.Under certain bias voltage, electric charge is limited in the film, crosses the size of the electric current of film so as to modulated stream.Aspect the influence that suppresses background charge, when not having background charge,, because the coulomb blockade effect, there is not the raceway groove of conducting in the film if when institute's gate voltage that applies is very little.When gate voltage increases to threshold voltage passage conducting when above, the flow of charge mistake is arranged.When having background charge, the coulomb blockade effect of subregion disappears and the effect of subregion enhancing in addition, and aggregate performance is still when not having enough bias voltages does not have the passage conducting.Because the current path that the memory point of its electric charge and dependence memory point are modulated is all on same granular film, therefore to the bad independent adjusting of the operating state of device.
(3) single-electron memory of side grid structure
As shown in Figure 3, Fig. 3 for the structural representation of the single-electron memory of accurate One-dimensional Quantum lattice array in the prior art (specifically please refer to document " A.Dutta; S.P.Lee; S.Hatatani; and S.Oda; " the content that Silicon-based single-electron memory using a multiple-tunnel junctionfabricated by electron-beam direct writing " Appl.Phys.Lett.75,1422 (1999). " is put down in writing).This is a kind of device of two-dimension plane structure, helps simplifying the technology of preparation.Accurate One-dimensional Quantum lattice array wherein plays the effect of many tunnel junctions, and it can provide higher coulomb blockade energy gap to suppress the fluctuation of background charge.Under certain grid voltage, electronics flows into by many tunnel junctions or flows out storage node, uses the coulomb blockade effect with the distribution of control store electronics in many tunnel junctions.Readout utilizes single-electronic transistor to realize that the charging charge electromotive force on the storage node can influence the energy state of single-electronic transistor quantum dot by capacitive coupling, and then the conducting current of single-electronic transistor is flow through in influence.
The nanometer technology technology of the single-electron memory of side grid structure is tool challenge.If can realize working and room temperature, to the development of single electron logical circuit with use significant.Nakazato in 1994 etc. have produced many statements of account electronic memory (specifically please refer to document " K Nakazato; R J Blaikie; H Ahmed et al; " Single-electron memory "; J.Appl.Phys.75 (10); 1994, p.5123. " content of being put down in writing) of first experiment usefulness on the GaAs material that mixes.The irrelevant many statements of account electronic memory model of proposition such as nineteen ninety-five Likharev and random background charge (specifically please refer to document " K Likharev A Korotokov; " Analysis ofQ0-independent single-electorn systems "; in Int.Workshop ComputationalElectronics; 1995, p.42. " content of being put down in writing).Ahmed group in 1998 has produced many statements of account electronics RAM memory (specifically please refer to document " NJ Stone; H Ahmed; " Silicon single electron memory cell "; Appl.Phys.Lett.73 (15); 1998, the p.2134. " content of being put down in writing) of 4.2K temperature work on the SOI material.Oda group in 1999 has prepared many statements of account electronic memory (specifically please refer to document " A Dutta; S P Lee; S Hatatani; et al; " Silicon-based single-electron memory using amultiple-tunnel junction fabricated by electron-beam direct writing "; Appl.Phys.Lett.75 (10), 1999, the p.1422. " content of being put down in writing) of 20K temperature work on the SIMOX material.Ahmed group in 2000 has realized the integrated memory device of the single electron multiple tunnel junction grid of 65K temperature work and CMOS (specifically please refer to document " Z A K Durrani; A C Irvine; H Ahmed; " Coulomb blockadememory using integrated single-electron transistor/metal-oxide-semiconductortransistor gain cells "; IEEE Electron devices; 47 (12), 2000, the p.2334. " content of being put down in writing).The electricity that Nakajima in 2002 etc. have studied the multiple tunnel junction single-electronic transistor is led mechanism (specifically please refer to document " A.Nakajima; Yuhei Ito; S Yokoyama; " Conductionmechamnism of Si single-electron transistor having a one-dimensional regulararray of multiple tunnel junctions "; Appl.Phys.Lett.81 (4); 2002, p.733. " content of being put down in writing).Amakawa in 2004 have summarized the logic (specifically please refer to the content that document " S Amakawa; et al; " Single-electron logic based onmultiple-tunnel junctions "; Mesoscopic Tunneling Devices; Ed.HiroshiNakashima, 2004:ISBN:81-271-0007-2. " is put down in writing) of multiple tunnel junction single-electron device.
China had also carried out the research work of silicon based single electron device on the SOI substrate in recent years.Inst. of Physics, CAS has carried out the design of the single-electronic transistor of various structures, and developed silicon based single electron transistor (specifically please refer to the content that document " T.H.Wang; H.W.Li and J.M.Zhou; Si single-electron transistors with in-plane point-contact metal gates; Appl.Phys.Lett.78,2160 (2001). " is put down in writing) under the 90K temperature.Technologies such as electron beam lithography and reactive ion etching are adopted in Xi'an University of Technology and Hong Kong University of Science and Thchnology's cooperation, manufactured the silicon single-electronic transistor on the p type SIMOX, can be low-temperature working under the 77K (specifically please refer to the content that document " G.Lu; Z.M.Chen; J.N.Wang, W.K.Ge.Fabrication and characteristics of aSi-based single electron transistor, Chinese J.Semiconductors; 23 (3), 246 (2002). " is put down in writing).Nanjing University has carried out based on the research of the silica-based many quantum dot memories of room temperature of single electron effect (specifically please refer to the content that document " Huang Xinfan; based on the silica-based many quantum dot memories of the room temperature of single electron effect; project of national nature science fund project numbering 60471021, Nanjing University " is put down in writing).
The operation principle of single-electron device relies on the coulomb blockade effect of interelectric coulomb repulsion power for the basis.Single-electron device need inferior 10nm structure just can reach the coulomb energy that overcomes the environment thermal noise at working and room temperature.The nanocrystal silicon particle can substitute the floating boom of storage component part, the stored charge that is distributed on the floating boom demonstrates several attractive characteristics, as comparing with EEPROM, compared durability etc. preferably with flash memory than writing the time faster, being operated under the lower temperature.Certainly, single-electron memory commercially produce become may before, also need to overcome many main challenges.Various single electron memory system architectures are also just in evolution, for example single-electronic transistor trigger, single-electron trap memory, single-electronic transistor toroidal memory, (specifically please refer to document " C.Wasshuber; H.Kosina; S.Selberherr; A comparative study of single-electron memories; IEEE TransElectron.Devices; 45 (11) with irrelevant memory of random background charge and list/archipelago memory etc., 1998, the p.2365. " content of being put down in writing).
The single electron number system mainly is to utilize single electron rotation grid principle, by in the double potential barrier of the single-electronic transistor grid voltage that changes of frequency f in addition, by being increased to, gate voltage surpasses certain threshold value, an electronics is drawn in coulomb island, center from the source electrode randomly, then, reduce gate voltage again, just electronics can be released coulomb island, center, the control gate of this rotation (turnstile) produces stair-stepping electric current ef, whenever rotate a circle just as voltage and just to produce the electronics, show the state that transports of single electron.Because the electric capacity on coulomb island is minimum, compole is short during the discharging and recharging of electric capacity, and the switching speed of device is exceedingly fast.Participated in the achievement in research (specifically please refer to document " H.E.Van den Brom; O.Kerkhof et al; Counting electrons one byone-overview of a joint European research project; IEEE trans.Instrum.Meas.; 52 (2); 2003, the p.584. " content of being put down in writing) of the metering electron stream of six family metering laboratories of European COUNT plan and the realization quantum standard that Chalmers university unites the initial stage of having delivered in 2003.The purpose of COUNT plan is in order to solve and to develop basic instrument and the measurement standard that is used to measure less than the 1nA electron stream.Single-electron device provides high precision to handle and survey the means of the behavior that transports of single electronics.The single electron tunneling device of two complementations of COUNT plan utilization, one of them is used for the single electron pump so that current source to be provided, and single electronics can be stored on coulomb island for a long time, can control the behavior that transports of electronics by gate voltage; Another is used for the single electron counter and is used as ammeter, and the single electron ammeter can detect the transmission of each electronics.
In a word, utilize the coulomb blockade effect and the resonance tunneling effect of single-electron device, can handle the behavior that transports of single electron effectively.Single electronic memory device and electric charge counting detection system thereof have extremely great potential in fields such as mass data storage, quantum signal detection, quantum logic circuit.
Summary of the invention
(1) technical problem that will solve
In view of this, one object of the present invention is to provide a kind of silicon based single electronic memory device with side grid structure, make the storing process of each electronics all depend on quantum coulomb blockade effect, and the stored charge potential field acts on signal code by capacitive coupling, thereby detects unicharged stored information.
Another object of the present invention is to provide a kind of manufacture method with side grid structure silicon based single electronic memory device, make the storing process of each electronics all depend on quantum coulomb blockade effect, and the stored charge potential field acts on signal code by capacitive coupling, thereby detects unicharged stored information.
(2) technical scheme
For reaching an above-mentioned purpose, the invention provides a kind of silicon based single electronic memory device with side grid structure, this silicon based single electronic memory device comprises:
Silicon-on-insulator (SOI) substrate;
The silicon nanometer electricity of being made by top layer silicon on described SOI substrate is led fine rule 5 and silicon quantum wire 14, described silicon nanometer electricity is led fine rule 5 and is parallel to each other with silicon quantum wire 14, silicon quantum wire 14 is used for surveying the stored charge on silicon nanocrystal coulomb island 6, and stored charge is led fine rule 5 by silicon nanometer electricity and entered silicon nanocrystal coulomb island 6;
Being positioned at silicon nanometer electricity leads fine rule 5 centre positions and leads the silicon nanocrystal coulomb island 6 that is used for stored charge that fine rule 5 is connected with silicon nanometer electricity;
Be positioned at that silicon nanometer electricity is led fine rule 5 two ends and lead with silicon nanometer electricity that the first ohmic contact electricity that fine rule 5 is connected is led step 3 and the second ohmic contact electricity is led step 4;
Being positioned at the first ohmic contact electricity leads the first source metal electrode 7 on the step 3 and is positioned at the second ohmic contact electricity and lead the first drain metal electrode 8 on the step 4;
Being positioned at silicon nanocrystal coulomb island 6 both sides silicon nanometer electricity leads first on the fine rule 5 and encloses grid nano-electrode 9, second and enclose grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11, described first encloses grid nano-electrode 9 and second encloses the same side that grid nano-electrode 10 is positioned at silicon nanocrystal coulomb island 6, and described measurements of the chest, waist and hips grid nano-electrode 11 is positioned at the opposite side on silicon nanocrystal coulomb island 6;
Be positioned at that silicon quantum wire 14 is led fine rule 5 opposite sides with respect to silicon nanometer electricity and the 3rd ohmic contact electricity that is connected with silicon quantum wire 14 is led step 15 and the 4th ohmic contact electricity is led step 16;
Being positioned at the 3rd ohmic contact electricity leads the second source metal electrode 19 on the step 15 and is positioned at the 4th ohmic contact electricity and lead the second drain metal electrode 20 on the step 16;
Leading step 15 and the 4th ohmic contact electricity at silicon quantum wire 14 with respect to the 3rd ohmic contact electricity leads step 16 homonymies and leads the 5th ohmic contact electricity that step 15 and the 4th ohmic contact electricity lead between the step 16 at the 3rd ohmic contact electricity and lead step 17;
Be positioned at the 5th ohmic contact electricity and lead metal side gate electrode 18 on the step 17;
Covering silicon nanometer electricity leads fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first and encloses grid nano-electrode 9, second and enclose insulating medium layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11;
Cover the surface metal floating boom 13 on the insulating medium layer 12.
Described silicon nanocrystal coulomb island 6 material therefors are ultra-thin polysilicon film, are used to realize under the room temperature condition that to the strong quantum limitation effect of electric charge, the storing process of each electric charge all depends on quantum coulomb blockade effect.
The potential field of described stored charge acts on signal code by contiguous silicon quantum wire 14 by capacitive coupling, makes silicon quantum wire 14 obtain the stored information of single electric charge.
Described signal code is by metal side gate electrode 18 and/or 13 controls of surface metal floating boom.
The described first ohmic contact electricity is led step 3, the second ohmic contact electricity and is led step 4, the 3rd ohmic contact electricity and lead step 15, the 4th ohmic contact electricity and lead step 16 and the 5th ohmic contact electricity and lead step 17 and be made by the top layer silicon of described SOI substrate.
The described first source metal electrode 7 and the first drain metal electrode 8 are deposited on respectively that the first ohmic contact electricity is led step 3 and the second ohmic contact electricity is led on the step 4, and annealed realization ohmic contact;
Described metal side gate electrode 18 is deposited on the 5th ohmic contact electricity and leads on the step 17, and annealed realization ohmic contact;
The described second source metal electrode 19 and the second drain metal electrode 20 are deposited on respectively that the 3rd ohmic contact electricity is led step 15 and the 4th ohmic contact electricity is led on the step 16, and annealed realization ohmic contact.
Described first encloses grid nano-electrode 9 and second encloses grid nano-electrode 10 and is used to control single electric charge and enters silicon nanocrystal coulomb island 6, realizes unicharged controlled storage;
Described measurements of the chest, waist and hips grid nano-electrode 11 is used for wiping of stored charge on the silicon nanocrystal coulomb island 6.
For reaching above-mentioned another purpose, the invention provides a kind of manufacture method with side grid structure silicon based single electronic memory device, this method comprises:
A, on the insulating layer of silicon oxide of SOI substrate, produce silicon nanometer electricity and lead fine rule 5, silicon quantum wire 14, the first ohmic contact electricity and lead step 3, the second ohmic contact electricity and lead that step 4, the 3rd ohmic contact electricity are led step 15, the 4th ohmic contact electricity leads step 16 and the 5th ohmic contact electricity is led step 17;
B, utilize the mask medium socket to carve to lead the coulomb island window that fine rule 5 is connected, expose the insulating layer of silicon oxide of SOI substrate with silicon nanometer electricity;
C, sputter thin polysilicon layer, the mask medium is fallen in chemical corrosion, forms silicon nanocrystal coulomb island 6 at described coulomb of island window region;
D, deposit form the first source metal electrode 7, the first drain metal electrode 8, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, and annealing realizes ohmic contact;
E, deposit formation first are enclosed grid nano-electrode 9, second and are enclosed grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11;
F, lead fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first at silicon nanometer electricity and enclose grid nano-electrode 9, second and enclose that deposit forms insulating medium layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11;
G, deposit forms surface metal floating boom 13 on insulating medium layer 12;
H, making contact conductor window.
Described steps A comprises: design layout, and utilize photoetching and electron beam lithography on the SOI substrate of overlay electronic bundle glue, to make silicon nanowires conductive structures figure; Utilizing inductively coupled plasma (ICP) lithographic technique to produce silicon nanometer electricity on the top layer silicon of SOI substrate leads fine rule 5, silicon quantum wire 14, the first ohmic contact electricity and leads step 3, the second ohmic contact electricity and lead that step 4, the 3rd ohmic contact electricity are led step 15, the 4th ohmic contact electricity leads step 16 and the 5th ohmic contact electricity is led step 17, and then, form the nano wire conductive channel of oxidation insulating layer restriction by thermal oxidation.
Described step B comprises: electron beam adhesive is utilized electron beam lithography to overlap on electron beam adhesive and is carved the coulomb island window area that is used for nanocrystalline coulomb of island 6 of sputtered silicon as the nanocrystalline mask medium of sputtered silicon, makes it to lead fine rule 5 with silicon nanometer electricity and aims at.
Described step C comprises: thin polysilicon layer is sputtered at electron beam adhesive surface and window area thereof, by peeling off (lift-off) technology the thin polysilicon layer film on electron beam adhesive surface is removed, stayed window region and lead the silicon nanocrystal coulomb island 6 that fine rule 5 is aimed at silicon nanometer electricity.
Described step D comprises: cover photoresist, lead on the step at ohm electricity and to go out the metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Ti/Al, after removing photoresist, form the metal-semiconductor first source metal electrode 7, the first drain metal electrode 8, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, at 450 ℃ to 550 ℃ following high annealings, form metal electrode and silicon electricity and lead the ohmic contact of step then.
Described step e comprises: overlay electronic bundle glue, lead on the fine rule 5 at the silicon nanometer electricity that transports stored charge, utilize the electron beam lithography alignment to go out nanometer and enclose the gate electrode window, utilize electron beam evaporation equipment depositing metal Ni, remove electron beam adhesive, formation first is enclosed grid nano-electrode 9, second and is enclosed grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11.
Described step F comprises: utilize plasma-reinforced chemical vapour deposition (PECVD) equipment to lead fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first at silicon nanometer electricity and enclose grid nano-electrode 9, second and enclose that deposit forms dielectric SiO2 layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11.
Described step G comprises: cover photoresist, on insulating medium layer 12, go out floating boom metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Al, remove photoresist after, formation surface metal floating boom 13.
Described step H comprises: cover photoresist, on insulating medium layer 12 with the photoetching alignment go out the first source metal electrode 7, the first drain metal electrode 8, first encloses the lead-in wire window that grid nano-electrode 9, second encloses grid nano-electrode 10, measurements of the chest, waist and hips grid nano-electrode 11, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, go out SiO2 layer contact conductor with buffered hydrofluoric acid HF chemical corrosion and connect window, remove photoresist, connect metal lead wire.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, utilizes the present invention, realize the magnanimity information storage, will have great demand amount and social progress meaning by single electronic memory device and electric charge counting detection system thereof.Single electronic memory device and electric charge counting detection system thereof rely on its low-power, integrated, the ultrafast advantages such as response speed of high density, will be in the important irreplaceable effect of following mass memory field performance.
2, utilize the present invention, the silicon nanocrystal body memory is present a kind of advanced person's a nano thin-film memory technology, this nano level nonvolatile memory will reduce the material cost of massage storage greatly, so single electronic memory device can become the following substitute of present nonvolatile memory.
3, utilize the present invention, Monoelectron memory device has more excellent performance in the low temperature environment in cosmic space, and low temperature can provide better signal background to Coulombian charge, and this is different from and depends on the floating-gate memory that hot electron carries out information stores.Monoelectron memory device on the SOI material is reinforced the charge carrier influence that irradiation produces by reinforcing gate oxide and field oxide.Single-electron memory and electric charge counting detection system thereof have extremely wide application prospect on following spacecraft.
Description of drawings
Fig. 1 is for having the structural representation of the single-electron memory of floating gate structure in the prior art;
Fig. 2 is with the single-electron memory structural representation of granular thin film as tunnel junctions in the prior art;
Fig. 3 is the structural representation of the single-electron memory of accurate One-dimensional Quantum lattice array in the prior art;
Fig. 4 is the silicon nanocrystal coulomb island of charge storage and the cross sectional representation of conductive channel thereof of being used for provided by the invention;
Fig. 5 is the planar structure schematic diagram of the silicon based single electronic memory device of side grid structure provided by the invention;
Fig. 6 has the method flow diagram of side grid structure silicon based single electronic memory device for making provided by the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 4 and Figure 5, Fig. 4 is the silicon nanocrystal coulomb island of charge storage and the cross sectional representation of conductive channel thereof of being used for provided by the invention, and Fig. 5 is the planar structure schematic diagram of the silicon based single electronic memory device of side grid structure provided by the invention.This silicon based single electronic memory device comprises: silicon-on-insulator (SOI) substrate, and this SOI substrate is made of top layer silicon, insulating layer of silicon oxide and silicon substrate from top to bottom; The silicon nanometer electricity of being made by top layer silicon on described SOI substrate is led fine rule 5 and silicon quantum wire 14, described silicon nanometer electricity is led fine rule 5 and is parallel to each other with silicon quantum wire 14, silicon quantum wire 14 is used for surveying the stored charge on silicon nanocrystal coulomb island 6, and stored charge is led fine rule 5 by silicon nanometer electricity and entered silicon nanocrystal coulomb island 6; Being positioned at silicon nanometer electricity leads fine rule 5 centre positions and leads the silicon nanocrystal coulomb island 6 that is used for stored charge that fine rule 5 is connected with silicon nanometer electricity; Be positioned at that silicon nanometer electricity is led fine rule 5 two ends and lead with silicon nanometer electricity that the first ohmic contact electricity that fine rule 5 is connected is led step 3 and the second ohmic contact electricity is led step 4; Being positioned at the first ohmic contact electricity leads the first source metal electrode 7 on the step 3 and is positioned at the second ohmic contact electricity and lead the first drain metal electrode 8 on the step 4; Being positioned at silicon nanocrystal coulomb island 6 both sides silicon nanometer electricity leads first on the fine rule 5 and encloses grid nano-electrode 9, second and enclose grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11, described first encloses grid nano-electrode 9 and second encloses the same side that grid nano-electrode 10 is positioned at silicon nanocrystal coulomb island 6, and described measurements of the chest, waist and hips grid nano-electrode 11 is positioned at the opposite side on silicon nanocrystal coulomb island 6; Be positioned at that silicon quantum wire 14 is led fine rule 5 opposite sides with respect to silicon nanometer electricity and the 3rd ohmic contact electricity that is connected with silicon quantum wire 14 is led step 15 and the 4th ohmic contact electricity is led step 16; Being positioned at the 3rd ohmic contact electricity leads the second source metal electrode 19 on the step 15 and is positioned at the 4th ohmic contact electricity and lead the second drain metal electrode 20 on the step 16; Leading step 15 and the 4th ohmic contact electricity at silicon quantum wire 14 with respect to the 3rd ohmic contact electricity leads step 16 homonymies and leads the 5th ohmic contact electricity that step 15 and the 4th ohmic contact electricity lead between the step 16 at the 3rd ohmic contact electricity and lead step 17; Be positioned at the 5th ohmic contact electricity and lead metal side gate electrode 18 on the step 17; Covering silicon nanometer electricity leads fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first and encloses grid nano-electrode 9, second and enclose insulating medium layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11; Cover the surface metal floating boom 13 on the insulating medium layer 12.
Described silicon nanocrystal coulomb island 6 material therefors are ultra-thin polysilicon film, are used to realize under the room temperature condition that to the strong quantum limitation effect of electric charge, the storing process of each electric charge all depends on quantum coulomb blockade effect.Ultra-thin polysilicon membrane, expection has strong quantum restricting effect.300meV is arrived in the variation of polysilicon membrane thickness, energy changing greatly, and it is more a lot of greatly than heat energy 26meV under the room temperature, and the electronics that therefore is parallel to polysilicon membrane transmits the influence that is subjected to strongly by the current potential at random of this quantum restricting effect generation.If polysilicon membrane is made as the nanostructure of stored charge, the two-dimentional tunnel junctions array that so much crystal silicon nanostructure forms will not influenced by background charge.Background charge comes from the impurity of position near quantum dot, and the electric capacity of the electric charge introduced of other quantum dots.The quantum dot array of graininess film lists increasing of quantum dot quantity, helps to have reduced the series connection total capacitance, has improved the Coulomb interaction energy of electric charge, thereby has overcome the influence of the background charge that is subjected to the interference of environment thermal noise
The potential field of described stored charge acts on signal code by contiguous silicon quantum wire 14 by capacitive coupling, makes silicon quantum wire 14 obtain the stored information of single electric charge.Described silicon quantum wire 14 is used to survey stored charge, and the potential field on stored charge silicon nanocrystal coulomb island 6 acts on signal code by adjacent silicon quantum wire 14 by capacitive coupling, thereby obtains the stored information of single electric charge.By the signal code of silicon quantum wire 14, control by metal side gate electrode 18 and surface metal floating boom 13.Quantum wire conducting current-voltage curve is non-linear quantum modulation, in order to make the electricity conducting, needs the gate threshold voltage of a qualification.For single electric charge write with erase status under, the threshold voltage of the metal side gate electrode 18 of single electronic memory device will have the electricity hysteresis characteristic, reflect the charge storage on nanocrystalline coulomb island 6 and the performance of release.As a result, combine with the charge quantization characteristic, in certain grid voltage scope, system can be stabilized in two or more quantity of electric charge attitudes, thereby single-electron memory realizes that bistable state or multistable work are possible.
The described first ohmic contact electricity is led step 3, the second ohmic contact electricity and is led step 4, the 3rd ohmic contact electricity and lead step 15, the 4th ohmic contact electricity and lead step 16 and the 5th ohmic contact electricity and lead step 17 and be made by the top layer silicon of described SOI substrate.
The described first source metal electrode 7 and the first drain metal electrode 8 are deposited on respectively that the first ohmic contact electricity is led step 3 and the second ohmic contact electricity is led on the step 4, and annealed realization ohmic contact; Described metal side gate electrode 18 is deposited on the 5th ohmic contact electricity and leads on the step 17, and annealed realization ohmic contact; The described second source metal electrode 19 and the second drain metal electrode 20 are deposited on respectively that the 3rd ohmic contact electricity is led step 15 and the 4th ohmic contact electricity is led on the step 16, and annealed realization ohmic contact.
Described first encloses grid nano-electrode 9 and second encloses grid nano-electrode 10 and is used to control single electric charge and enters silicon nanocrystal coulomb island 6, realizes unicharged controlled storage; Described measurements of the chest, waist and hips grid nano-electrode 11 is used for wiping of stored charge on the silicon nanocrystal coulomb island 6.
The storage of electric charge and wipe and only depend on the voltage that discharges and recharges bias voltage and floating boom 13 that is added in 6 two ends, silicon nanocrystal coulomb island.In the quantum dot array array structure, strong coulomb repulsion power makes the electric charge that has transmitted storage hinder the transmission of other electronics, and the coulomb energy quantitative change gets can be comparable with the unsteady energy of environment heat.Writing and read the operation of a little electrons, is exactly that the passing threshold grid voltage changes e/Cg (Cg is the total capacitance of memory node) and overcomes coulomb energy capturing and flow out restriction single electron.Silicon nanocrystal coulomb island 6 forms the two-dimensional array with nanometer tunnel junctions, and the tunnel junctions electric capacity of series connection reduces, and the electric charge coulomb energy will be enhanced, thereby improve working temperature.The storage of many tunnel junctions single electron and release must make the electrical potential difference at junction array two ends change greater than an electric charge coulomb energy gap.When being higher than coulomb energy gap in biasing, middle configurational energy is lower than neighbour's initial state, the order of occurrence tunneling effect.The generation of order tunnelling will suppress tunnelling altogether, promptly be suppressed at coulomb blockade district electronics and rely on coulomb non-resilient tunnelling that the island excited level takes place.Therefore, many tunnel junctions can suppress the leakage current that common tunneling effect produces effectively, thereby can control the storage and the release of a little charge.Electric charge is transferred on the point the isolated point and is absorbed in from current channel, and this is absorbed in the quantum that causes the side gate potential and jumps.By the signal code of silicon quantum wire 14, control by silicon nanocrystal coulomb island 6 two ends bias voltages and/or metal side gate electrode 18 and/or surface metal floating boom 13.
Describedly lead on the fine rule 5, make two adjacent first and enclose grid nano-electrode 9 and second and enclose grid nano-electrode 10, be used to control entering of single electron, realize unicharged controlled storage at the silicon nanometer electricity that is connected with nanocrystalline coulomb island 6.Leading on the opposite side of fine rule 5 with nanocrystalline coulomb island 6 joining silicon nanometer electricity, makes one measurements of the chest, waist and hips grid nano-electrode 11, be used for silicon nanocrystal and store wiping of stored charge on the island.Adjacent first encloses grid nano-electrode 9 and second encloses zone between the grid nano-electrode 10 as the node storage island of single electron, enclose grid nano-electrode 9 and second first and enclose on the grid nano-electrode 10 grid voltage that frequency f in addition changes, the control gate of this rotation (turnstile) produces stair-stepping electric current ef, whenever rotate a circle just as voltage and just to produce the electronics, show the state that transports of single electron.Because the electric capacity on coulomb island is minimum, compole is short during the discharging and recharging of electric capacity, and the switching speed of device is exceedingly fast.The electronics that enters silicon nanocrystal side grid nanochannel like this can be enclosed grid nano-electrode 9, second by first and enclose grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11 Artificial Control effectively, frequency change on revolving door is as the input signal of electronics storage, and the electrorheological of contiguous silicon quantum wire 14 turns into to output signal and is detected.The value that the information stores position of single electronic memory device changes it surpasses the scheduled time, and the deferring procedure that is produced can cause an error.Quantum dot can or be total to tunnelling and spontaneously discharge owing to thermal excitation.Even if correct value is added on the unit, write cycle time also can produce wrong numerical value, or perhaps a read cycle can lose efficacy.The process that nanocrystalline coulomb island 6 storage space information are refreshed can be enclosed grid nano-electrode 9, second by first and be enclosed grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11 revolving doors and carry out electronic counting and detect, and can judge thus to write the error rate that refreshes.
The structural representation of the silicon based single electronic memory device of the side grid structure that provides based on above-mentioned Fig. 4 and Fig. 5, Fig. 6 shows the method flow diagram that making provided by the invention has the side grid structure silicon based single electronic memory device, and this method may further comprise the steps:
Step 601: on the insulating layer of silicon oxide of SOI substrate, produce silicon nanometer electricity and lead fine rule 5, silicon quantum wire 14, the first ohmic contact electricity and lead step 3, the second ohmic contact electricity and lead that step 4, the 3rd ohmic contact electricity are led step 15, the 4th ohmic contact electricity leads step 16 and the 5th ohmic contact electricity is led step 17;
Step 602: utilize the mask medium socket to carve and lead the coulomb island window that fine rule 5 is connected, expose the insulating layer of silicon oxide of SOI substrate with silicon nanometer electricity;
Step 603: sputter thin polysilicon layer, chemical corrosion fall the mask medium, form silicon nanocrystal coulomb island 6 at described coulomb of island window region;
Step 604: deposit forms the first source metal electrode 7, the first drain metal electrode 8, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, and annealing realizes ohmic contact;
Step 605: deposit formation first is enclosed grid nano-electrode 9, second and is enclosed grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11;
Step 606: lead fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first at silicon nanometer electricity and enclose grid nano-electrode 9, second and enclose that deposit forms insulating medium layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11;
Step 607: deposit forms surface metal floating boom 13 on insulating medium layer 12;
Step 608: make the contact conductor window.
Embodiment
Have the method flow diagram of side grid structure silicon based single electronic memory device based on the making shown in Fig. 6, below in conjunction with specific embodiment the present invention is made the method with side grid structure silicon based single electronic memory device and further describe.
The process implementing method of the silicon based single electronic memory device of a kind of side grid structure provided by the invention specifically comprises the steps:
(1) on the SOI silicon thin film, produces the nano wire conductive structures;
According to the domain of Fig. 4 and the described structural design of Fig. 5, utilize photoetching and electron beam lithography on the SOI sheet of overlay electronic bundle glue, to make silicon nanowires conductive structures figure; Utilizing inductively coupled plasma (ICP) lithographic technique to produce silicon nanometer electricity again leads fine rule 5, silicon quantum wire 14, the first ohmic contact electricity and leads step 3, the second ohmic contact electricity and lead that step 4, the 3rd ohmic contact electricity are led step 15, the 4th ohmic contact electricity leads step 16 and the 5th ohmic contact electricity is led step 17.And then, form the nano wire conductive channel of oxidation insulating layer restriction by thermal oxidation.
(2) mask film covering medium;
Get rid of the thick electron beam adhesive polymethyl methacrylate of 150nm (PolyMethyl MethAcrylate, PMMA) the mask medium of growing as silicon nanocrystal.
(3) cover carves silicon nanocrystal coulomb island window;
Electron beam adhesive is as the nanocrystalline mask medium of sputtered silicon, utilize electron beam lithography on electron beam adhesive, to overlap and carve the coulomb island window area that is used for nanocrystalline coulomb of island 6 of sputtered silicon, make it to lead fine rule 5 and aim at, make silicon nanocrystal sputter at the silicon oxide surface of window area with silicon nanometer electricity.
(4) thin polysilicon layer is sputtered at electron beam adhesive surface and window area thereof, thickness is 50nm, and, stay window region and lead the silicon nanocrystal coulomb island 6 that fine rule 5 is aimed at silicon nanometer electricity by peeling off of the thin polysilicon layer film removal of (lift-off) technology with the electron beam adhesive surface
(5) remove the mask medium of covering: utilize acetone to remove PMMA mask and top silicon nanocrystal thin layer thereof.
(6) lead fine rule 5 on the silicon nanocrystal coulomb island 6 of silicon oxide surface with silicon nanometer electricity and link to each other, high annealing for realize silicon nanocrystal and silicon nanowires preferably electricity contact.
(7) make the metal ohmic contact electrode:
Cover photoresist, lead on the step at ohm electricity and to go out the metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Ti/Al, after removing photoresist, form the metal-semiconductor first source metal electrode 7, the first drain metal electrode 8, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20 at 450 ℃ to 550 ℃ following high annealings.
(8) make control and enclose the grid metal electrode:
Overlay electronic bundle glue, lead on the fine rule 5 at the silicon nanometer electricity that transports stored charge, utilize the electron beam lithography alignment to go out nanometer and enclose the gate electrode window, utilize electron beam evaporation equipment depositing metal Ni, remove electron beam adhesive, formation first is enclosed grid nano-electrode 9, second and is enclosed grid nano-electrode 10 and measurements of the chest, waist and hips grid nano-electrode 11.
(9) cover insulating medium layer:
Utilizing plasma-reinforced chemical vapour deposition (PECVD) equipment to lead fine rule 5, silicon nanocrystal coulomb island 6, silicon quantum wire 14, first at silicon nanometer electricity encloses grid nano-electrode 9, second and encloses that deposit forms dielectric SiO2 layer 12 on grid nano-electrode 10 and the measurements of the chest, waist and hips grid nano-electrode 11.
(10) deposit floating boom metal electrode:
Cover photoresist, on insulating medium layer 12, go out floating boom metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Al, remove photoresist after, formation surface metal floating boom 13.
(11) make the contact conductor window:
Cover photoresist, on insulating medium layer 12 with the photoetching alignment go out the first source metal electrode 7, the first drain metal electrode 8, first encloses the lead-in wire window that grid nano-electrode 9, second encloses grid nano-electrode 10, measurements of the chest, waist and hips grid nano-electrode 11, metal side gate electrode 18, the second source metal electrode 19 and the second drain metal electrode 20, go out SiO2 layer contact conductor with buffered hydrofluoric acid HF chemical corrosion and connect window, remove photoresist, connect metal lead wire.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1. the silicon based single electronic memory device with side grid structure is characterized in that, this silicon based single electronic memory device comprises:
Silicon-on-insulator SOI substrate;
The silicon nanometer electricity of being made by top layer silicon on described SOI substrate is led fine rule (5) and silicon quantum wire (14), described silicon nanometer electricity is led fine rule (5) and is parallel to each other with silicon quantum wire (14), silicon quantum wire (14) is used for surveying the stored charge on silicon nanocrystal coulomb island (6), and stored charge is led fine rule (5) by silicon nanometer electricity and entered silicon nanocrystal coulomb island (6);
Being positioned at silicon nanometer electricity leads fine rule (5) centre position and leads the silicon nanocrystal coulomb island (6) that is used for stored charge that fine rule (5) is connected with silicon nanometer electricity;
Be positioned at that silicon nanometer electricity is led fine rule (5) two ends and lead with silicon nanometer electricity that the first ohmic contact electricity that fine rule (5) is connected is led step (3) and the second ohmic contact electricity is led step (4);
Being positioned at the first ohmic contact electricity leads the first source metal electrode (7) on the step (3) and is positioned at the second ohmic contact electricity and lead the first drain metal electrode (8) on the step (4);
Being positioned at both sides, silicon nanocrystal coulomb island (6) silicon nanometer electricity leads first on the fine rule (5) and encloses grid nano-electrode (9), second and enclose grid nano-electrode (10) and measurements of the chest, waist and hips grid nano-electrode (11), described first encloses grid nano-electrode (9) and second encloses the same side that grid nano-electrode (10) is positioned at silicon nanocrystal coulomb island (6), and described measurements of the chest, waist and hips grid nano-electrode (11) is positioned at the opposite side on silicon nanocrystal coulomb island (6);
Be positioned at that silicon quantum wire (14) is led fine rule (5) opposite side with respect to silicon nanometer electricity and the 3rd ohmic contact electricity that is connected with silicon quantum wire (14) is led step (15) and the 4th ohmic contact electricity is led step (16);
Being positioned at the 3rd ohmic contact electricity leads the second source metal electrode (19) on the step (15) and is positioned at the 4th ohmic contact electricity and lead the second drain metal electrode (20) on the step (16);
Being positioned at silicon quantum wire (14) leads step (1 5) and the 4th ohmic contact electricity with respect to the 3rd ohmic contact electricity and leads step (16) homonymy and lead the 5th ohmic contact electricity that step (15) and the 4th ohmic contact electricity lead between the step (16) at the 3rd ohmic contact electricity and lead step (17);
Be positioned at the 5th ohmic contact electricity and lead metal side gate electrode (18) on the step (17);
Covering silicon nanometer electricity leads fine rule (5), silicon nanocrystal coulomb island (6), silicon quantum wire (14), first and encloses grid nano-electrode (9), second and enclose insulating medium layer (12) on grid nano-electrode (10) and the measurements of the chest, waist and hips grid nano-electrode (11);
Cover the surface metal floating boom (13) on the insulating medium layer (12).
2. the silicon based single electronic memory device with side grid structure according to claim 1, it is characterized in that, described silicon nanocrystal coulomb island (6) material therefor is ultra-thin polysilicon film, be used to realize under the room temperature condition that to the strong quantum limitation effect of electric charge, the storing process of each electric charge all depends on quantum coulomb blockade effect.
3. the silicon based single electronic memory device with side grid structure according to claim 1, it is characterized in that, the potential field of described stored charge acts on signal code by contiguous silicon quantum wire (14) by capacitive coupling, makes silicon quantum wire (14) obtain the stored information of single electric charge.
4. the silicon based single electronic memory device with side grid structure according to claim 3 is characterized in that, described signal code is by metal side gate electrode (18) and/or surface metal floating boom (13) control.
5. the silicon based single electronic memory device with side grid structure according to claim 1, it is characterized in that the described first ohmic contact electricity is led step (3), the second ohmic contact electricity and led step (4), the 3rd ohmic contact electricity and lead step (15), the 4th ohmic contact electricity and lead step (16) and the 5th ohmic contact electricity and lead step (17) and be made by the top layer silicon of described SOI substrate.
6. the silicon based single electronic memory device with side grid structure according to claim 1, it is characterized in that, the described first source metal electrode (7) and the first drain metal electrode (8) are deposited on respectively that the first ohmic contact electricity is led step (3) and the second ohmic contact electricity is led on the step (4), and annealed realization ohmic contact;
Described metal side gate electrode (18) is deposited on the 5th ohmic contact electricity and leads on the step (17), and annealed realization ohmic contact;
The described second source metal electrode (19) and the second drain metal electrode (20) are deposited on respectively that the 3rd ohmic contact electricity is led step (15) and the 4th ohmic contact electricity is led on the step (16), and annealed realization ohmic contact.
7. the silicon based single electronic memory device with side grid structure according to claim 1 is characterized in that,
Described first encloses grid nano-electrode (9) and second encloses grid nano-electrode (10) and is used to control single electric charge and enters silicon nanocrystal coulomb island (6), realizes unicharged controlled storage;
Described measurements of the chest, waist and hips grid nano-electrode (11) is used for silicon nanocrystal coulomb island (6) and goes up wiping of stored charge.
8. the manufacture method with side grid structure silicon based single electronic memory device is characterized in that, this method comprises:
A, on the insulating layer of silicon oxide of SOI substrate, produce silicon nanometer electricity and lead fine rule (5), silicon quantum wire (14), the first ohmic contact electricity and lead step (3), the second ohmic contact electricity and lead that step (4), the 3rd ohmic contact electricity are led step (15), the 4th ohmic contact electricity leads step (16) and the 5th ohmic contact electricity is led step (17);
B, utilize the mask medium socket to carve to lead the coulomb island window that fine rule (5) is connected, expose the insulating layer of silicon oxide of SOI substrate with silicon nanometer electricity;
C, sputter thin polysilicon layer, the mask medium is fallen in chemical corrosion, forms silicon nanocrystal coulomb island (6) at described coulomb of island window region;
D, deposit form the first source metal electrode (7), the first drain metal electrode (8), metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode (20), and annealing realizes ohmic contact;
E, deposit formation first are enclosed grid nano-electrode (9), second and are enclosed grid nano-electrode (10) and measurements of the chest, waist and hips grid nano-electrode (11);
F, lead fine rule (5), silicon nanocrystal coulomb island (6), silicon quantum wire (14), first at silicon nanometer electricity and enclose grid nano-electrode (9), second and enclose grid nano-electrode (10) and measurements of the chest, waist and hips grid nano-electrode (11) and go up deposit and form insulating medium layer (12);
G, go up deposit at insulating medium layer (12) and form surface metal floating boom (13);
H, making contact conductor window.
9. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described steps A comprises:
Design layout utilizes photoetching and electron beam lithography to make silicon nanowires conductive structures figure on the SOI substrate of overlay electronic bundle glue;
Utilizing inductively coupled plasma ICP lithographic technique to produce silicon nanometer electricity on the top layer silicon of SOI substrate leads fine rule (5), silicon quantum wire (14), the first ohmic contact electricity and leads step (3), the second ohmic contact electricity and lead that step (4), the 3rd ohmic contact electricity are led step (15), the 4th ohmic contact electricity leads step (16) and the 5th ohmic contact electricity is led step (17), and then, form the nano wire conductive channel of oxidation insulating layer restriction by thermal oxidation.
10. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step B comprises:
Electron beam adhesive is utilized electron beam lithography to overlap on electron beam adhesive and is carved the coulomb island window area that is used for nanocrystalline coulomb of island of sputtered silicon (6) as the nanocrystalline mask medium of sputtered silicon, makes it to lead fine rule (5) with silicon nanometer electricity and aims at.
11. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step C comprises:
Thin polysilicon layer is sputtered at electron beam adhesive surface and window area thereof, the thin polysilicon layer film on electron beam adhesive surface is removed, stay window region and lead the silicon nanocrystal coulomb island (6) that fine rule (5) is aimed at silicon nanometer electricity by peeling off lift-off technology.
12. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step D comprises:
Cover photoresist, lead on the step at ohm electricity and to go out the metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Ti/Al, after removing photoresist, form the metal-semiconductor first source metal electrode (7), the first drain metal electrode (8), metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode (20), at 450C ° to 550C ° following high annealing, form metal electrode and silicon electricity and lead the ohmic contact of step then.
13. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step e comprises:
Overlay electronic bundle glue, lead on the fine rule (5) at the silicon nanometer electricity that transports stored charge, utilize the electron beam lithography alignment to go out nanometer and enclose the gate electrode window, utilize electron beam evaporation equipment depositing metal Ni, remove electron beam adhesive, formation first is enclosed grid nano-electrode (9), second and is enclosed grid nano-electrode (10) and measurements of the chest, waist and hips grid nano-electrode (11).
14. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step F comprises:
Utilizing plasma-reinforced chemical vapour deposition PECVD equipment to lead fine rule (5), silicon nanocrystal coulomb island (6), silicon quantum wire (14), first at silicon nanometer electricity encloses grid nano-electrode (9), second and encloses grid nano-electrode (10) and measurements of the chest, waist and hips grid nano-electrode (11) and go up deposit and form dielectric SiO2 layer (12).
15. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step G comprises:
Cover photoresist, go up at insulating medium layer (12) and go out floating boom metal electrode window with the photoetching alignment, deposited by electron beam evaporation depositing metal Al, remove photoresist after, formation surface metal floating boom (13).
16. the manufacture method with side grid structure silicon based single electronic memory device according to claim 8 is characterized in that, described step H comprises:
Cover photoresist, insulating medium layer (12) go up with the photoetching alignment go out the first source metal electrode (7), the first drain metal electrode (8), first encloses the lead-in wire window that grid nano-electrode (9), second encloses grid nano-electrode (10), measurements of the chest, waist and hips grid nano-electrode (11), metal side gate electrode (18), the second source metal electrode (19) and the second drain metal electrode (20), go out SiO2 layer contact conductor with buffered hydrofluoric acid HF chemical corrosion and connect window, remove photoresist, connect metal lead wire.
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| JP4873335B2 (en) * | 2000-04-28 | 2012-02-08 | 独立行政法人科学技術振興機構 | Information processing structure |
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| CN102142376A (en) * | 2010-12-31 | 2011-08-03 | 上海集成电路研发中心有限公司 | Preparation method of silicon nanowire fence device |
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| CN106383163A (en) * | 2016-10-19 | 2017-02-08 | 中国人民解放军国防科学技术大学 | Ionizing gas sensor based on single electron transistor and preparation method thereof |
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