CN1466214A - Carbon nano tube type integrated EFI and preparation process thereof - Google Patents
Carbon nano tube type integrated EFI and preparation process thereof Download PDFInfo
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- CN1466214A CN1466214A CNA02123860XA CN02123860A CN1466214A CN 1466214 A CN1466214 A CN 1466214A CN A02123860X A CNA02123860X A CN A02123860XA CN 02123860 A CN02123860 A CN 02123860A CN 1466214 A CN1466214 A CN 1466214A
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Abstract
This invention relates to a preparing technology realizing fieldistor integration by carbon nm transistors which is to make interphases grating and electrodes on an insulation layer with a super long carbon nm transistor on it, a certain value of constant voltage is given to some gratings to stop part of the support long nm transistor which is equivalent to several carbon nm transistor fieldistors realizing the integration. The preparation technology is to put a carbon nm transistor on the grid and electrodes of an insulation layer to finished an integrated fieldistor.
Description
Technical field
The present invention relates to a kind of integrated and its preparation technology who utilizes an overlength carbon nano pipe to realize the high density integrated EFI.
Background technology
Semiconductor integrated circuit is one of invention that 20th century mankind was had significant impact.Exactly because the appearance of integrated circuit has just been brought the mankind " information age " into.Enter 21 century, passed through the development of decades, it is perfect that the technology of semiconductor integrated circuit and technology have been tending towards.Its manufacture craft is also very ripe as: technology such as photoetching, mask, doping.Use these technology, integrated circuit is integrated into switching devices such as thousands of transistor on the chip exactly to realize the complex calculations function.At present, use the switching device of conventional silicon substrate production to be constructed such that basically impurity diffusion zone, isolated area and channel region level are connected.The integrated circuit of being made up of a plurality of switching devices is constructed such that also each switching device is horizontal, and is integrated with high density.Under existing technical conditions, the limit of photoetching is 10nm.Metal oxide semiconductor field effect tube (MOSFET) is a kind of meticulous switching device of the most typical use, that is to say to use this kind technology, a forty-two million metal-oxide-semiconductor field effect t can be integrated in area and be on 1 square centimeter the chip.
But along with the technology of semiconductor integrated circuit constantly develops, people are also improving constantly the requirement of aspects such as the integration density of circuit and speed.And under existing technical conditions, all deficiencies of traditional semiconductor integrated circuit also just slowly come out.For example: be subjected to machining medium---the restriction of light wavelength, machining accuracy can't further improve; Be subjected to the restriction of semiconductor operation principle, the arithmetic speed of semiconductor circuit is difficult to increase again; Along with reducing of device size, the performance of its reliability and device all decreases or the like.People are in order to overcome the problem that exists in the miniaturization ordinary tap device, and the carbon nano-tube switching device is attracting people's sight with its distinctive advantage.
1998 " Applied Physics wall bulletin " (APPLIED PHYSICS LETTERS) reported people such as R.Martel (" Applied Physics wall bulletin " Appl.Phy.Letters in IBM research center, 2001, Vol73, No.17,2447) field effect transistor produced with carbon nano-tube.This carbon nanotube field-effect pipe at room temperature has good electrical properties, and its every performance index can compare favourably with traditional semiconductor field fully.Field effect transistor is the base components of integrated circuit, therefore we can say that the appearance of carbon nanotube field-effect pipe is the first step of nanometer logical circuit of marching toward.We can see the key issue in the making of carbon nano tube device is how carbon nano-tube accurately to be in place from the manufacturing process of the carbon nanometer transistor of people such as R.Martel making.At present, people generally be use " atomic force microscope " (AFM) or " scanning tunnel microscope " (STM) technology control short single-root carbon nano-tube that is only applicable to single device, it is in place.The shortcoming of this technology is that efficient is low, effect is relatively poor.At present, this technology can only be used for making single device, and when making the device of being made up of a plurality of carbon nanotube field-effect pipes, this method is just powerless, says nothing of and has been applied to the making of large scale integrated circuit.
The content of invention
The objective of the invention is to provide a kind of integrated EFI that on the basis of single-root carbon nano-tube, can realize fairly large integrated level in order to address the above problem.
The present invention also aims to provide a kind of technology of utilizing single overlength carbon nano pipe to prepare carbon nano tube type integrated EFI.
Purpose of the present invention can realize by following measure:
A kind of carbon nano tube type integrated EFI comprises substrate and insulating barrier, establishes insulating barrier on substrate; On insulating barrier, be provided with grid and electrode alternately, one overlength carbon nano pipe contacts with electrode with grid, on the grid of the contiguous both sides of a grid, link to each other with a constant voltage, the grid-controlled carbon nano-tube of this logical constant voltage is ended, form integrated independent field effect transistor two grid and two electrodes and carbon nano-tube between the grid.
Described grid and distance between electrodes are 5nm to 100 μ m; The width of grid and electrode is 10nm to 50 μ m.
Described gate surface is an insulating barrier, and its thickness is 1nm to 5nm.
The thickness of insulating barrier is 35nm to 100 μ m on the described substrate.
Described carbon nano-tube is a Single Walled Carbon Nanotube.
Purpose of the present invention also can realize by following measure:
A kind of carbon nano tube type integrated EFI comprises substrate and insulating barrier, on substrate, establish insulating barrier, its preparation technology comprises the steps: that (i) at first prepares grid, adopting photoetching process to make the photoresist on the insulating barrier form indentation on the insulating barrier, and the some grooves of employing dry etching method etching on insulating barrier, deposition one conductive layer in groove, and on conductive layer, form insulating barrier, thus form grid; (ii) repeat above-mentioned lithographic method, deposition one conductive noble metal layer forms some electrodes of alternately arranging with grid on insulating barrier; (iii) be placed on the insulated substrate layer the Single Walled Carbon Nanotube of an overlength is straight, and contact with electrode with grid; (iv) a logical constant voltage on two grids of the adjacent both sides of a grid is ended the grid-controlled carbon nano-tube of this logical constant voltage, forms integrated field effect transistor by remaining grid and electrode and carbon nano-tube.
Described grid and electrode are positioned at the groove of insulating barrier, and the surface of grid and electrode and surface of insulating layer maintain an equal level; The thickness of described insulating barrier is 35nm to 100 μ m; The degree of depth of insulating barrier groove is 10nm to 95 μ m.
Described grid and distance between electrodes are 5nm to 100 μ m; The width of grid and electrode is 10nm to 50 μ m.
Purpose of the present invention can realize by following measure again:
A kind of preparation technology of carbon nano tube type integrated EFI comprises the steps: that (i) at first prepares grid, on substrate, establish insulating barrier, adopting photoetching process to make the photoresist on the insulating barrier form indentation on the insulating barrier, and employing dry etching method etching groove on insulating barrier, depositing conducting layer in groove, and on conductive layer, form insulating barrier, thereby form grid; (ii) the Single Walled Carbon Nanotube with an overlength is placed on the insulated substrate layer, and contacts with grid; (iii), form the electrode of alternately arranging with grid at the some electrodes of deposition on insulated substrate layer between the grid and carbon nano-tube; (iv) a logical constant voltage on two grids of the adjacent both sides of a grid is ended the grid-controlled carbon nano-tube of this logical constant voltage, forms integrated field effect transistor by remaining grid and electrode and carbon nano-tube.
Described grid is positioned at the groove of insulating barrier, and electrode is positioned on insulating barrier and the Single Walled Carbon Nanotube; The thickness of described insulating barrier is 35nm to 100 μ m; The degree of depth of insulating barrier groove is 10nm to 95 μ m.
Described grid and distance between electrodes are 5nm to 100 μ m; The width of grid and electrode is 10nm to 50 μ m.
Establish electrode on insulated substrate layer and the carbon nano-tube, the height of electrode is 5nm to 200 μ m
The present invention has following advantage compared to existing technology:
The present invention utilizes an overlength carbon nano pipe to be placed on the grid and electrode of substrate, and with the logical constant voltage of its adjacent part grid make by the carbon nano-tube of its control by and form the field effect transistor of several independent, realized the integrated of field effect transistor; Integrated EFI of the present invention simple in structure, and be easy to make and integrated.
Description of drawings
Fig. 1 is a structure chart of the present invention
1-carbon nano-tube 2-grid 3-electrode 4-insulating barrier
The 5-substrate
Fig. 2 is an A-A cutaway view of the present invention;
Fig. 3 is a circuit diagram of the present invention;
The 6-constant pressure source
Fig. 4 is an equivalent circuit diagram of the present invention;
Fig. 5 is an embodiment of the invention structure chart.
Embodiment
Embodiment 1:
The silicon of choosing (001) orientation is as substrate 5.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on substrate 5
2Layer 4.At first make grid 2: at SiO
2Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier.Photoresist behind the electron beam exposure through development, photographic fixing, remove the photoresist of exposure after, on photoresist layer, form some wide 30nm, at a distance of the groove of 130nm.The SiO that uses dry etching method etching not have photoresist to cover
2, at SiO
2Form wide 30nm on the insulating barrier, the groove of dark 30nm.Utilize the method for electron beam evaporation, at the thick Al of entire device surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating
2O
3Insulating barrier.So just finished the preparation of grid 2.Prepare electrode 3 then: repeat above lithography step, evenly smear the photoresist that a layer thickness is 80nm on the entire device surface.Behind the resist exposure, form on the photoresist layer some positions between grid,, width parallel with grid apart from grid 50nm, direction be the groove of 30nm.Use dry etching, do not having the SiO of photoresist
2Etch the groove of wide 30nm, dark 30nm on the insulating barrier.Utilizing the method for electron beam evaporation again, is the gold of 30nm at whole surface deposition one layer thickness.Both finished the preparation of electrode 3 after then electric lithography glue being peeled off, cleaned.Selecting a diameter is that 1nm, carrier concentration are 9 * 10
6Cm
-1Overlength Single Walled Carbon Nanotube 1, its length should satisfy the device needs, is placed on the entire device with atomic force microscope.It is straight to require carbon nano-tube to place, and direction is basic vertical with the grid direction with electrode, and will contact well with grid with electrode.After device encapsulated, connect grid 2, electrode 3 and constant pressure source 6 on demand.
Embodiment 2:
The silicon of choosing (001) orientation is as substrate 5.Utilize organic vapor phase deposition method (PECVD), the thick SiO of preparation 300nm on substrate 5
2Layer 4.At first make grid 2: at SiO
2Even smearing thickness is the thick electric lithography glue (PMMA) of 80nm on the insulating barrier.Photoresist behind the electron beam exposure through development, photographic fixing, remove the photoresist of exposure after, on photoresist layer, form some wide 30nm, at a distance of the groove of 200nm.The SiO that uses dry etching method etching not have photoresist to cover
2, at SiO
2Form wide 30nm on the insulating barrier, the groove of dark 30nm.Utilize the method for electron beam evaporation, at the thick Al of entire device surface deposition one deck 30nm.With photoresist lift off, cleaning,, make the Al surface form the thick Al of 2-3nm again through peroxidating
2O
3Insulating barrier.Selecting a diameter is that 1nm, carrier concentration are 9 * 10
6Cm
-1Overlength Single Walled Carbon Nanotube 1, its length should be satisfied the demand, and is placed on the entire device with atomic force microscope.It is straight to require carbon nano-tube to place, and direction is basic vertical with the grid direction, and will contact well with grid.After carbon nano-tube is in place,, on carbon nano-tube, prepares three width with focused ion beam (FIB) method and be 0.1 μ m, highly be the platinum of 200nm (Pt) electrode 3 respectively in the centre of two grids and the position of outside 50nm.After device encapsulated, connect grid 2, electrode 3 and constant pressure source 6 on demand.
Electrical properties and schematic diagram of the present invention 4 below in conjunction with carbon nano-tube illustrate operation principle of the present invention.
The overlength Single Walled Carbon Nanotube that the present invention selects for use electric conductivity to be.The character of this Single Walled Carbon Nanotube is: conductivity is preferably arranged at normal temperatures, and its resistance is generally a hundreds of k Ω.Its charge carrier is the hole by testing as can be known, and conduction type is the P type.Its electric conductivity changes with the change of grid voltage.Under the effect of forward grid bias, the concentration in charge carrier---hole will reduce.When grid voltage increases to certain value, carbon nano-tube will be in cut-off state.At thickness of insulating layer is under the situation of 140nm, and grid voltage is about 6V, and the hole in the carbon nano-tube will be exhausted fully, and carbon nano-tube is in cut-off state.Simultaneously, we are as can be known: at this moment, if keep the cut-off state of carbon nano-tube, added bias voltage should be not more than 1.5V at the carbon nano-tube two ends.(" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, Vol 73, NO.17,2447.) so we are defined in the circuit of the present invention, and 1.2V is logical value " 1 ", 0V is logical value " 0 ".
By above discussion we as can be known: when the gate insulator layer thickness was 140nm, the voltage that exhausts of grid was 6V.We determine by following calculating, during the exhausting voltage and be 1.2V of grid, and the thickness of gate insulator.
Known, there is following relationship in the voltage that blocks between carbon nano-tube and the grid:
Q=CV
G, T(1) V
G, TFor blocking voltage, Q is electrically charged by charge carrier, and C is the electric capacity between carbon nano-tube and the grid.
Q and carrier concentration satisfy formula:
Q=peL (2) p is a carrier concentration; E is electrically charged by charge carrier, and charge carrier is the hole in p type carbon nano-tube, so e=+1.6 * 10 here
-19Coulomb; L is the length of carbon nano-tube and grid contact portion.
Know that again the electric capacity between carbon nano-tube and the grid satisfies formula:
C ≈ 2 π ε ε
0L/ln (2h/r) (3) h is the distance between carbon nano-tube and the grid, the i.e. thickness of gate insulator; R is the carbon nano-tube radius; ε is a dielectric constant, and here we get ε=2.5.
Formula (2), (3) are brought in the formula (1) and can be got:
peln(2h/r)＝2πεε
0V
G，T
It is 9 * 10 that the present invention selects carrier concentration
6Cm
-1P type overlength Single Walled Carbon Nanotube (" Applied Physics wall bulletin " Appl.Phy.Letters, 2001, vol 73, NO.17,2447.).Diameter of single-wall carbon nano tube is 1nm, and cut-ff voltage is 1.2V.Bringing formula (4) into can get: h ≈ 3nm.That is: in the present invention, work as Al
2O
3Thickness of insulating layer is not more than under the situation of 3nm, and Single Walled Carbon Nanotube is in cut-off state.
This conclusion is very important in the present invention.Logical constant voltage 1.2V partly ends overlength carbon nano pipe on the grid of needs, is the field effect transistor that some carbon nano-tube form with equivalence.As shown in Figure 3, as required some grids are connected the 1.2V constant pressure source.Under the effect of 1.2V grid voltage, the part carbon nano-tube is cut off.So just can work alone in the part that is not cut off by grid 2 between two grids 2 and two electrodes 3 and carbon nano-tube 1, its structure and independently the carbon nanotube field-effect pipe is in full accord.So just formed the field effect transistor of several independent.Its effect is equivalent to the integrated of field effect transistor that some short carbon nanometer tubes make.Principle as shown in Figure 4.As required grid just is connected with electrode again and can forms circuit, the function that realization is complicated.Like this, on an overlength carbon nano pipe, form several field effect transistor, realized the integrated of field effect transistor.The concrete length of the quantity of grid and electrode and carbon nano-tube can be determined as required.
Claims (11)
1, a kind of carbon nano tube type integrated EFI comprises substrate (5) and insulating barrier (4), establishes insulating barrier (4) on substrate (5); It is characterized in that on insulating barrier (4) grid (2) and electrode (3) alternately, one overlength carbon nano pipe (1) contacts with electrode (3) with grid (2), upward link to each other at the contiguous both sides of a grid (2) grids (2) with a constant voltage, the carbon nano-tube of grid (2) control of this logical constant voltage is ended, two grid (2) and two electrodes (3) and integrated independent field effect transistor of carbon nano-tube (1) formation of ending between the grid.
2, carbon nano tube type integrated EFI as claimed in claim 1 is characterized in that the distance between described grid (2) and the electrode (3) is 5nm to 100 μ m; The width of grid (2) and electrode (3) is 10nm to 50 μ m.
3, carbon nano tube type integrated EFI as claimed in claim 1 is characterized in that described grid (2) surface is insulating barrier, and its thickness is 1nm to 5nm.
4, carbon nano tube type integrated EFI as claimed in claim 1, the thickness that it is characterized in that the insulating barrier (4) on the described substrate is 35nm to 100 μ m.
5, a kind of preparation technology of carbon nano tube type integrated EFI, it is characterized in that comprising the steps: that (i) at first prepares grid (2), on substrate, establish insulating barrier (4), going up the employing photoetching process at insulating barrier (4) makes the photoresist on the insulating barrier (4) form indentation, and adopt the dry etching method to go up etching groove at insulating barrier (4), deposition one conductive layer in groove, and on conductive layer, form insulating barrier, thus form grid (2); (ii) repeat above-mentioned lithographic method, go up deposition one conductive layer at insulating barrier (4) and form and grid (2) electrode (3) alternately; (iii) the Single Walled Carbon Nanotube (1) with an overlength is placed on the insulated substrate layer (4), and contacts with electrode (3) with grid (2); (iv) go up a logical constant voltage, the carbon nano-tube (1) of grid (2) control of this logical constant voltage is ended, form integrated field effect transistor by remaining grid (2) and electrode (3) and carbon nano-tube (1) at the contiguous both sides of a grid (2) grids (2).
6, carbon nano tube type integrated EFI as claimed in claim 5 preparation technology, it is characterized in that: grid (2) and electrode (3) are positioned at the groove of insulating barrier (4), and the surface of grid (2) and electrode (3) and insulating barrier (4) surface maintains an equal level; The thickness of described insulating barrier (4) is 35nm to 100 μ m; The degree of depth of insulating barrier (4) groove is 10nm to 95 μ m.
7, the preparation technology of carbon nano tube type integrated EFI as claimed in claim 5 is characterized in that the distance between described grid (2) and the electrode (3) is 5nm to 100 μ m; The width of grid (2) and electrode (3) is 10nm to 50 μ m.
8, a kind of preparation technology of carbon nano tube type integrated EFI, it is characterized in that comprising the steps: that (i) at first prepares grid (2), on substrate, establish insulating barrier (4), go up the employing photoetching process at insulating barrier (4) and go up the formation indentation at insulating barrier (4), and adopt the dry etching method to go up etching groove at insulating barrier (4), deposition one conductive layer in groove, and on conductive layer, form insulating barrier, thus form grid (2); (ii) the Single Walled Carbon Nanotube (1) with an overlength is placed on the insulated substrate layer (4), and contacts with grid (2); (iii) on carbon nano-tube (1), with preparation of focused ion beam method and grid (2) electrode (3) alternately; (iv) go up a logical constant voltage, the carbon nano-tube (1) of grid (2) control of this logical constant voltage is ended, form integrated field effect transistor by remaining grid (2) and electrode (3) and carbon nano-tube (1) at the contiguous both sides of a grid (2) grids (2).
9, the preparation technology of carbon nano tube type integrated EFI as claimed in claim 8 is characterized in that: grid (2) is positioned at the groove of insulating barrier (4), and electrode (3) is positioned on insulating barrier (4) and the Single Walled Carbon Nanotube (1); The thickness of described insulating barrier (4) is 35nm to 100 μ m; The degree of depth of insulating barrier (4) groove is 10nm to 95 μ m.
10, the preparation technology of carbon nano tube type integrated EFI as claimed in claim 9 is characterized in that the distance between described grid (2) and the electrode (3) is 5nm to 100 μ m; The width of grid (2) and electrode (3) is 10nm to 50 μ m.
11, the preparation technology of carbon nano tube type integrated EFI as claimed in claim 8 or 9 is characterized in that establishing electrode (3) on insulated substrate layer (4) and the carbon nano-tube (1), and the height of electrode (3) is 5nm to 200 μ m.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02123860 CN1236492C (en) | 2002-07-05 | 2002-07-05 | Carbon nano tube type integrated EFI and preparation process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02123860 CN1236492C (en) | 2002-07-05 | 2002-07-05 | Carbon nano tube type integrated EFI and preparation process thereof |
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| Publication Number | Publication Date |
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| CN1466214A true CN1466214A (en) | 2004-01-07 |
| CN1236492C CN1236492C (en) | 2006-01-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02123860 Expired - Fee Related CN1236492C (en) | 2002-07-05 | 2002-07-05 | Carbon nano tube type integrated EFI and preparation process thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100472755C (en) * | 2006-09-19 | 2009-03-25 | 北京大学 | Integration method for single-wall carbon nano tube part |
| CN104867817A (en) * | 2015-05-21 | 2015-08-26 | 北京工业大学 | Semiconductor process for film planarization |
| US9947743B2 (en) | 2016-06-16 | 2018-04-17 | International Business Machines Corporation | Structures and methods for long-channel devices in nanosheet technology |
-
2002
- 2002-07-05 CN CN 02123860 patent/CN1236492C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100472755C (en) * | 2006-09-19 | 2009-03-25 | 北京大学 | Integration method for single-wall carbon nano tube part |
| CN104867817A (en) * | 2015-05-21 | 2015-08-26 | 北京工业大学 | Semiconductor process for film planarization |
| US9947743B2 (en) | 2016-06-16 | 2018-04-17 | International Business Machines Corporation | Structures and methods for long-channel devices in nanosheet technology |
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| Publication number | Publication date |
|---|---|
| CN1236492C (en) | 2006-01-11 |
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Granted publication date: 20060111 Termination date: 20120705 |