CN104867817A - Semiconductor process for film planarization - Google Patents

Semiconductor process for film planarization Download PDF

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Publication number
CN104867817A
CN104867817A CN201510262462.5A CN201510262462A CN104867817A CN 104867817 A CN104867817 A CN 104867817A CN 201510262462 A CN201510262462 A CN 201510262462A CN 104867817 A CN104867817 A CN 104867817A
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graphene
photoresist
metal
photoetching
etching
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徐晨
刘奇
孙捷
许坤
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Beijing University of Technology
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Beijing University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/203—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using physical deposition, e.g. vacuum deposition, sputtering
    • H01L21/2033—Epitaxial deposition of elements of Group IV of the Periodic System, e.g. Si, Ge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor process for film planarization is disclosed. In a conventional process of producing semiconductors with graphene films, the films are usually damaged severely. The semiconductor process combines lithography and sputtering technologies and employ inductively coupled plasma (ICP) to ensure the complete contact between the graphene films and metallic structured. The semiconductor process improves the adhesiveness of metal and a substrate, may not damage a graphene film structure and substantially improves the reliability and stability of a semiconductor device.

Description

A kind of semiconductor technology of thin film planar
Technical field
The invention belongs to the preparation field of semiconductor device, be specifically related to a kind of semiconductor technology of thin film planar.
Background technology
The processing technology of semiconductor device is mainly divided into planar technique and body technology, body technology requires that the size of device is enough large, and be unfavorable for accurate controlled working size, especially when relating to thin film technique, due to the step that the differing heights on device is formed, there is part film unsettled below the section that film can be made to follow step to contact, very easily cause fracture or the breakage of film, had a strong impact on the Structure and stability of device.
Graphene is a kind of new carbon with zero band gap, high mobility, low-resistivity and high light transmittance, and thickness only has 0.34nm.Utilize its band structure and relevant nature, the device of a lot of semiconductor applications can be made, and in the structure of device, in order to ensure that graphene film contacts with the complete of device, namely ensure that Graphene can not be excessive and rupture due to the difference in height of device architecture, need that difference in height is dropped to minimum.If but the deposit thickness of thinning material, the stability of follow-up techniques can be made again to be affected, and the thickness such as reducing insulating barrier can cause leaky, and the thickness reducing metal can make metal and substrate poor adhesion.
The manufacture method of traditional graphene semiconductor device first shifts Graphene in target substrate, then carries out electron beam lithography and hydatogenesis metal to the substrate with Graphene.Although the metal deposition rate that evaporation is formed is high, but can not deposit metal alloy, the atom be simultaneously evaporated or the amount of molecule are comparatively large and speed is unstable, and these all can cause the tack of metal and substrate to be deteriorated, and whole process easily produces damage to the membrane structure of Graphene.Therefore first metal structure can be made by the method for sputtering, again Graphene is transferred on the substrate with metal structure, if but now the metal of sputtering is blocked up, great disparity is excessive compared with the film thickness of Graphene, Graphene can be caused cannot completely to contact with metal, even rupture at engagement edge.
Summary of the invention
Difference in height on device architecture can cause breakage or the fracture of graphene film, but the thickness reducing deposition materials simply can bring many adverse effects to subsequent technique again; First shift Graphene, then make structure, although deposition rate is high by the method for evaporated metal, but can not deposit metal alloy, and evaporation rate is unstable, the tack of metal and substrate can be caused to be deteriorated, the whole process also easy membrane structure to Graphene produces damage; If change alternatively, i.e. first splash-proofing sputtering metal structure, transferred to by Graphene on the substrate with metal structure again, this method also needs to ensure that metal and the film thickness difference of Graphene can not differ too large, otherwise Graphene still can be caused cannot completely to contact with metal.
In view of above Problems existing, the invention provides a kind of method of planarization films technique, photoetching is combined with sputtering technology, and utilize sense coupling (Inductively Coupled Plasma, ICP) technology, ensures that graphene film contacts with the complete of metal structure.Improve metal and substrate adhering while, do not damage again the membrane structure of Graphene, greatly improve the reliability of semiconductor device.
Concrete technology step is as follows:
After silicon chip with insulating medium layer is cleaned by S1, prepare photoetching, now insulating medium layer (2) is on silicon substrate (1), as shown in Fig. 1-1,1-2;
S2 photoetching, photoresist (3), on insulating medium layer (2), produces the figure as Fig. 1-3 structure;
S3 with photoresist (3) makes mask, and ICP etches, etched recesses, and the structure after etching as Figure 1-4;
S4 chooses etching parameters, removes photoresist after etching completes, and measures the degree of depth of institute's etched recesses with step instrument;
S5 splash-proofing sputtering metal, the thickness of sputtering is the corresponding degree of depth that previous step is measured, then the metal material now sputtered (4) can just fill and lead up the groove that step 3 etches, as Figure 1-5;
S6 organic solution peels off unnecessary metal, material is thus formed the planar structure shown in Fig. 1-5.
When the film related to is graphene film, the silicon dioxide that insulating medium layer (2) is 300nm thickness.
The photoresist (3) used is negative glue, is not the part needing to etch groove by photoresist (3) covering place.
Described lithographic method is dry etching.
Organic solution used need guarantee the photoresist (3) dissolved in preceding step.
After above-mentioned cutting, filling step, metal thickness and the substrate of sputtering remain on same level height substantially, need the film carrying out multiple processing step when contacting with step after so just can making, can not be excessive due to both differences in height, and the problem causing film to fracture produces.Key of the present invention is exactly ensure that the depth of groove of institute's etachable material is identical with the metal thickness sputtered subsequently.
Accompanying drawing explanation
Fig. 1-1 is the silicon substrate with insulating barrier;
Fig. 1-2 is whirl coating, prepares litho pattern;
Fig. 1-3 is for making the figure wanted by lithography;
Fig. 1-4 is for make mask with photoresist, and ICP etches;
Fig. 1-5 is splash-proofing sputtering metal, the consistency of thickness that thickness should etch with ICP;
Fig. 1-6 is peel-away removal redundance metal;
Fig. 2-1 is the silicon substrate with silicon dioxide;
Fig. 2-2 is whirl coating, prepares litho pattern;
Fig. 2-3 is for making gate electrode figure by lithography;
Fig. 2-4 is for make mask with photoresist, and ICP etches grid recess;
Fig. 2-5 sputters the metal alloy Ti/Au thickness identical with previous step etching depth, as gate electrode;
Fig. 2-6 is after the unnecessary metallic member of peel-away removal, only leaves the gate electrode figure of needs;
Fig. 2-7 is growth 300nm silicon dioxide;
Fig. 2-8 is whirl coating preparation photolithographic source, drain electrode;
Fig. 2-9 for photoetching complete after source, drain electrode patterns;
Fig. 2-10 is for make mask with photoresist, and ICP etches the groove of grid source, drain electrode;
Fig. 2-11 sputters the metal alloy Ti/Au thickness identical with previous step etching depth, as source, drain electrode;
Fig. 2-12 has defined required source, drain electrode structure after having peeled off;
Fig. 2-13 is transfer graphene film;
Fig. 2-14 for photoetching complete after only leave the Graphene figure of needs;
Fig. 3-1 is the silicon chip with 300nm silicon dioxide;
Fig. 3-2 prepares photoetching for after whirl coating;
The gate electrode figure of Fig. 3-3 for making by lithography;
Fig. 3-4 for make mask with photoresist, the gate electrode groove that ICP etches out;
Fig. 3-5 is that the thickness of the sputtering metal alloy Ti/Au identical with previous step etching depth is as gate electrode;
Fig. 3-6 is after the unnecessary metallic member of peel-away removal, only leaves the gate electrode figure of needs;
Fig. 3-7 is the silicon dioxide of growth 30nm;
Fig. 3-8 is whirl coating, prepares photolithographic source, drain electrode patterns;
The source that Fig. 3-9 produces for photoetching, drain electrode patterns;
Fig. 3-10 for make mask with photoresist, the source that ICP etches out, the groove of drain electrode;
Fig. 3-11 is the thickness sputtering the metal alloy Ti/Au identical with previous step etching depth, as source, drain electrode;
Fig. 3-12, for after stripping completes, only leaves the source of needs, drain electrode structure;
Fig. 3-13 is transfer Graphene;
Fig. 3-14, for after photoetching completes, only leaves required Graphene figure;
Fig. 4-1 is the silicon chip with 300nm silicon dioxide;
Fig. 4-2 prepares photoetching for after whirl coating;
Fig. 4-3 is for making electrode pattern by lithography;
Fig. 4-4 is for make mask with photoresist, and ICP etches the groove of electrode;
Fig. 4-5 is the thickness sputtering the metal alloy Ti/Au identical with previous step etching depth;
Fig. 4-6, for after completing, leaves the electrode structure of needs;
Fig. 4-7 is transfer Graphene;
The Graphene graphic structure that Fig. 4-8 is required for photoetching stays;
In figure: 1, silicon substrate, 2, insulating medium layer, 3, photoresist, 4, the metal material of sputtering, 5, Graphene.
Embodiment
Enforcement of the present invention is described by following three embodiments.
Embodiment 1: be applied in the photodetector of Graphene
After silicon chip with insulating medium layer is cleaned by S1, photoetching forms the figure of gate electrode, as shown in Fig. 2-1,2-2,2-3;
Mask made by photoresist above S2 device, and ICP etches 50s, and the structure after etching as in Figure 2-4;
S3 chooses etching parameters, removes photoresist after etching completes, and measures the degree of depth etched with step instrument, is about 90nm;
S4 considers measure error, and determine splash-proofing sputtering metal Ti/Au 15/70nm, the groove that step 3 etches is filled and led up in the now large activation of the thickness of metal, as shown in Figure 2-5;
S5 peels off excess metal part, and the metal material (4) as the sputtering in Fig. 2-6, Fig. 2-6 after having peeled off is gate electrode;
S6PECVD grows 300nm SiO 2as insulating barrier, as Fig. 2-7;
S7 whirl coating, as Fig. 2-8, prepares photolithographic source, drain electrode patterns;
Source after S8 photoetching completes, drain electrode patterns, as shown in figs. 2-9;
S9 is similar with the step of etching gate electrode groove, and still make mask with photoresist, ICP etches 3min, and the structure after etching as shown in figs. 2-10;
S10 removes photoresist after having etched, and measures the degree of depth etched be about 300nm with step instrument;
S11 can fill up groove to make the Ti/Au of sputtering, and considers error, determines actual sputtered with Ti/Au100/290nm, as Fig. 2-11;
S12 peels off unnecessary metallic member, only leaves source, drain electrode structure, as Fig. 2-12.This completes the device architecture of graphene photodetector, Graphene is transferred on device.
S13 adopts CVD method growing graphene on Cu sheet, and whirl coating PMMA on Graphene, then dries 10min on the hot plate of 150 DEG C;
S14 configures the corrosive liquid of Cu, and corrosive liquid composition is CuSO 415g, HCl solution 50ml and deionized water 50ml, erodes Cu;
S15 pulls graphene film out after corroding 4 hours, is placed in clear water 2 hours;
Graphene film is transferred to and is carried out on the substrate of structure by S16, dries, and dry 15min, Graphene schematic diagram is on this structure as Fig. 2-13;
S17 photoetching, remove more than Graphene, stay and form the Graphene (5) of PN junction, as Fig. 2-14.
Embodiment 2: be applied in the fieldtron of Graphene
After silicon chip with insulating medium layer is cleaned by S1, whirl coating, prepares photoetching and forms gate electrode, as Fig. 3-1,3-2;
S2 photoetching forms gate electrode figure, as shown in Fig. 3-3;
S3 chooses etching parameters, makes mask with the photoresist above silicon chip, and ICP etches 80s, and the structure after etching as shown in Figure 3-4;
S4 removes photoresist after etching completes, and measures the degree of depth etched with step instrument, is 140nm;
S5 considers measure error, determines splash-proofing sputtering metal Ti/Au 30/100nm, the groove that step 3 etches is filled and led up in the now large activation of the thickness of metal, as in Figure 3-5;
S6 peels off unnecessary metallic member, defines required gate electrode structure, as Fig. 3-6 after having peeled off;
S7PECVD grows 300nm SiO 2as insulating barrier, as Fig. 3-7;
S8 whirl coating, prepares photolithographic source, drain electrode patterns, as Fig. 3-8;
Source after S9 photoetching completes, drain electrode patterns, as Fig. 3-9;
S10 is similar with the step of etching gate electrode, and still make mask with photoresist, ICP etches 2min, and the structure after etching as shown in figs. 3-10;
S11 removes photoresist after having etched, and measures the degree of depth etched be about 270nm with step instrument;
S12 can fill up groove to make the Ti/Au of sputtering, and considers error, determines actual sputtered with Ti/Au100/160nm, as Fig. 3-11;
S13 peels off unnecessary metallic member, as Fig. 3-12 after having peeled off.
This completes the process structure of the fieldtron of Graphene, Graphene (5) is transferred on device.The transfer process of Graphene is identical with description above, and the Graphene figure just stayed after final step photoetching is different, as Fig. 3-13,3-14.
Embodiment 3: be applied to Hall effect and measure in the mobility of Graphene
S1 prepares photoetching, as shown in Fig. 4-1 after being cleaned by the silicon chip with insulating medium layer;
S2 whirl coating to make electrode pattern by lithography, as Fig. 4-2
S3 photoetching, produces the figure of Fig. 4-3 structure;
Mask made by photoresist above S4 silicon chip, and ICP etches 35s, and the structure after etching is as shown in Fig. 4-4;
S5 chooses etching parameters, removes photoresist after etching completes, and measures the degree of depth etched with step instrument, is 65nm;
S6 considers measure error, determines splash-proofing sputtering metal Ti/Au 10/45nm, the groove that step 3 etches is filled and led up in the now large activation of the thickness of metal, as illustrated in figures 4-5;
S7 acetone peels off unnecessary metal, material is thus formed the structure shown in Fig. 4-6.
This completes the device architecture measuring Graphene mobility by Hall effect, next Graphene is transferred on device.The transfer process of Graphene is identical with description above, and the Graphene figure just stayed after final step photoetching is different, as Fig. 4-7,4-8.
Key of the present invention mainly ensures that the depth of groove etched is identical with the metal material thickness sputtered below, therefore the grid etched in above-mentioned steps, source and the drain electrode degree of depth and the metal alloy degree of depth sputtered subsequently, be not only confined to the numeral in above embodiment.
The foregoing is only better embodiment of the present invention, not in order to limit the present invention, all make under the prerequisite of spirit of the present invention and design any amendment, replacement and improvement etc., all should think and be included within protection scope of the present invention.

Claims (8)

1. a semiconductor technology for thin film planar, is characterized in that: concrete technology step is as follows:
After silicon chip with insulating medium layer is cleaned by S1, prepare photoetching, now insulating medium layer (2) is on silicon substrate (1);
S2 photoetching, photoresist (3) is on insulating medium layer (2);
S3 with photoresist (3) makes mask, and ICP etches, etched recesses;
S4 chooses etching parameters, removes photoresist after etching completes, and measures the degree of depth of institute's etched recesses with step instrument;
S5 splash-proofing sputtering metal, the thickness of sputtering is the corresponding degree of depth that previous step is measured, then the metal material now sputtered (4) can just fill and lead up the groove that S3 etches;
S6 organic solution peels off unnecessary metal.
2. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: when the film related to is graphene film, the silicon dioxide that insulating medium layer (2) is 300nm thickness.
3. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: the photoresist (3) of use is negative glue, is not the part needing to etch groove by photoresist (3) covering place.
4. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: described lithographic method is dry etching.
5. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: organic solution used need guarantee the photoresist (3) dissolved in S3.
6. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: be applied in the photodetector of Graphene,
After silicon chip with insulating medium layer is cleaned by S1, photoetching forms the figure of gate electrode;
Mask made by photoresist above S2 device, and ICP etches 50s;
S3 chooses etching parameters, removes photoresist after etching completes, and to measure with step instrument the degree of depth etched be 90nm;
S4 considers measure error, and determine splash-proofing sputtering metal Ti/Au 15/70nm, the groove that S3 etches is filled and led up in the now large activation of the thickness of metal;
S5 peels off excess metal part, and the metal material (4) of the sputtering after having peeled off is gate electrode;
S6PECVD grows 300nm SiO 2as insulating barrier;
S7 whirl coating, prepares photolithographic source, drain electrode patterns;
Source after S8 photoetching completes, drain electrode patterns;
S9 is similar with the step of etching gate electrode groove, and still make mask with photoresist, ICP etches 3min;
S10 removes photoresist after having etched, and measures the degree of depth etched be about 300nm with step instrument;
S11 can fill up groove to make the Ti/Au of sputtering, and considers error, determines actual sputtered with Ti/Au 100/290nm;
S12 peels off unnecessary metallic member, only leaves source, drain electrode structure; This completes the device architecture of graphene photodetector, Graphene is transferred on device;
S13 adopts CVD method growing graphene on Cu sheet, and whirl coating PMMA on Graphene, then dries 10min on the hot plate of 150 DEG C;
S14 configures the corrosive liquid of Cu, and corrosive liquid composition is CuSO 415g, HCl solution 50ml and deionized water 50ml, erodes Cu;
S15 pulls graphene film out after corroding 4 hours, is placed in clear water 2 hours;
Graphene film is transferred to and is carried out on the substrate of structure by S16, dries, and dries 15min;
S17 photoetching, remove more than Graphene, stay and form the Graphene (5) of PN junction.
7. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: be applied in the fieldtron of Graphene,
After silicon chip with insulating medium layer is cleaned by S1, whirl coating, prepares photoetching and forms gate electrode;
S2 photoetching forms gate electrode figure;
S3 chooses etching parameters, makes mask with the photoresist above silicon chip, and ICP etches 80s;
S4 removes photoresist after etching completes, and measures the degree of depth etched with step instrument, is 140nm;
S5 considers measure error, determines splash-proofing sputtering metal Ti/Au 30/100nm, the groove that S3 etches is filled and led up in the now large activation of the thickness of metal;
S6 peels off unnecessary metallic member, defines required gate electrode structure after having peeled off;
S7PECVD grows 300nm SiO 2as insulating barrier;
S8 whirl coating, prepares photolithographic source, drain electrode patterns;
Source after S9 photoetching completes, drain electrode patterns;
S10 is similar with the step of etching gate electrode, and still make mask with photoresist, ICP etches 2min;
S11 removes photoresist after having etched, and measuring with step instrument the degree of depth etched is 270nm;
S12 can fill up groove to make the Ti/Au of sputtering, and considers error, determines actual sputtered with Ti/Au 100/160nm;
S13 peels off unnecessary metallic member;
This completes the process structure of the fieldtron of Graphene, Graphene (5) is transferred on device; The transfer process of Graphene is identical with description above, and the Graphene figure just stayed after final step photoetching is different.
8. the semiconductor technology of a kind of thin film planar according to claim 1, is characterized in that: be applied to Hall effect and measure in the mobility of Graphene,
S1 prepares photoetching after being cleaned by the silicon chip with insulating medium layer;
S2 whirl coating is to make electrode pattern by lithography;
S3 photoetching, produces the figure of structure;
Mask made by photoresist above S4 silicon chip, and ICP etches 35s;
S5 chooses etching parameters, removes photoresist after etching completes, and measures the degree of depth etched with step instrument, is 65nm;
S6 considers measure error, determines splash-proofing sputtering metal Ti/Au 10/45nm, the groove that S3 etches is filled and led up in the now large activation of the thickness of metal;
S7 acetone peels off unnecessary metal.
CN201510262462.5A 2015-05-21 2015-05-21 Semiconductor process for film planarization Pending CN104867817A (en)

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CN110556283A (en) * 2018-05-30 2019-12-10 山东大学 Method for preparing graphene and graphene device by pretreating SiC substrate epitaxy
CN110556283B (en) * 2018-05-30 2021-11-26 山东大学 Method for preparing graphene and graphene device by pretreating SiC substrate epitaxy

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Application publication date: 20150826