CN1441996A - Fast switching input buffer - Google Patents
Fast switching input buffer Download PDFInfo
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- CN1441996A CN1441996A CN01812668A CN01812668A CN1441996A CN 1441996 A CN1441996 A CN 1441996A CN 01812668 A CN01812668 A CN 01812668A CN 01812668 A CN01812668 A CN 01812668A CN 1441996 A CN1441996 A CN 1441996A
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- 239000000872 buffer Substances 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 210000000746 body region Anatomy 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 206010065929 Cardiovascular insufficiency Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
An input buffer circuit (300) for a semiconductor device that includes a PMOS transistor (306), an NMOS transistor (308), and a pull-up circuit (314). The pull-up circuit (314) applies a voltage to the bulk region of the PMOS transistor (306) causing a positive body effect which causes the absolute value of the voltage threshold of the PMOS transistor (306) to temporally lower when the input buffer (300) switches. This causes the input buffer (300) to switch faster than conventional input buffers. The input buffer (300) is an inverter, NOR, NAND, or other input buffer.
Description
Technical field
The present invention relates to a kind of CMOS input buffer that is used for semiconductor device.
Background technology
Complementary metal oxide semiconductor (CMOS) input buffer uses for many years in semiconductor device.A key property of input buffer is switching time, promptly be converted to low state required time by high state, or vice versa.
Fig. 1 explanation is used for the example of the existing CMOS inverter of semiconductor device input buffer 100.CMOS inverter input buffer 100 comprises a P-channel mosfet transistor 106, also is called the PMOS transistor, and the N-channel mosfet transistor 108 of a tool complementary structure, also is called nmos pass transistor.The grid of PMOS and nmos pass transistor 106,108 joins with the input node 102 that also is called input terminal.Because of two grids all join with input node 102, so input signal also is called grid voltage Vg.Output signal is transmitted by the output node 110 that also is called outlet terminal.Output node 110 joins with the drain electrode of PMOS and nmos pass transistor 106,108.When a low signal, be no-voltage haply, when imposing on input node 102,106 unblanks of PMOS transistor, and nmos pass transistor 108 shutoffs make output node 110 become high state.When a high signal, be service voltage haply, when imposing on input terminal 102, PMOS transistor 106 is turned off, and nmos pass transistor 108 unblanks, makes output node become low state.Because one of them is maintained at off state PMOS and nmos pass transistor, then if there is any DC current drain also to be trace.
Fig. 2 illustrates the example of existing CMOS NOR input buffer 200.CMOS NOR input buffer 200 comprises the first and second PMOS transistors 210,212, and first and second nmos pass transistors 214,216.The grid of the 2nd PMOS transistor 212 and first nmos pass transistor 214 joins with input node 202.Output signal is transmitted by the output node 220 that joins with the 2nd PMOS transistor 212,214,216 drain electrodes of first and second nmos pass transistor." power-off " control signal receives in Control Node 218.The grid of Control Node 218 and a PMOS transistor 210 and second nmos pass transistor 216 joins.
Summary of the invention
The present invention is a kind of input buffer circuit that is used for semiconductor device, comprises a PMOS transistor, a nmos pass transistor and a pull-up circuit.Pull-up circuit applies voltages to the transistorized body region of PMOS, produces positive main body effect, and when input buffer switched, this effect can temporarily reduce PMOS transistor threshold voltage absolute value.The existing input buffer of ratio that so makes input buffer switch is quick.This input buffer is inverter, NOR, NAND or other input buffer.
Description of drawings
Description of the invention is with reference to accompanying drawing.In figure, similar Ref. No. is represented assembly similar on identical or the function.In addition, the icon that occurs first of the leftmost numeral Ref. No. of Ref. No..
Fig. 1 is the icon of existing CMOS inverter input buffer;
Fig. 2 is the icon of existing CMOS NOR input buffer;
Fig. 3 is the icon of the present invention about CMOS inverter input buffer embodiment;
Fig. 4 is the icon of the present invention about CMOS NOR input buffer embodiment; And
Fig. 5 implements the cross-sectional view of assembly for PMOS transistor of the present invention.
Embodiment
The input unit that is used for semiconductor device as memory device SRAM and DRAM, provides the quick switching between high and low output state.Operate on the input unit tool low current leakage of low service voltage.The present invention can temporarily reduce the cut-ff voltage absolute value, reduces switching time, and can not produce the leakage current of essence.
The signal of input buffer monitoring input node, and according to input node switching output node.When the input buffer and the circuit that surpass output node operate between service voltage Vcc and the ground connection, then will be positioned at than close limit, for example Vih and Vil in the input signal that node received.Vih represents " height ", and signal, Vil are represented " low " signal.Because linear capacitance and other factor, Vil is usually less than service voltage usually above ground connection and Vih.
When operating in low service voltage, even in than jogging speed, the PMOS transistor also is inclined to switching.Low service voltage is for being lower than 3.3 volts, as the service voltage of 1.8 volts or 1.6 volts.In many application, The faster the better on electric brake running ground.
The principle of CMOS design is that the PMOS transistor is than nmos pass transistor " weak ".This is the mobility factor.Because of the transistorized threshold voltage absolute value of PMOS | Vt| with respect to nmos transistor gate ration the power supply press high, input buffer by " height " extremely switching time of " low " common than by " low " extremely switching time of " height " fast.Threshold voltage is high or low state in order to the signal of decision incoming line.If reduce PMOS transistor cut-ff voltage absolute value, attempt to reduce switch speed, then the transistorized leakage current of PMOS will produce undesirable increase.The present invention can temporarily reduce the threshold voltage absolute value, reducing switching time, and can not produce the leakage current of essence, shown in the 3rd to 5 figure.
Fig. 3 illustrates that tool switches fast and the example of the CMOS inverter input buffer 300 of low ullage.CMOS inverter input buffer 300 comprises the nmos pass transistor 308 of a PMOS transistor 306, a tool complementary structure, drawing upwardly device 314, and selectivity capacitor 312.The grid of PMOS and nmos pass transistor 306,308 joins with input node 302.Output signal is transmitted by the output node 310 that joins with the drain electrode of PMOS and nmos pass transistor 306,308.Drawing upwardly device 314, for example a resistance joins with the main body of service voltage and PMOS transistor 306.
The resistance of drawing upwardly device 314 depends on the characteristic of input buffer 300 and the especially characteristic of PMOS transistor 306.For example, resistance value can be 1,000 ohm to 3,000 thousand ohm.Other drawing upwardly device 314 also can use, and needing only them provides voltage to the transistorized body region of PMOS, for example a RL circuit, a diode or other device.Drawing upwardly device 314 provides the main body of voltage to PMOS transistor 306 as a charging mechanism.
A selectivity capacitor 312 joins with transistorized grid of PMOS and main body.When PMOS and nmos pass transistor 306,308 can't provide enough input capacitances to increase the switching time of buffer, then capacitor 312 increases grid capacitances to input buffer 300.
When input signal becomes lowly, promptly import node 302 and receive Vil, then grid capacitance moment the body region of PMOS transistor 306 is reduced.This measure makes the threshold voltage absolute value | and vt| reduces.Therefore, PMOS transistor 306 becomes " strong ", and electric current passes the P-channel quickly.After output switched to high state, the body region of drawing upwardly device 314 pair pmos transistors 306 was returned and is charged to service voltage.PMOS transistor 306 and drawing upwardly device 314 can at random join with different service voltages.
Fig. 4 illustrates that tool switches fast and the example of the CMOS NOR input buffer 400 of low current leakage.CMOS NOR input buffer 400 comprises first and second PMOS transistor 410,412, first and second nmos pass transistor 414,416, first and second drawing upwardly device 406,408, and a selectivity capacitor 422.The grid of the 2nd PMOS transistor 412 and first nmos pass transistor 414 joins with input node 402.Output signal is transmitted by the output node 420 that joins with the drain electrode of the 2nd PMOS transistor 412, first and second nmos pass transistor 414,416.The source electrode and the earth terminal of first and second nmos pass transistor 414,416 join.The drain electrode of the source electrode of the 2nd PMOS transistor 412 and a PMOS transistor 410 is joined.The source electrode of the one PMOS transistor 410 and service voltage 404 join.Be denoted as the control signal of " power-off ", receive in Control Node 418.The grid of control signal and a PMOS transistor 410 and second nmos pass transistor 416 joins.Control Node 418 and input node 402 are the input to the NOR circuit, and output node is the output of NOR circuit.
First drawing upwardly device 406 joins with the main body of a service voltage and a PMOS transistor 410.Second drawing upwardly device 408 also deserves to be called puller circuit, joins with service voltage 404 and the 2nd PMOS transistor 412 main bodys.The resistance of drawing upwardly device 406,408 depends on the characteristic of input buffer 400 and the PMOS characteristics of transistor that especially it connected.For example, the resistance of drawing upwardly device 406,408 can be 1,000 ohm to 3,000 thousand ohm.Other numerical value also can be accepted, and depends on the characteristic of input buffer 400.Drawing upwardly device 406,408 can comprise other circuit, needs only circuit the body region of voltage to PMOS transistor 410,412 is provided, for example a RL circuit, a rlc circuit, a diode circuit or other device.The drawing upwardly device 406,408 of this embodiment is as a charging mean, provides voltage to PMOS transistor 410,412 main bodys.In another embodiment, only use in the drawing upwardly device 406,408.
A selectivity capacitor 422 can add to increase grid capacitance.The grid and the main body of selectivity capacitor 422 and the 2nd PMOS transistor 412 are joined.
Optional land used, a PMOS transistor 410 and drawing upwardly device 406,408 join with different service voltages respectively.Common service voltage is 5.0 volts and 3.3 volts.The present invention preferably uses low-power input buffer.The service voltage of low-power input buffer is 3.3 volts or littler.For example, service voltage is about 2.0 volts to 1.0 volts.The present invention also can use under other service voltage scope.
Fig. 5 specifically implements the cross-sectional view of assembly PMOS transistor 500 for the present invention.PMOS transistor 500 comprises a N-type substrate regions 526, dielectric medium zone 524, two P-type zones 518,522, and a P-channel region 520, also is called the N-well area.The outer interface of PMOS transistor 500 comprises a source electrode 512, grid 514, drain electrode 516, and main body 528.PMOS transistor 500 has a drawing upwardly device 506, and it is connected main body 528 with service voltage in source node 504.A selectivity capacitor 508 joins main body 528 and grid 514.Grid 514 joins with the gate node 502 that receives signal.Drain electrode 516 is joined with the drain node 510 that transmits the output that is produced by PMOS transistor 500.When ground connection, be zero volt haply, add to gate node 502, no P-channel 520 produces, and drain electrode 516 provides Weak current.When negative voltage added to gate node 502, electronics was ostracised by the surface, produced P-channel 520, and this is a conductive area, and provided by the positive current of source electrode 512 to drain electrode 516.
When after grid voltage Vb, and the potential difference of source voltage Vs is called Vbs, applied signal voltage is negative when changing, and will produce the main body effect phenomenon in nmos pass transistor, and increases the nmos transistor gate pressure absolute value of rationing the power supply.For the PMOS transistor, potential difference Vbs will just change, to increase the cut-ff voltage absolute value.When this phenomenon when nmos pass transistor produces, grid is to the voltage of source electrode, Vgs descends, the driving force of nmos pass transistor descends, and the signal transfer resistance increases.This is " to bear " main body effect phenomenon.The present invention uses and is called the complementary phenomenon of " just " main body effect with temporary transient reduction PMOS transistor threshold voltage absolute value.
Above-mentioned input buffer 300 (Fig. 3), the high DC cut-ff voltage of 400 (Fig. 4) tool cause lower leakage voltage.In addition, input buffer 300,400 tools hang down the AC threshold voltage, and very fast switching and low drain voltage are provided.Estimate this input buffer can in existing low-voltage input buffer required time about 50% to 60% in, switch to low state by height.
When incoming line is converted to low state by height, to logical zero, grid capacitance will descend moment by logical one.This measure descends the threshold voltage absolute value.Electric current then passes through the P-channel quickly.This measure makes output voltage V o, quickly by the low high state that switches to.The voltage of body layer, Vbulk after output node 510 switches to high state, recharges to maximum service voltage via drawing upwardly device 506.Optionally, add capacitor 508, to increase grid capacitance.
Following equation is described the factor that influences the threshold voltage absolute value:
| V
t|=V
T0+ δ * [sqrt (2 Φ F+V
Bs)-sqrt (2 Φ F)] equation 1
Wherein:
| Vt| is a PMOS transistor threshold voltage absolute value.
Threshold voltage when Vt0 is Vbs=0.
δ is the bias effect constant of substrate.This constant be manufacture process function and the device between different.
Φ F is the main body current potential.The main body current potential be manufacture process function and the device between different.
Vbs is the voltage difference between main body and source electrode.
Be the temporary transient threshold voltage absolute value that reduces | Vt|, when grid voltage state from high to low, | Vbs| will descend, that is body voltage Vb, be increased to source voltage Vs, promptly main body to source voltage Vbs for bearing.When grid voltage switch to low, body voltage coupled gates voltage, and bring to lower than service voltage.This measure temporarily reduces PMOS transistor cut-ff voltage absolute value | and Vt|, it is quicker to make that output voltage V out switches.
The RC circuit, 506 and 508 (Fig. 5) for example when body voltage during less than source voltage, preferably adjust to avoid the breech lock situation.
Though Fig. 3 to 5 inverter of explanation and a NOR input buffer, the present invention can together use with other input buffer that is used in semiconductor device, as memory device.For example, the present invention can together use with the NAND input buffer.
Though in this demonstration and describe preferred embodiment, as can be known be that they are not in order to limiting this announcement, and be to desire to comprise all by modification, alternative method and device in claim scope of the present invention or defined spirit of the present invention of equal meaning and the category.
Claims (10)
1. input buffer circuit (300) that is used for semiconductor device comprises:
(a) input node (302);
(b) output node (310);
(c) PMOS transistor (306) that has source electrode, grid, drain electrode, reaches master nodes, the source node of PMOS transistor (306) and first service voltage (304) join;
(d) one have source electrode, grid, with the nmos pass transistor (308) of drain node, this source node ground connection;
Wherein the grid of this PMOS and nmos pass transistor (306,308) joins with input node (302), and the drain electrode and the output node (310) of PMOS and nmos pass transistor (306,308) join; And
(e) pull-up circuit (314) joins with the master nodes and second service voltage of PMOS transistor (306).
2. input buffer circuit as claimed in claim 1 (300), wherein this input buffer circuit (300) comprises a low-power input buffer circuit.
3. input buffer circuit as claimed in claim 1 (300), wherein this first (304) and second service voltage provides identical haply voltage.
4. input buffer circuit as claimed in claim 1 (300), wherein this first service voltage (304) is less than or equal to 1.9 volts.
5. input buffer circuit as claimed in claim 1 (300), wherein this pull-up circuit (314) comprises a resistor.
6. input buffer circuit as claimed in claim 1 (300) more comprises a capacitor circuit (312) that joins with PMOS transistor (306) source electrode and master nodes.
7. input buffer circuit as claimed in claim 1 (300), wherein this pull-up circuit (314) reduces the switching time of the threshold voltage and the minimizing input buffer circuit (300) of PMOS transistor (306).
8. input buffer circuit as claimed in claim 1 (300), wherein this input buffer circuit (300) comprises a CMOS inverter circuit.
9. an input buffer circuit (400), comprise an input node (402), an output node (420), select node (418) for one, first and second PMOS transistor (410,412), each all has source electrode, grid, drain electrode, and master nodes, wherein the source node of the 2nd PMOS transistor (412) and this first service voltage (404) join, first and second nmos pass transistor (414,416) both all have source electrode, grid, with drain node, this first and second nmos pass transistor (414 wherein, 416) source node ground connection, this first and second nmos pass transistor (414,416) drain node and output node (420) join, the gate node of this first nmos pass transistor (414) joins with input node (402), and the gate node of second nmos pass transistor (416) joins with selecting node (418), wherein the drain node of a PMOS transistor (410) and output node (420) join, the grid of the one PMOS transistor (410) joins with input node (402), and the gate node of the 2nd PMOS transistor (412) joins with selecting node (418); The master nodes that it is characterized by this first pull-up circuit (406) and a PMOS transistor (410) is joined and this master nodes and the 3rd service voltage of this second service voltage and this second pull-up circuit (408) and the 2nd PMOS transistor (412) join.
10. memory device comprises:
(a) a CMOS input buffer (300) comprises at least one nmos pass transistor (308), PMOS transistor (306) that at least one joins with nmos pass transistor (308), and pull-up circuit (314) that is connected PMOS transistor (306) master nodes to service voltage (304); And
(b) memory array that joins with CMOS input buffer (300).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US61635700A | 2000-07-14 | 2000-07-14 | |
| US09/616,357 | 2000-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1441996A true CN1441996A (en) | 2003-09-10 |
Family
ID=24469083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN01812668A Pending CN1441996A (en) | 2000-07-14 | 2001-06-29 | Fast switching input buffer |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1307965A1 (en) |
| JP (1) | JP2004504751A (en) |
| KR (1) | KR20030016401A (en) |
| CN (1) | CN1441996A (en) |
| AU (1) | AU2001271671A1 (en) |
| BR (1) | BR0112513A (en) |
| TW (1) | TW498617B (en) |
| WO (1) | WO2002007317A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795134A (en) * | 2010-03-18 | 2010-08-04 | 中国科学院上海微系统与信息技术研究所 | Circuit for lowering CMOS transient power consumption |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644266A (en) * | 1995-11-13 | 1997-07-01 | Chen; Ming-Jer | Dynamic threshold voltage scheme for low voltage CMOS inverter |
| KR100242997B1 (en) * | 1996-12-30 | 2000-02-01 | 김영환 | Low power consumption input buffer |
| KR100245556B1 (en) * | 1997-05-27 | 2000-02-15 | 윤종용 | Semiconductor random access memory device of soi having word line driving circuit |
-
2001
- 2001-06-29 AU AU2001271671A patent/AU2001271671A1/en not_active Abandoned
- 2001-06-29 KR KR10-2003-7000515A patent/KR20030016401A/en not_active Application Discontinuation
- 2001-06-29 CN CN01812668A patent/CN1441996A/en active Pending
- 2001-06-29 WO PCT/US2001/020818 patent/WO2002007317A1/en not_active Application Discontinuation
- 2001-06-29 JP JP2002513098A patent/JP2004504751A/en not_active Withdrawn
- 2001-06-29 BR BR0112513-3A patent/BR0112513A/en not_active Application Discontinuation
- 2001-06-29 EP EP01950703A patent/EP1307965A1/en not_active Withdrawn
- 2001-07-06 TW TW090116545A patent/TW498617B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101795134A (en) * | 2010-03-18 | 2010-08-04 | 中国科学院上海微系统与信息技术研究所 | Circuit for lowering CMOS transient power consumption |
Also Published As
| Publication number | Publication date |
|---|---|
| AU2001271671A1 (en) | 2002-01-30 |
| BR0112513A (en) | 2003-07-01 |
| EP1307965A1 (en) | 2003-05-07 |
| WO2002007317A1 (en) | 2002-01-24 |
| TW498617B (en) | 2002-08-11 |
| KR20030016401A (en) | 2003-02-26 |
| JP2004504751A (en) | 2004-02-12 |
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