CN1228845C - Linear current/voltage characteristics metal oxide semiconductor output driving circuit - Google Patents
Linear current/voltage characteristics metal oxide semiconductor output driving circuit Download PDFInfo
- Publication number
- CN1228845C CN1228845C CN 02102561 CN02102561A CN1228845C CN 1228845 C CN1228845 C CN 1228845C CN 02102561 CN02102561 CN 02102561 CN 02102561 A CN02102561 A CN 02102561A CN 1228845 C CN1228845 C CN 1228845C
- Authority
- CN
- China
- Prior art keywords
- output
- transistor
- driving circuit
- coupling
- output driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The present invention discloses an output driving circuit with the characteristics of linear current/voltage, for example, output impedance is a fixed value when output voltage is converted. The output driving circuit comprises a first input transistor, a second input transistor, a first pair of transistors, a second pair of transistors, a first output transistor and a second output transistor, wherein the first input transistor and the second input transistor which respectively input a first input signal and a second input signal are respectively provided with output nodes coupled with output nodes of the circuit; the first pair of transistors and the second pair of transistors respectively generate a second control signal and a fourth control signal according to a first control signal, a third control signal, a first output signal and a third output signal; the first output transistor and the second output transistor which respectively receive the second control signal and the fourth control signal are respectively provided with output nodes respectively coupled with the output nodes of the circuit.
Description
Technical field
The present invention relates to have the metal oxide semiconductor output driving circuit of linear current/voltage characteristic.
Background technology
Because have that reaction speed is fast, advantages such as low-energy-consumption and high integration, the semiconductor chip that contains metal-oxide semiconductor (MOS) (MOS) circuit is of many uses.For example metal oxide semiconductor output driving circuit is usually used in driving the required voltage standard of arrival, to transmit desired logical value.
With reference to figure 1 a known metal oxide semiconductor output driving circuit has been described.The source electrode of the mos field effect transistor of P shape (PMOSFET) 140 (source node) is connected with reference voltage Vss.Reference voltage is the metastable voltage source that provides according to design specification, 3 or 5 volts of voltages using always as the MOS assembly.When the initial voltage value of input node (input node) 110 and 120 is hanged down, at the initial voltage value height of output node 130.When importing node 120 and input node 140 respectively from prime driver (predriver, not shown) when receiving the signal of high-voltage value, the source electrode and the gate leve of P shape mos field effect transistor 140 all can be drawn high, and P shape mos field effect transistor 140 can be closed thus.While N shape mos field effect transistor (NMOSFET) 150 is also drawn high and the source electrode of N shape mos field effect transistor 150 is a ground connection, and N shape mos field effect transistor 150 is opened thus.In this example, the drain electrode of N shape mos field effect transistor 150 and gate pole are drawn high simultaneously, so N shape mos field effect transistor 150 is to operate under the saturation region.Owing to opened by N shape mos field effect transistor 150, the magnitude of voltage of output node 130 begins to descend.When the magnitude of voltage reduction of output node 130, N shape mos field effect transistor 150 can become triode (triode) zone at last.Above operation is called drawing of output signal and falls transformation (pull-down transition).
In the same manner, open and N shape mos field effect transistor 150 when closing when P shape mos field effect transistor 140, known metal oxide semiconductor output driving circuit also can experience to draw and fall transformation (pull-down transition).
When 150 operations of N shape mos field effect transistor transfer triode region to from the zone of saturation, descend with output node 130 viewpoint output impedance meetings.Therefore known metal oxide semiconductor output driving circuit changes when drawing high or draw to fall that the impedance meeting changes when taking place.For known metal oxide semiconductor output driving circuit, when drawing high or draw, generation falls when changing, and it is unapproachable that fixing output impedance is provided.
Summary of the invention
The present invention introduces compensating circuit (compensation circuit) and overcomes impedance change problem in output driving circuit.
Main purpose of the present invention is for providing the output driving circuit that has the good signal performance.
Another object of the present invention has linear current/voltage characteristic, i.e. Gu Ding output impedance for a kind of output driving circuit is provided.
A further object of the present invention has constant output impedance for an output driving circuit is provided, and can be easy to be used in the CMOS (Complementary Metal Oxide Semiconductor) integrated circuit manufacture process of standard now.
Output driving circuit of the present invention comprises first input transistors, second input transistors, first pair of transistor, second pair of transistor, first output transistor and second output transistor.First input transistors is imported first input signal, and the coupling of the output node of output node and output driving circuit.Second input transistors is imported second input signal, and the coupling of the output node of output node and output driving circuit.First pair of transistor, first control signal and output signal according to corresponding to first input signal produce second control signal.Second pair of transistor, the 3rd control signal and output signal according to corresponding to second input signal produce the 4th control signal.First output transistor is used to receive second control signal, and the coupling of the output node of output node and output driving circuit.Second output transistor is used to receive the 4th control signal, and the coupling of the output node of output node and output driving circuit.
Description of drawings
Fig. 1 is known metal oxide semiconductor output driving circuit schematic diagram.
Fig. 2 a is respectively four kinds of preferred embodiments of the present invention to Fig. 2 d.
Fig. 3 a is respectively other four kinds of preferred embodiments of the present invention to Fig. 3 d.
Embodiment
Below described circuit formed by field-effect transistor (FET).But circuit described in the invention is not limited to make field-effect transistors, and is not limited to other transistor such as bipolar junction transistor (bipolar junction transistor) or the combination of field-effect transistor and bipolar junction transistor or the similar techniques of other any kind of.In addition, the present invention can use in a different manner, as is used for single component or integrated circuit.
Please refer to Fig. 2 a, first preferred embodiment of the present invention comprises first input transistors 210, is preferably the P-type mos field effect transistor element, and second input transistors 215 is preferably N type metal oxide semiconductor field effect transistor element.First pair of transistor, comprise P-type mos field-effect transistor 220, N type metal oxide semiconductor field-effect transistor 225, second pair of transistor comprises P-type mos field-effect transistor 230, N type metal oxide semiconductor field-effect transistor 235.First output transistor 240 is preferably the P-type mos field effect transistor element, and second input transistors 245 is preferably N type metal oxide semiconductor field effect transistor element.Output driving circuit also comprises inverter 250 and 255.
Suppose that output node 270 is drawn high at the beginning, input node 260 and 265 receives high signal (high signal) from prime driver (predriver, not shown) respectively.The process of falling of drawing is below described.The source electrode of P-type mos field-effect transistor 210 and gate pole are all drawn high, and P-type mos field-effect transistor 210 is a closed condition.The source electrode of N type metal oxide semiconductor field-effect transistor 215 is a ground connection and its gate pole is drawn high, so N type metal oxide semiconductor field-effect transistor 215 is open modes.Inverter 250 output low signals (low signal).The door-plate of the gate pole of the output node of inverter 250, P-type mos field-effect transistor 220 and N type metal oxide semiconductor field-effect transistor 225 is coupled.Because the gate pole of P-type mos field-effect transistor 220 is received low signal, and its source electrode is connected with reference voltage, and P-type mos field-effect transistor 220 is an opening.N type metal oxide semiconductor field-effect transistor 225 is just in time opposite, is closed condition.Because its gate pole draws fallen, and source electrode because of and output node 270 coupling drawn high.
When N type metal oxide semiconductor field-effect transistor 225 is closed, there is not the electric current node 280 of flowing through.So node 280 is followed the high-voltage value of (trace) node 270.At this moment, P type semiconductor field-effect transistor 240 is closed.Because inverter 250,255 output low signals, and transistor 220,225 and the 230, the 235th, symmetrical, therefore hold to obtain the result that P-type mos field-effect transistor 230 is opened and N type metal oxide semiconductor field-effect transistor 235 is closed very much.The gate pole of N type metal oxide semiconductor field-effect transistor 245 and node 290 couplings.Node 290 is followed the high-voltage value of node 270, and N type metal oxide semiconductor field-effect transistor 245 is unlocked.
Must be noted that above operation comes down to finish with the time.N type metal oxide semiconductor field- effect transistor 215 and 245 all is unlocked and operates in the zone of saturation.From output node 270, the output impedance of N type metal oxide semiconductor field-effect transistor 215 and two parallel connections of 245 pictures.Because N type metal oxide semiconductor field-effect transistor 215 is at zone of saturation operation, its output impedance value height.Because the magnitude of voltage height of node 290 and node 270, N type metal oxide semiconductor field-effect transistor 245 are to connect in the configuration (diode-connect configuration), so its output impedance value is low at diode.N type metal oxide semiconductor field-effect transistor 245 provides most output impedance of the output driving circuit shown in Fig. 2 a.Be of a size of the N type metal oxide semiconductor field-effect transistor 215 of B by careful selection, and be of a size of dimension ratio between the N type metal oxide semiconductor field-effect transistor 245 of D, can when changing, obtain high linear output (current/voltage) transformation curve.In this transistorized dimension definitions is (width/) ratio of assembly channel.So drive circuit can reach the purpose of output blocked impedance.
P type semiconductor field-effect transistor 230 and n type field effect transistor 245 are unlocked, and output signal draws the process of falling to begin to descend because of experiencing, and the drain voltage value of N type metal oxide semiconductor field-effect transistor 215 descends.Final N type metal oxide semiconductor field-effect transistor 215 enters three polar body zones (triode region), and the output impedance in three polar body zones is far beyond being low in the zone of saturation.Simultaneously, the magnitude of voltage of node 290 begins to reduce, and output node 270 also is.It is more and more higher that the output impedance of N type metal oxide semiconductor field-effect transistor 245 becomes, till transistor 245 is closed.
Suppose that output node 270 has just begun to be dragged down, input node 260 and 265 is received low signal from prime driver (not shown) respectively.Below narration draws high process.The source electrode of P-type mos field-effect transistor 210 and gate pole are all dragged down, and transistor 210 is opened.The source electrode of N type metal oxide semiconductor field-effect transistor 215 is a ground connection, and its gate pole is dragged down, so transistor 215 is for closing.The high signal of inverter 250 outputs.The gate pole of the gate pole of the output node of inverter 250, P-type mos field-effect transistor 220 and N type metal oxide semiconductor field-effect transistor 225 is coupled.Because the gate pole of P-type mos field-effect transistor 220 receives high signal, and its source electrode is connected with reference voltage, and P-type mos field-effect transistor 220 is a closed condition.N type metal oxide semiconductor field-effect transistor 225 just in time is opening on the contrary because and under output node 270 coupling states, its gate pole is drawn high and source electrode is dragged down.
When P-type mos field-effect transistor 220 is in closed condition, there is not the electric current node 280 of flowing through.So node 280 is followed the trail of node 270 low voltage value is arranged.At the same time, P-type mos field-effect transistor 240 is opened.Because the high signal of inverter 250,255 outputs, and transistor is symmetrical to 220,225 and 230,235, be easy to draw P-type mos field-effect transistor 230 and be closed condition, and N type metal oxide semiconductor field-effect transistor 235 is the result of opening.N type metal oxide semiconductor field-effect transistor 245 and node 290 couplings.Node 290 is followed the low voltage value of output node 270.N type metal oxide semiconductor field-effect transistor 245 is a closed condition.
Must be noted that above all operations is essentially simultaneously to be finished.P-type mos field-effect transistor 210 and 240 all is in opening and operates in the saturation area territory.From output node 270, the output impedance of P-type mos field-effect transistor 210 and two parallel connections of 240 pictures.Because P-type mos field-effect transistor 210 is at saturation region operation, its output impedance value height.Because the magnitude of voltage of node 280 and output node 270 is all low, so P-type mos field-effect transistor 240 is to connect in the configuration at three polar bodys.So the output impedance value of P-type mos field-effect transistor 240 is quite low.P-type mos field-effect transistor 240 accounts for the overwhelming majority to the output impedance of the output driving circuit shown in Fig. 2 a contribution.Be of a size of the P-type mos field-effect transistor 210 of A by careful selection, and be of a size of ratio between the P-type mos field-effect transistor 240 of C, can obtain when conversion, having high linear output (current/voltage) conversion line.In this transistorized dimension definitions is (width/height) ratio of assembly channel.So drive circuit can reach the purpose of output blocked impedance.
N type metal oxide semiconductor field-effect transistor 225 and P-type mos field-effect transistor 240 are unlocked, output signal begins to rise because of experiencing the process of drawing high, and the drain voltage value of P mos field effect transistor 210 increases.Final P-type mos field-effect transistor 210 enters three polar body zones (triode region), and the output impedance in three polar body zones is far beyond being low in the zone of saturation.Simultaneously, the magnitude of voltage of node 280 begins to increase, and node 270 also is.The output impedance of P-type mos field-effect transistor 240 is more and more higher, till transistor 240 is closed.
To achieve the object of the present invention, the present invention is just like Fig. 2 b, 2c and the described embodiment of 2d.
In Fig. 2 b, N type metal oxide semiconductor field-effect transistor 211 receives the signal of input node 260 via inverter 250.Suppose that output node 270 initially has high signal, and input node 260 and 265 receives high signal by the prime driver respectively.N type metal oxide semiconductor field-effect transistor 215 is opened.The gate pole of N type metal oxide semiconductor field-effect transistor 211 receives low signal by inverter 250, so N type metal oxide semiconductor field-effect transistor 211 is closed.The operation of the output driving circuit among the operation that is easy to learn Fig. 2 b and Fig. 2 a is identical.
In Fig. 2 c, P-type mos field-effect transistor 216 receives the signal of input node 265 via inverter 255.Suppose that output node 270 has high signal, and input node 260 and 265 receives high signal by the prime driver respectively.P-type mos field-effect transistor 210 is opened, and P-type mos field-effect transistor 216 is closed.The door-plate of P-type mos field-effect transistor 216 receives low signal by inverter 255, so P-type mos field-effect transistor 216 is closed.The operation of the output driving circuit among the operation that is easy to learn Fig. 2 c and Fig. 2 a is identical.
In Fig. 2 d, be to utilize N type metal oxide semiconductor field-effect transistor 212 and P-type mos field-effect transistor 217, without any need for inverter.Be easy to and infer the result of the output driving circuit among Fig. 2 d by similar output driving circuit among Fig. 2 a.
For protecting drive circuit of the present invention, (Electro Static Discharge ESD) does not destroy, and the present invention uses impedance in circuit, shown in Fig. 3 a, 3b, 3c and 3d by the static release effects.
Comparison diagram 3a and Fig. 2 a, impedance 391 is linked between the source electrode and output node 370 of N type metal oxide semiconductor field-effect transistor 325.Impedance 392 is connected between the source electrode and output node 370 of P-type mos field-effect transistor 330. Impedance 391 and 392 provides the discharge approach when the static release effects produces respectively, thus the transistor component of protection in circuit.The mode of operation of the output circuit of Fig. 3 a is similar with Fig. 2 a basically.
Fig. 3 b discloses the output circuit similar with Fig. 2 b, and contains the protective device of static release effects.The mode of operation of the output circuit of Fig. 3 b is similar with Fig. 2 b basically.
Fig. 3 c discloses the output circuit similar with Fig. 2 c, and contains the protective device of static release effects.The mode of operation of the output circuit of Fig. 3 c is similar with Fig. 2 c basically.
Fig. 3 d discloses the output circuit similar with Fig. 2 d, and contains the protective device of static release effects.The mode of operation of the output circuit of Fig. 3 d is similar with Fig. 2 d basically.
Above specification illustrates the present invention with specific preferred embodiment.Yet do not depart from the scope of the present invention with spirit under, the present invention can many alter modes implement.Above-mentioned specification and graphicly should be illustrative, and non-limiting scope of the present invention.Therefore the present invention cover appended claim and impartial variation and modification thereof.
Claims (26)
1. an output driving circuit that has linear current/voltage ratio provides an output signal via an output node, via drawing high or draw the variation that falls that one fixing output impedance is provided, comprises:
One first input transistors that is of a size of A is imported one first input signal, and this first input transistors has the output node coupling of an output node and this output driving circuit, and this size is by this transistorized width and the definition of length ratio;
One second input transistors that is of a size of B is imported one second input signal, and this second input transistors has the output node coupling of an output node and this output driving circuit;
One first pair of transistor is according to first control signal and this output signal corresponding to first input signal, to produce one second control signal;
One second pair of transistor is according to the 3rd control signal and this output signal corresponding to second input signal, to produce one the 4th control signal;
One first output transistor that is of a size of C is used to receive this second control signal, and this first output transistor has the output node coupling of an output node and this output driving circuit; And
One second output transistor that is of a size of D is used to receive the 4th control signal, and this second output transistor has the output node coupling of an output node and this output driving circuit;
Wherein A/C ratio and B/D ratio make when the variation that falls or draw high is drawn in this output node generation, obtain this fixing output impedance.
2. output driving circuit as claimed in claim 1, wherein this first input transistors has a gate pole to receive this first input signal, one source pole and reference voltage Vss coupling, and the output node of this first input transistors is a drain electrode.
3. output driving circuit as claimed in claim 1, wherein this output driving circuit more comprises one first inverter, responds this first input signal, produces this first control signal.
4. output driving circuit as claimed in claim 1, wherein this first input transistors has a gate pole to receive this first input signal via an inverter, and one source pole and is with reference to the ground connection coupling, and the output node of this first input transistors is a drain electrode.
5. output driving circuit as claimed in claim 1, wherein this second input transistors has a gate pole to receive this second input signal, and one source pole and is with reference to the ground connection coupling, and the output node of this second input transistors is a drain electrode.
6. output driving circuit as claimed in claim 1, wherein this output driving circuit more comprises one second inverter, responds this second input signal, produces the 3rd control signal.
7. output driving circuit as claimed in claim 6, wherein this second input transistors has a gate pole to receive this second input signal via an inverter, and one source pole and is with reference to the earthing device coupling, and the output node of this second input transistors is a drain electrode.
8. output driving circuit as claimed in claim 1, wherein this first input transistors has a gate pole to receive this first input signal, one source pole and with reference to ground connection coupling, the output node of this first input transistors is a drain electrode.
9. output driving circuit as claimed in claim 1, wherein this second input transistors has a gate pole to receive this second input signal, one source pole and reference voltage coupling, the output node of this second input transistors is a drain electrode.
10. output driving circuit as claimed in claim 1, wherein this first pair of transistor comprises:
One the first transistor has one source pole and reference voltage coupling, and a drain electrode is coupled with the gate pole of this first output transistor, and a gate pole receives this first control signal; And
One transistor seconds and this first transistor match each other, and this transistor seconds has the output node coupling of one source pole and this output driving circuit, a drain coupled of a drain electrode and this first transistor, and the coupling of the gate pole of a gate pole and this first transistor.
11. output driving circuit as claimed in claim 1, wherein this second pair of transistor comprises:
One the 3rd transistor has the output node coupling of one source pole and this output driving circuit, the gate pole coupling of a drain electrode and this second output transistor, and a gate pole receives the 3rd control signal; And
One the 4th transistor and the 3rd transistor match each other, and the 4th transistor has one source pole and with reference to the ground connection coupling, a drain coupled of a drain electrode and this first transistor, the gate pole coupling of a gate pole and this first transistor.
12. output driving circuit as claimed in claim 1, wherein this first output transistor has one source pole and reference voltage coupling, and a drain electrode and this output node coupling.
13. output driving circuit as claimed in claim 1, wherein this second output transistor has one source pole and with reference to the ground connection coupling, and a drain electrode and this output node coupling.
14. output driving circuit as claimed in claim 1 further comprises:
One first impedance provides this first pair of transistor anti-electrostatic-discharge effect protection; And
One second electricity group provides this second couple transistorized anti-electrostatic-discharge effect protection;
15. output driving circuit as claimed in claim 14, wherein this first input transistors has a gate pole to receive this first input signal, one source pole and reference voltage Vss coupling, and the output node of this first input transistors is a drain electrode.
16. output driving circuit as claimed in claim 14, wherein this output driving circuit more comprises an inverter, responds this first input signal, produces this first control signal.
17. output driving circuit as claimed in claim 16, wherein this first input transistors has a gate pole to receive this first input signal via an inverter, and one source pole and is with reference to the ground connection coupling, and the output node of this first input transistors is a drain electrode.
18. output driving circuit as claimed in claim 14, wherein this second input transistors has a gate pole to receive this second input signal, and one source pole and is with reference to the ground connection coupling, and the output node of this second input transistors is a drain electrode.
19. output driving circuit as claimed in claim 14, wherein this output driving circuit more comprises one second inverter, responds this second input signal, produces the 3rd control signal.
20. output driving circuit as claimed in claim 14, wherein this second input transistors has a gate pole to receive this second input signal via an inverter, and one source pole and is with reference to the ground connection coupling, and the output node of this second input transistors is a drain electrode.
21. output driving circuit as claimed in claim 20, wherein this first input transistors has a gate pole to receive this first input signal, one source pole and with reference to ground connection coupling, and the output node of this first input transistors is a drain electrode.
22. output driving circuit as claimed in claim 14, wherein this second input transistors has a gate pole to receive this second input signal, one source pole and reference voltage coupling, and the output node of this second input transistors is a drain electrode.
23. output driving circuit as claimed in claim 14, wherein this first pair of transistor comprises:
One the first transistor has one source pole and reference voltage coupling, and a drain electrode is coupled with the gate pole of this first output transistor, and a gate pole receives this first control signal; And
One transistor seconds and this first transistor match each other, and this transistor seconds has the output node coupling of one source pole and this output driving circuit, a drain coupled of a drain electrode and this first transistor, and the coupling of the gate pole of a gate pole and this first transistor.
24. output driving circuit as claimed in claim 14, wherein this second pair of transistor comprises:
One the 3rd transistor has the output node coupling of one source pole and this output driving circuit, the gate pole coupling of a drain electrode and this second output transistor, and a gate pole receives the 3rd control signal; And
One the 4th transistor and the 3rd transistor match each other, and the 4th transistor has one source pole and with reference to the ground connection coupling, a drain coupled of a drain electrode and this first transistor, the gate pole coupling of a gate pole and this first transistor.
25. output driving circuit as claimed in claim 14, wherein this first output transistor has one source pole and reference voltage coupling, and a drain electrode and this output node coupling.
26. output driving circuit as claimed in claim 14, wherein this second output transistor has one source pole and with reference to ground connection, and a drain electrode and this output node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02102561 CN1228845C (en) | 2002-01-28 | 2002-01-28 | Linear current/voltage characteristics metal oxide semiconductor output driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02102561 CN1228845C (en) | 2002-01-28 | 2002-01-28 | Linear current/voltage characteristics metal oxide semiconductor output driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1435884A CN1435884A (en) | 2003-08-13 |
| CN1228845C true CN1228845C (en) | 2005-11-23 |
Family
ID=27627611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02102561 Expired - Fee Related CN1228845C (en) | 2002-01-28 | 2002-01-28 | Linear current/voltage characteristics metal oxide semiconductor output driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1228845C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3901151B2 (en) * | 2003-12-25 | 2007-04-04 | セイコーエプソン株式会社 | Driver IC and driver IC and output device inspection method |
| JP2006279883A (en) * | 2005-03-30 | 2006-10-12 | Sanyo Electric Co Ltd | Driver circuit |
| US7924087B2 (en) * | 2008-05-20 | 2011-04-12 | Mediatek Inc. | Reference buffer circuit |
-
2002
- 2002-01-28 CN CN 02102561 patent/CN1228845C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1435884A (en) | 2003-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10177764B2 (en) | Input/output circuit | |
| US7554379B2 (en) | High-speed, low-power level shifter for mixed signal-level environments | |
| US7388410B2 (en) | Input circuits configured to operate using a range of supply voltages | |
| JP4768300B2 (en) | Voltage level conversion circuit and semiconductor integrated circuit device | |
| US5537059A (en) | Output circuit of semiconductor integrated circuit device | |
| US8149042B2 (en) | Analog switch for signal swinging between positive and negative voltages | |
| EP1387491A2 (en) | Level shifter and flat panel display | |
| KR20010049227A (en) | Level adjustment circuit and data output circuit thereof | |
| US10627847B2 (en) | Bias current circuit operating at high and low voltages | |
| WO2003030360A2 (en) | High voltage cmos output driver in low voltage process | |
| US7646233B2 (en) | Level shifting circuit having junction field effect transistors | |
| CN1855724B (en) | Buffer circuit | |
| CN109921779B (en) | Half-bridge circuit through protection circuit | |
| US7239176B2 (en) | Voltage tolerant protection circuit for input buffer | |
| US7492210B2 (en) | Voltage selection circuit | |
| US6717456B2 (en) | Level conversion circuit | |
| CN1228845C (en) | Linear current/voltage characteristics metal oxide semiconductor output driving circuit | |
| US20080024188A1 (en) | Junction field effect transistor level shifting circuit | |
| JP2009260832A (en) | Semiconductor device | |
| KR20070026612A (en) | Gate driver output stage with bias circuit for high and wide operating voltage range | |
| CN113285706B (en) | Voltage level conversion circuit | |
| JP4641660B2 (en) | Level shift circuit | |
| US6621322B2 (en) | Voltage generating circuit, level shift circuit and semiconductor device | |
| Park et al. | A novel level-shifter circuit design for display panel driver | |
| CN110391809A (en) | The stress of stacked transistors circuit reduces |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |