CN1432885A - Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method - Google Patents
Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method Download PDFInfo
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- CN1432885A CN1432885A CN 03106875 CN03106875A CN1432885A CN 1432885 A CN1432885 A CN 1432885A CN 03106875 CN03106875 CN 03106875 CN 03106875 A CN03106875 A CN 03106875A CN 1432885 A CN1432885 A CN 1432885A
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Abstract
The present invention provides a voltage stabilizing circuit and its relative control method and the present invention provides one stable voltage. The voltage stabilizing circuit includes a bipolar transistor, a capacitor module and an operation amplifier for feedback control. The operation amplifier has an amplifier circuit, a driver stage and a current mirror. The transistor charges the capacitor module to set the stable voltage; and the operation amplifier controls the drive current of the drive stage to the base of the transistor through feedback and based on the magnitude of the stable voltage. When the stable voltage is within some preset ranges, the current mirror provides a supplementary current implanted to the drive stage to decrease the drive current of the transistor base, and this can limit the transistor current.
Description
Technical field
The invention provides a kind of mu balanced circuit and corresponding control methods, refer in particular to a kind of mu balanced circuit and corresponding control methods that at the beginning of operation, can reduce the bipolar junction transistor drive current with the auxiliary current that another current mirror provides.
Background technology
In modern information society, electronic message unit of all kinds (little as mobile phone, greatly to computing machine, the webserver) all is based on various microcontrollers; Microcontroller can normally be moved, also just become one of most important research and development emphasis of modern information industry.
In order to improve the integrated level of semiconductor circuit in the microcontroller chip, reduce power consumption, increase arithmetic speed, the core circuit (core circuit) that is used for carrying out data operation, data processing in the chip all can be setovered with lower voltage, and the voltage level of electronic signal is also lower.But the data in the core circuit to be exported to the outer circuit board of chip, or data are inputed to chip when handling by circuit board, signal higher with voltage level usually, that power is bigger just has enough signal driving forces, so an output/input circuit (i/o buffer) can be set in the chip in addition, go into the usefulness of buffering as output.Fig. 1 shows that a known chip 10 cooperates the functional block diagram of a circuit board 12 operations.For instance, circuit board 12 can be a motherboard, and 10 of chips can be the chips of being located on the motherboard (as north and south bridge chip group); Perhaps circuit board 12 also can be the printed circuit board (PCB) on the auxiliary insert card (add-on card is as network card), and chip 10 is exactly the function that is used for controlling this auxiliary insert card.As previously mentioned, promptly be provided with a core circuit 14 and an output/input circuit 16 in the chip 10.Core circuit 14 is mainly used to carry out data operation and data processing.To export the data of circuit board 12 after core circuit 14 is handled to, or will import pending data into, then all will carry out the buffering of data and the conversion of signal via output/input circuit 16 to core circuit 14 via circuit board 12.Just as above-mentioned, core circuit 14 can be offset to lower voltage, and handled electronic data, signal also have lower voltage level; To will these data, voltage of signals level, power be improved by output/input circuit 16, so that transfer on the circuit board 12 with these data, when signal transfers to circuit board 12.In like manner, also can its signal level be reduced,, make things convenient for core circuit 14 to carry out data operation and data processing to meet the lower bias voltage of core circuit 14 by the pending data, signal that circuit board 12 transfers to core circuit 14 by output/input circuit 16.
Because the direct swap data of output/input circuit 16 and circuit board 12 energy on circuit design, output/input circuit 16 is offset to identical voltage usually with circuit board 12; DC voltage Vcc among Fig. 1, Vss (voltage that DC voltage Vss can hold with regarding as) promptly are used for the output/input circuit 16 in biasing circuit plate 12 and the chip 10.But, as previously mentioned, core circuit 14 can be offset to lower DC voltage, and therefore, chip 10 will cooperate circuit board 12 to cooperate a mu balanced circuit 18, to produce the voltage of voltage regulation Vp25 core circuit 14 of setovering.With typical example, circuit board 12 can provide the Dc bias (just DC voltage Vcc is 3.3 volts) of 3.3 volts (volt) to chip 10, and core circuit 14 then can be offset to lower 2.5 volts; In this configuration, mu balanced circuit 18 will utilize 3.3 volts DC voltage Vcc, produce 2.5 volts voltage of voltage regulation Vp25, the electricity needs during 14 operations of supply core circuit.In order to detect the situation that voltage of voltage regulation is set up, also be provided with a testing circuit 26 in the chip 10, be electrically connected to node Np0, be used for detecting voltage of voltage regulation and whether set up, and send a detection signal Vpg0 according to testing result.
As shown in Figure 1, in known mu balanced circuit 18, can use pnp type bipolar junction transistor Qp1 on the circuit board 12 as a charging circuit, and the capacitance module 24 that forms by high capacity capacitor C p1.Cooperate transistor Qp1, capacitance module 24 on the circuit board 12, then be provided with an operational amplifier 20, a reference voltage generator (bandgap circuit) 22 in the chip 10 and be used for two resistance R p0, Rp1 of dividing potential drop.Mu balanced circuit 18 is offset between DC voltage Vcc, the Vss; Wherein reference voltage generator 22 is used for producing a reference voltage Vbg0; 20 of operational amplifiers have two differential input terminal Inn0, Inp0, are electrically connected to node Np1 and reference voltage generator 22 respectively; Its output terminal Op0 then is electrically connected to the base stage (base) of transistor Qp1, and with the drive current Ib0 of a driving voltage Vd0, a correspondence as a drive signal, the base bias of oxide-semiconductor control transistors Qp1.Output terminal Op0 can be provided with a pin (pin) on the chip 10, so that can connect the transistor Qp1 to the circuit board 12.The emitter-base bandgap grading of transistor Qp1 (emitter) is offset to DC voltage Vcc, and collector (collector) then is electrically connected to capacitance module 24 in node Np0.The capacitor C p1 that is provided with high capacity in the capacitance module 24 is used for voltage stabilizing, interference that also can bypass (bypass) AC ripple; After this electric capacity is charged to stable state, just can set up the voltage of voltage regulation Vp25 of stable state at node Np0.And capacitance module 24 can be back in the chip 10 via another corresponding pin of chip 10 at the voltage of voltage regulation Vp25 of node Np0.This voltage of voltage regulation Vp25 can provide on the one hand to the voltage of core circuit 14 as biasing, also can set up a voltage Vs0 at node Np1 via the dividing potential drop of resistance R p0, Rp1 on the one hand.Behind operational amplifier 20 comparison reference voltage Vbg0, the voltage Vs0, just the energy FEEDBACK CONTROL is to driving voltage Vd0 and the drive current Id0 of transistor Qp1.Before chip 10 brought into operation, circuit board 12 can not provide DC voltage Vcc, make chip 10 can not get bias voltage and can not move, and mu balanced circuit 18 also can not move, and made the voltage of node Np0 equal the voltage of low level DC voltage Vss in fact.
The situation of mu balanced circuit 18 operations can be described below.When circuit board 12 will make chip 10 bring into operation, the DC voltage Vcc that can begin high level is provided brought into operation mu balanced circuit 18 to mu balanced circuit 18.This moment, reference voltage generator 22 and operational amplifier 20 brought into operation, by the voltage Vs0 of operational amplifier 20 beginning comparison node Np1 and the reference voltage Vbg0 of reference voltage generator 20 generations.Because before mu balanced circuit 18 brought into operation, node Np0 was maintained low level, voltage Vs0 also is maintained at low level jointly; Therefore when operational amplifier 20 had just brought into operation, operational amplifier 20 can also can be low level voltage because voltage Vs0 makes the driving voltage Vd0 of its output terminal Op0 much smaller than reference voltage Vbg0.At this moment, the voltage between transistor Qp1 emitter-base bandgap grading, base stage also just almost is equivalent to the voltage difference between DC voltage Vcc, Vss.And operational amplifier 20 also can be as a current absorption source (current sink), base stage by transistor Qp1 absorbs suitable drive current Ib0, with driving transistors Qp1, the a large amount of electric current I c0 of conducting is as charging current between its emitter-base bandgap grading, base stage, the high capacity capacitor C p1 charging in capacitance module 24.As is known to the person skilled in the art, because the characteristic of the current drives of two-carrier transistor own, the drive current Ib0 that cooperates operational amplifier 20 to be absorbed by the base stage of transistor Qp1, operational amplifier 20 just can be via relation mutual between bipolar junction transistor emitter current, base current (Ic0=β * Ib0 just; β is the current amplification degree of bipolar junction transistor) drive, oxide-semiconductor control transistors Qp1 is at the electric current I c0 of its emitter-base bandgap grading, inter-collector conducting.
Along with the carrying out of charging process, the voltage of node Np0 can rise gradually, and the voltage Vs0 of node Np1 also can rise gradually; And operational amplifier 20 also will increase the driving voltage Vd0 of its output terminal Op0, and reduces drive current Ib0.The minimizing of the rising of driving voltage Vd0, drive current Ib0 can reduce the voltage between transistor Qp1 emitter-base bandgap grading, base stage, reduces its conducting degree, and the size of current of electric current I c0 is also reduced gradually.Via the detection feedback to voltage Vs0, the size of operational amplifier 20 meeting controlling and driving voltage Vd0 makes the voltage of voltage regulation Vp25 of node Np0 be tending towards the definite value of stable state gradually.When having arrived stable state, operational amplifier 20 can be kept voltage Vs0 and equate with reference voltage Vbg0; In other words, voltage Vp25 also just equals voltage (1+Rp0/Rp1) Vbg0.The voltage Vp25 of this stable state just can be as the Dc bias of core circuit 14; And required electric current I c1 during core circuit 14 operation is also just supplied by transistor Qp1 conducting.When the voltage swing idol of voltage Vp25 changed, operational amplifier 20 controlling and driving voltage Vd0, drive current Ib0 accordingly compensated dynamically.For instance, if core circuit 14 strengthens the electric current demand because of operand, this moment, capacitor C p2 can prevent that the voltage Vp25 of node Np0 from descending suddenly apace, and the voltage Vp25 that slightly falls can make voltage Vs0 descend jointly, driving voltage Vd0 is descended, and make voltage microlitre between transistor Qp1 emitter-base bandgap grading, base stage, increase the electric current I c0 of transistor Qp1 conducting, with the electricity needs that increases in response to core circuit 14.In addition, as previously mentioned, be provided with a testing circuit 26 in the chip 10 and detect whether normally foundation of voltage of voltage regulation V125; In the above-mentioned process of setting up the stable state voltage of voltage regulation, when the voltage of voltage regulation Vp25 of mu balanced circuit 18 is raise gradually by low level, the voltage Vpg0 that testing circuit 26 produces also can be maintained low level, represents the voltage of voltage regulation Vp25 of stable state not set up as yet with digital " 0 "; When voltage of voltage regulation Vp25 rises to a certain predeterminated voltage value near the stable state voltage of voltage regulation by the time (for instance, rise to the stable state voltage of voltage regulation 90%), testing circuit 18 will judge that voltage of voltage regulation Vp25 can stably supply the bias requirement of core circuit 14.This moment, testing circuit 18 will be pulled up to high level with voltage Vpg0, represented the voltage of voltage regulation Vp25 of stable state to be ready for (power-good) with numeral " 1 ".Because output/input circuit 16 and core circuit 14 are wanted the allomeric function of synthetic operation competence exertion chip 10, but output/input circuit 16 can obtain the biasing of DC voltage Vcc earlier, the voltage of voltage regulation Vp25 of core circuit 14 biasing usefulness will could set up a little later; For make both energy synchronous operation, output/input circuit 16 brings into operation just reset (reset) simultaneously after can waiting until that with core circuit 14 testing circuit 26 sends the voltage Vpg0 of numeral " 1 ".
For further specifying the situation of operational amplifier 20 operation during voltage of voltage regulation Vp25 sets up, please continue with reference to figure 2.Fig. 2 is the synoptic diagram of operational amplifier 20 circuit among Fig. 1.Operational amplifier 20 is offset between DC voltage Vcc and Vss, and is provided with n type MOS transistor M1 to M8, p type MOS transistor M9 to 14, to form an amplifying circuit 29 and a driving stage 28 as AB class (class AB) output stage.Wherein transistor M8, M14 form driving stage 28, and all the other each transistors then form amplifying circuit 29; The volume (body) of each n type MOS transistor M1 to M8 is offset to DC voltage Vss, and the body (body) of each p type MOS transistor M9 to M14 then is offset to DC voltage Vcc.It is one differential to (differential pair) that transistor M1, M2 form, and the grid of two transistor just forms input end Inp0, the Inn0 of differential amplifier 20 respectively.Transistor M3 is electrically connected mutually to the grid of M6, forms a current mirror; 27 of support circuits can provide an electric current I r0 as a reference current, provide current bias to amplifying circuit 29 by this current mirror.For instance, the transistor M4 that is electrically connected to node Np3 is promptly as a current source, with bias transistor M1, M2 form differential right.In gross, transistor M1, M2, M9, M10 are as a differential input level, and its output signal is made the buffering of driving stage via transistor M7, M3, M12, M13.Amplifying circuit 29 can be distinguished the gate bias of transistor M8, M14 in the controlling and driving level 28 in the output voltage of node Np5, Np6, and the node Np4 of driving stage 28 just can be used as the output terminal Op0 (please also refer to Fig. 1) of operational amplifier 20.
As previously mentioned, at the beginning of known mu balanced circuit 18 brings into operation, can draw suitable drive current Ib0 to the base stage of transistor Qp1, with the charging current Ic0 (as Fig. 1) of the big electric current of driving transistors Qp1 conducting.And, can further understand the state that known operational amplifier 20 moves in this case by the circuit diagram of operational amplifier among Fig. 2 20.At the beginning of mu balanced circuit 18 brings into operation, the voltage of voltage regulation Vp25 of node Np0 (as Fig. 1) is near low level DC voltage Vss, the voltage Vs0 that node Np1 dividing potential drop is come out also is low level voltage, and the voltage in operational amplifier 20 input end Inp0 also is low level jointly.Compared to the higher reference voltage Vbg0 of input end Inn0 (representative value is between 1 to 2 volt), the low level voltage of input end Inp0 can make transistor M1 almost completely turn-off (as Fig. 2), the bias current major part that transistor M4 provides is by transistor M2 conducting, make transistor M7 grid voltage be pulled up to the DC voltage Vcc of high level, be pulled up to high level in voltage jointly node Np5, Np6.This also makes transistor M14 turn-off, and makes transistor M8 present the state of high conducting, the electric current I d0 that conducting is suitable; The electric current I d0 of this conducting is the drive current Ib0 that the base stage of transistor Qp1 extracted by input end Op of operational amplifier 20 just.And this drive current Ib0 will the high electric current of driving transistors Qp1 conducting charging current Ic0.In other words, the base stage of transistor Qp1 can be considered a control end, and node Np4 can be considered a Control Node; The driven situation of transistor Qp1 is by the drive current Ib0 decision that flows into node Np4, and the conducting situation of transistor M8 between drain electrode, source electrode itself controlled the size of current that is flowed out by node Np4, and then controlled the size of the charging current Ic0 of transistor Qp1 conducting.
The core circuit 14 though the voltage of voltage regulation Vp25 that known mu balanced circuit 18 can produce stable state among Fig. 1 setovers, but one of shortcoming of known technology, be exactly that mu balanced circuit 18 can be at the excessive driving transistors Qp1 of initial stage that moves at the beginning, make the great electric current of transistor Qp1 conducting, cause transistor Qp1 to be burnt easily.As previously mentioned, when mu balanced circuit 18 has just brought into operation because the voltage of node Np0 is low level, jointly operational amplifier 20 in the driving voltage Vd0 of output terminal Op0 also near low level; So voltage difference between DC voltage Vcc, Vss no better than just of the voltage between transistor Qp1 emitter-base bandgap grading, base stage; And the n type MOS transistor M8 of operational amplifier 20 in driving stage 28 also can the suitable drive current Ib0 of conducting, the high electric current I c0 of driving transistors Qp1 conducting.With aforesaid exemplary, the voltage difference between DC voltage Vcc, Vss has 3.3 volts; And under general situation, as long as the voltage between transistor Qp1 emitter-base bandgap grading, base stage has 0.7 to 0.8 volt, just can the suitable electric current of conducting.In comparison, steady-state circuit 18 significantly surmounts the electric current of transistor Qp1 required conducting under the operate as normal situation in fact at the electric current of the first conducting of operation as can be known.And so big electric current very easily just burns transistor Qp1 known mu balanced circuit 18 the first of operation.In case transistor Qp1 burns, mu balanced circuit 18 just can't normally move certainly with generation voltage of voltage regulation Vp25, and chip 10 also just can't obtain biasing, causes whole microcontroller paralysis.
Summary of the invention
Therefore, fundamental purpose of the present invention, being to provide a kind of provides auxiliary current to reduce mu balanced circuit and the corresponding control methods of operational amplifier to the drive current of bipolar junction transistor base stage in initial operating stage with a current mirror, to avoid the shortcoming of known technology.
In known technology, known mu balanced circuit can be according to the transistor in the still low voltage of voltage regulation conducting operational amplifier driving stage of magnitude of voltage when just bringing into operation, make the known operational amplifier can be by drawing bigger driving direct current in the bipolar junction transistor, thus, bipolar junction transistor will excessively be driven, burnt because of the charging current that conducting is excessive, setover core circuit in the chip of voltage of voltage regulation can't normally be provided.
In the present invention, mu balanced circuit of the present invention can provide an extra auxiliary current with an extra current mirror when just bringing into operation, even the operational amplifier among the present invention can be according to the transistor in the still low voltage of voltage regulation conducting driving stage of magnitude of voltage, but auxiliary electrical fails to be convened for lack of a quorum and injects the transistor of this conducting, make the drive current that operational amplifier reality is drawn in bipolar junction transistor among the present invention effectively to reduce, just can excessively not drive bipolar junction transistor thus, and can provide correct, stable bias voltage chip.
Description of drawings
Fig. 1 is the function block schematic diagram of a known mu balanced circuit structure on a chip and a circuit board.
Fig. 2 is the circuit diagram of operational amplifier among Fig. 1.
Fig. 3 is the function block schematic diagram of mu balanced circuit structure of the present invention on a chip and a circuit board.
Fig. 4 is the circuit diagram of operational amplifier among Fig. 3.
Fig. 5 is the synoptic diagram of each coherent signal waveform sequential when mu balanced circuit moves among Fig. 3.
The reference numeral explanation
10,30 chips, 12,32 circuit boards
14,34 core circuits, 16,36 output/input circuits
18,38 mu balanced circuits, 20,40 operational amplifiers
22,42 reference voltage generators, 24,46 capacitance modules
26,45 testing circuits, 27,47 support circuits
28,48 driving circuits, 29,49 amplifying circuits
50 current mirrors, 54 rejection gates
56 phase inverter Vcc, Vss DC voltage
Ic0, Ic do not have electric current Vbg0, Vbg reference voltage
Vop2 dotted line waveform t0, t1, tp time point
Vp25, V25 voltage of voltage regulation V25Pg, V25s voltage level
Op0, Op output terminal Vs0, Vpg0, Vs, Vpg voltage
Rp0-Rp2, R1-R2 resistance Cp1, C1 electric capacity
Np0-Np6, N0-N7 node vd0, Vd driving voltage
Inn0, Inp0, Inn, Inp input end
Qp1-Qp2, Q1-Q2, M1-M14, T1-T17, S1-S3 transistor
Ic1, Ir0, Ib0, Ib, Id0, Ir, Im, Im0, Id electric current
Embodiment
Please refer to Fig. 3.Fig. 3 is formed in the function block schematic diagram of 32 of a chip 30 and circuit boards for mu balanced circuit 38 of the present invention.Based on the configuration of modern microcontroller, also be provided with core circuit 34 and output/input circuit 36 in the chip 30; Core circuit 34 is offset to lower voltage of voltage regulation V25, is used for carrying out signal Processing and data operation; Output/input circuit 36 and circuit board 32 are the same to use higher DC voltage Vcc to setover, and is used for transmitting data, the signal of core circuit 34,32 exchanges of circuit board; The zero voltage reference that Dc bias Vss then holds with can be considered.In order to produce core circuit 34 employed voltage of voltage regulation V25, the present invention also is provided with a mu balanced circuit 38 between chip 30 and circuit board 32, set up voltage of voltage regulation V25 with the Dc bias Vcc that provides according to circuit board 32.Mu balanced circuit 38 of the present invention is offset between DC voltage Vcc, the Vss (for instance, DC voltage Vcc can be 3.3 volts a voltage, corresponding DC voltage Vss then is 0 volt a voltage reference), it has comprised reference voltage generator 42, the operational amplifier 40 that is arranged in the chip 30, resistance R 0, the R1 that is used for dividing potential drop; Cooperate foregoing circuit, also be provided with a pnp type bipolar junction transistor Q1 and a capacitance module 46 on the circuit board 32 as a charging circuit.Reference voltage generator 42 is used for producing a reference voltage Vbg.40 of operational amplifiers are provided with two differential positive-negative input end Inp, Inn and output terminal Op; Wherein input end Inn promptly is used for accepting reference voltage Vbg, and input end Inp then is electrically connected to node N1.When operational amplifier 40 operation, can be worse than output terminal Op according to the voltage of two input end Inp, Inn and export a corresponding driving voltage Vd and a drive current Ib, with as drive signal transistor Q1.Transistor Q1 is as a charging circuit, its base stage is subjected to the biasing control (on the chip 30 pin can be set so that output terminal Op can outwards be electrically connected to the base stage of transistor Q1) of driving voltage Vd, the drive current Ib of operational amplifier 40 outputs, emitter-base bandgap grading is offset to DC voltage Vcc, and collector then is electrically connected to node N0; According to the control of drive current Ib, transistor Q1 can provide a charging current Ic to inject node N0 according to the drive characteristic of bipolar junction transistor.Be provided with the capacitor C 1 and a resistance R 2 of high capacity in the capacitance module 46; Capacitor C 1 is mainly used to voltage stabilizing, but and the unnecessary interchange of bypass disturb, make the voltage of node N0 be maintained at a stationary value easily; Utilize capacitance module 46 to be used as load, mu balanced circuit 38 can be set up voltage of voltage regulation V25 at node N0.Node N0 can be electrically connected to the node N2 in the chip 30 by another pin on the chip 38, and the voltage of voltage regulation V25 of node N0 is back to core circuit 34, with biasing core circuit 34; Resistance R 0, R1 also can divide extrusion a voltage Vs at node N1 according to voltage of voltage regulation V25 simultaneously, make voltage Vs equal (R1/ (R1+R2)) V25, and voltage Vs are transferred to the input end Inp of operational amplifier 40.N type MOS transistor Q2 then is electrically connected between node N0 and the DC voltage Vss, and its grid is subjected to the control of voltage Vreg.In addition, also be provided with a testing circuit 45 in the chip 30, whether the voltage of voltage regulation V25 that is used for detecting stable state sets up, and sends voltage Vpg as a detection signal according to testing result accordingly.Before voltage of voltage regulation V25 did not also raise, the voltage Vpg that testing circuit 45 sends can be maintained at low level; Deng voltage of voltage regulation V25 be increased to a certain preset value (as the stable state voltage of voltage regulation 90%) after, voltage Vpg will change into high level, represents voltage of voltage regulation V25 can begin to provide stable state to setover to core circuit 34.
In one embodiment of the invention, the operational amplifier 40 among the present invention can switch on different operator schemes according to the voltage Vpg that testing circuit 45 sends in addition.Fig. 4 is the synoptic diagram of operational amplifier 40 circuit of the present invention.Be provided with amplifying circuit 49, driving stage 48 and an extra current mirror 50 in the operational amplifier 40.Be provided with n type MOS transistor T1 to T7, p type MOS transistor T9 to T13 in the amplifying circuit 49; Be provided with n type MOS transistor T8 and p type MOS transistor T14 in the driving stage 48; Then be provided with n type MOS transistor T15, p type MOS transistor T16, T17 in the current mirror 50; N type MOS transistor S1, S2 and p type MOS transistor S3 are then as switching transistor, grid is controlled by the biasing of rejection gate 54, phase inverter 56 output voltage V d1b, Vd1 respectively, the operation that comes Control current mirror 50 with the voltage Vpg of foundation testing circuit 45 (and another control voltage Vop).Wherein the body utmost point of each p type MOS transistor is offset to DC voltage Vcc, and the body utmost point of each n type MOS transistor is offset to DC voltage Vss, and rejection gate 54, phase inverter 56 also are offset between DC voltage Vcc, the Vss.
In the amplifying circuit 49, it is one differential right that transistor T 1, T2 form, and the grid of two transistor is respectively as input end Inp, the Inn of operational amplifier 40.Transistor T 9, T10 can be considered the active load of transistor T 1, T2.The grid of transistor T 3 to T6 also is electrically connected mutually, forms another current mirror; The electric current I r that transistor T 6 can provide according to support circuits 47 controls the electric current of each transistor turns in this current mirror as reference current; The transistor T 4 that is electrically connected to node N3 promptly provides differential right bias current as a current source.In gross, transistor T 1, T2, T9, T10 form a differential input level, and its signal is done the buffering of driving stage again through transistor T 7, T3, T12 to T13, export driving stage 48 in node N5, N6.Transistor T 8 in the driving stage 48, T14 form an AB class (class AB) output stage, respectively at the grid receiving node N5 of two transistor, the signal of N6, and with the output terminal Op of node N4 as operational amplifier 40, the signal after the final amplification of output.
In the invention provides current mirror 50, wherein the grid of transistor T 15 is electrically connected to node N5 jointly by the grid of transistor T 8 in transistor S2 and the driving stage 48; The grid of transistor T 16, T17 also is electrically connected to node N7 jointly.By finding out among Fig. 4, when the voltage Vd1b of rejection gate 54 is that high level (voltage level of DC voltage Vcc) and voltage Vd1 are when being low level (voltage level of DC voltage Vss), transistor S3, S1 as switch all turn-off not conducting, transistor S2 then can turn-on transistor T8, the electrical connection between the T15 grid, make transistor T 8, T15, T16 and T17 form a current mirror, and transistor T 15 is understood according to the electric current I d of transistor T 8 conductings conducting one electric current I m0; By the configuration of transistor T 16, T17 grid mutual coupling, transistor T 17 also can inject node N4 according to the situation conducting one electric current I m of transistor T 16 conductings; And when operational amplifier 40 was drawn drive current Ib by the base stage (please in the lump with reference to figure 3) of transistor Q1, drive current Ib also can flow into node N4 with electric current I m.When the voltage Vd1b of rejection gate 54 transfers low level to and when making voltage Vd1 transfer high level to, transistor S3, S1 can conductings, and transistor S2 can turn-off.The transistor S2 that turn-offs makes the grid of transistor T 15 no longer be subjected to the Control of Voltage of node N5, but the transistor S1 that is switched on is electrically connected to low level DC voltage Vss, makes transistor T 15 turn-off not conducting.In like manner, transistor T 16, T17 are drawn high to the high level of DC voltage Vcc in the transistor S3 that the grid bias of node N7 also can be switched on, and make transistor T 16, T17 all turn-off not conducting, and transistor T 17 also just can not inject node N4 by conducting electric current I m.As seen from the above description, by voltage Vpg, Vop voltage Vd1b (and Vd1), just can whether to provide electric current I m to be injected into node N4 according to the situation of transistor T 8 conductings by Control current mirror 50 via rejection gate 54 outputs.
Please refer to Fig. 5 (and in the lump with reference to figure 3, Fig. 4).Fig. 5 is the synoptic diagram of each coherent signal waveform sequential when mu balanced circuit 38 of the present invention moves among Fig. 3.Solid line waveform from top to bottom among Fig. 5 is represented voltage Vpg, voltage Vd1 and the Vd1b (see figure 4) of voltage of voltage regulation V25, voltage Vop, testing circuit 45 respectively, and the transverse axis of each waveform is the time, and the longitudinal axis is a voltage swing.Below just will cooperate Fig. 3, Fig. 4 that the situation of principle of the present invention and enforcement is described with Fig. 5.Suppose that circuit board 32 will bring into operation chip 30 at time point t0, circuit board 32 will begin to supply DC voltage Vcc at time point t0.When time point t0, each capacitor C 1 in the charging module 46 is store charge not also, and the voltage that makes node N2 is near low level (voltage level of DC voltage Vss), and the voltage Vs of node N1 also is a low level voltage jointly.At the same time, reference voltage generator 42 produces reference voltage Vbg (representative value is between 1 to 2 volt) immediately after the biasing that obtains DC voltage Vcc.Therefore, in operational amplifier 40, transistor T 2 (see figure 4)s can because the bias voltage (reference voltage Vbg just) of its grid greater than the grid bias (voltage Vs) of transistor T 1, make the bias current of transistor T 4 conductings almost entirely by transistor T 2 conductings, and make the transistor T 14 in the driving stage 48 be close to shutoff jointly, 8 complete conductings of transistor T absorb suitable electric current I d by node N4.
In the embodiment of Fig. 5, voltage Vop can be maintained at low level always in the present invention, and when time point t0, because voltage of voltage regulation V25 not rising as yet, so testing circuit 45 is used for reflecting that the voltage Vpg of testing result also can keep low level.Via the computing of rejection gate 54 (see figure 4)s, can make voltage Vd1b is high level, and voltage Vd1 then is a low level jointly, and current mirror 50 is brought into operation, and is injected into node N4 according to the electric current I d conducting electric current I m of transistor T 8 conductings.Note that the electric current I d that flows into node N4 this moment will equal drive current Ib and Im and.In other words and since current mirror 50 conductings electric current I m as auxiliary current, inject node N4 with the drive current Ib of transistor Q1 base stage, the size of drive current Ib will essence less than the size of electric current I d.Because the drive current Ib that operational amplifier 40 is drawn by transistor Q1 (see figure 3) base stage diminishes, the excessive excessive charging current Ic of driving transistors Q1 conducting not just.Before when being discussed, known technology can mention, because at the beginning of mu balanced circuit brings into operation, n type MOS transistor M8 (Fig. 2) in the driving stage has sizable conducting degree, and known operational amplifier 20 not current mirror auxiliary current is provided, so in fact known operational amplifier 20 is exactly drive current Ib0 in the electric current I d0 of transistor M8 conducting; The drive current Ib0 of this big electric current can excessively drive bipolar junction transistor Qp1, causes transistor Qp1 to be burnt.In comparison, because operational amplifier 40 of the present invention provides current mirror 50 to produce auxiliary current Im, even the transistor T 8 in the driving stage 48 has higher conducting degree, drive current Ib also can not be equal to the size of electric current I d, but can be less than the size of electric current I d.If the base stage of transistor Q1 is considered as a control end, node N4 is considered as a Control Node, even the conducting degree of transistor T 8 meeting Control Node N4 flows out the size of electric current, but because drive current Ib and electric current I m flow into node N4 all equally, operational amplifier 40 will reduce to the drive current Ib that transistor Q1 absorbs.Thus, the bipolar junction transistor Q1 in the mu balanced circuit 38 of the present invention just can excessively not driven, and has normally moved in the subsequent process that just can set up, keep at voltage of voltage regulation yet.
As shown in Figure 5, under the driving of drive current Id, transistor Q1 can provide charging current Ic to come to 1 charging of the capacitor C in the capacitance module 46 the voltage of voltage regulation V25 of node N0 to be risen gradually.Between the voltage of voltage regulation V25 rising stage, the driving voltage Vd of operational amplifier 40 output terminal Op also can rise thereupon.As previously mentioned, by the time voltage of voltage regulation V25 time point t1 rise to a default voltage level V25Pg (as the stable state voltage of voltage regulation 90%) after, testing circuit 45 (Fig. 3) will be increased to high level by low level with voltage VPg, begins to reset also coordinated operation with notice output/input circuit 36 and core circuit 34.Simultaneously, because the change of voltage Vpg, voltage Vd1b, Vd1 also change jointly, make current mirror 50 (Fig. 4) stop to provide electric current I m to node N4; After this will come dynamically to adjust driving condition with the cooperation of amplifying circuit 49, driving stage 48 in the operational amplifier 40 to transistor Q1 (Fig. 3) according to the feedback of voltage Vs, finally make voltage Vs be locked in the voltage swing of reference voltage Vbg, make voltage of voltage regulation V25 reach the definite value of stable state, and be maintained at the voltage level V25s of stable state, such as among Fig. 5 sign.This steady state voltage level V25s also just equals voltage (1+R0/R1) Vbg.
In addition, by the circuit among Fig. 4 as can be known,, also can come the operation of Control current mirror 50 with voltage Vop except whether the voltage Vpg Control current mirror 50 with testing circuit 45 provides the auxiliary current Im.For instance, if the waveform of voltage Vop is shown in the dotted line waveform Vop2 among Fig. 5, be to change low level into by high level at time point tp, then current mirror 50 can just can provide auxiliary current Im between time point tp, t1; Between time point t0, tp or after the time point t1, current mirror 50 neither can operations can not provide auxiliary current Im yet.In addition, the testing circuit 45 in Fig. 3, the time of available another electric capacity charging judges that it is the opportunity (being the time point t1 among Fig. 5) of high level that its voltage Vpg is raise by low level.For instance, an one normalized current source and a standard capacitance (or RC circuit of electric capacity-resistance) can be set in the testing circuit 45, after mu balanced circuit 38 is brought into operation by time point t0, normalized current source in the testing circuit 45 also begins to charge to standard capacitance (RC circuit), by the time the voltage of standard capacitance (RC circuit) is increased to a preset value, and testing circuit 45 just can be increased to high level by low level with voltage Vpg.In other words, the capacitance of the size of current of design standards current source and standard capacitance (or the resistance value in the RC circuit, capacitance) suitably, the situation that voltage of voltage regulation V25 voltage raises just can " be simulated ", be estimated to testing circuit 45, make when voltage of voltage regulation V25 is increased to high voltage level V25Pg by the low level of time point t0 (asking for an interview Fig. 5), the voltage of standard capacitance also rises to preset value in the testing circuit 45, at time point t1 detection trigger circuit 45 voltage Vpg is increased to high level by low level just.
In summary, the n type MOS transistor of driving stage in can be at the beginning of the bringing into operation a large amount of conducting operational amplifiers of known mu balanced circuit, make known operational amplifier also can absorb suitable drive current to bipolar junction transistor by its output terminal, cause bipolar junction transistor to burn, and the core circuit of known mu balanced circuit in also just can't the normal bias chip.In comparison, mu balanced circuit of the present invention can provide auxiliary current with the extra current mirror in the operational amplifier at the beginning of bringing into operation, even the n type MOS transistor in the driving stage has suitable conducting degree, operational amplifier can not absorb excessive drive current to bipolar junction transistor yet, prevents that bipolar junction transistor from just being burnt at the beginning of voltage of voltage regulation is set up.By the time after the voltage of voltage regulation of stable state is set up, operational amplifier of the present invention just can stop to provide auxiliary current, only keep driven to bipolar junction transistor with amplifying circuit, driving stage, stable voltage of voltage regulation V25 is provided setover core circuit in the chip, keeps the normal operation of chip.
The above only is preferred embodiment of the present invention, and all equivalences of making according to claims of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (10)
1. a mu balanced circuit is used to provide a voltage of voltage regulation, and this mu balanced circuit includes:
One charging circuit, it has a control end, its conducting one drive current; This charging circuit can produce a charging current according to this drive current;
One capacitance module is electrically connected to this charging circuit, and the electric charge that provides by this charging current is to set up this voltage of voltage regulation accordingly;
One drive circuit is electrically connected to this charging circuit, is used for controlling the size of current of the electric current that is flowed out by this Control Node; And
One current mirror is electrically connected to this control end, is used for producing the auxiliary current of this Control Node of inflow;
Wherein after this charging circuit began to produce this charging current, when the voltage swing of this voltage of voltage regulation met a predeterminated voltage scope, this current mirror can produce this auxiliary current, drew super-high-current to avoid this charging circuit moment; If the voltage swing of this voltage of voltage regulation has exceeded this predeterminated voltage scope, this current mirror can stop to produce this auxiliary current.
2. mu balanced circuit as claimed in claim 1, wherein when this drive current increase, this charging circuit can increase this charging current accordingly; And the electric current that is flowed out by this Control Node when the control of this driving circuit is when being certain value, if this auxiliary current increases, then this drive current can reduce.
3. mu balanced circuit as claimed in claim 1, it includes an amplifying circuit in addition, is used for producing an output voltage; And this driving circuit is the electric current that is flowed out by this Control Node according to the size control of this output voltage.
4. mu balanced circuit as claimed in claim 3, wherein this amplifying circuit is the output voltage that produces correspondence according to the size of this voltage of voltage regulation.
5. mu balanced circuit as claimed in claim 3, wherein this amplifying circuit is to produce corresponding output voltage according to this voltage of voltage regulation with voltage difference between a reference voltage.
6. mu balanced circuit as claimed in claim 3, wherein this current mirror can be adjusted the size of this auxiliary current according to the size of this output voltage.
7. mu balanced circuit as claimed in claim 1, it includes a testing circuit in addition, and whether the voltage swing that is used for detecting this voltage of voltage regulation meets this preset range; When this voltage of voltage regulation exceeds this preset range, this mu balanced circuit can send the detection signal of a correspondence, and this current mirror can stop to provide this auxiliary current after receiving this detection signal.
8. mu balanced circuit as claimed in claim 1, it is to be used for providing this voltage of voltage regulation to a chip; This chip is to be arranged on the circuit board; Wherein this driving circuit and this current mirror are to be located in this chip, and this charging circuit and this capacitance module are to be arranged on this circuit board.
9. one kind is used for one and has the method for the mu balanced circuit of a control end, is used for controlling this mu balanced circuit so that a voltage of voltage regulation to be provided, and wherein one of output buffer output couples this mu balanced circuit in this control end, and this method includes:
In an initial time, utilize an auxiliary current mirror to produce an auxiliary current, reduce electric current through this mu balanced circuit; And
Behind this initial time, forbid that this auxiliary current mirror is to stop to produce this auxiliary current.
10. method as claimed in claim 9, wherein this mu balanced circuit includes an amplifying circuit in addition, is used for producing an output voltage; And this method includes in addition: the electric current of controlling this control end according to the size of this output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03106875 CN1208702C (en) | 2003-03-06 | 2003-03-06 | Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03106875 CN1208702C (en) | 2003-03-06 | 2003-03-06 | Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1432885A true CN1432885A (en) | 2003-07-30 |
| CN1208702C CN1208702C (en) | 2005-06-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03106875 Expired - Lifetime CN1208702C (en) | 2003-03-06 | 2003-03-06 | Voltage stabilizing circuit with current mirror to compensate current and prevent initial overcurrent and its contol method |
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| Country | Link |
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| CN (1) | CN1208702C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100367142C (en) * | 2003-10-21 | 2008-02-06 | 联发科技股份有限公司 | Low-noise stablized voltage circuit capable of fast stopping working |
| CN103176494A (en) * | 2011-12-23 | 2013-06-26 | 联芯科技有限公司 | Voltage-controlled zero compensating circuit |
| CN105278601A (en) * | 2014-07-21 | 2016-01-27 | 联咏科技股份有限公司 | Current source used for voltage stabilizers and voltage stabilizers |
| US9494959B2 (en) | 2014-07-11 | 2016-11-15 | Novatek Microelectronics Corp. | Current source for voltage regulator and voltage regulator thereof |
| CN109407745A (en) * | 2017-08-17 | 2019-03-01 | 力晶科技股份有限公司 | Voltage stabilization output device |
| CN114460993A (en) * | 2020-11-09 | 2022-05-10 | 扬智科技股份有限公司 | Voltage regulator |
-
2003
- 2003-03-06 CN CN 03106875 patent/CN1208702C/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100367142C (en) * | 2003-10-21 | 2008-02-06 | 联发科技股份有限公司 | Low-noise stablized voltage circuit capable of fast stopping working |
| CN103176494A (en) * | 2011-12-23 | 2013-06-26 | 联芯科技有限公司 | Voltage-controlled zero compensating circuit |
| US9494959B2 (en) | 2014-07-11 | 2016-11-15 | Novatek Microelectronics Corp. | Current source for voltage regulator and voltage regulator thereof |
| CN105278601A (en) * | 2014-07-21 | 2016-01-27 | 联咏科技股份有限公司 | Current source used for voltage stabilizers and voltage stabilizers |
| CN109407745A (en) * | 2017-08-17 | 2019-03-01 | 力晶科技股份有限公司 | Voltage stabilization output device |
| CN114460993A (en) * | 2020-11-09 | 2022-05-10 | 扬智科技股份有限公司 | Voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1208702C (en) | 2005-06-29 |
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