CN216599552U - Transient thermal compensation bias circuit of power amplifier - Google Patents
Transient thermal compensation bias circuit of power amplifier Download PDFInfo
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- CN216599552U CN216599552U CN202123026918.8U CN202123026918U CN216599552U CN 216599552 U CN216599552 U CN 216599552U CN 202123026918 U CN202123026918 U CN 202123026918U CN 216599552 U CN216599552 U CN 216599552U
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Abstract
The utility model belongs to the field of integrated circuits, and discloses a transient thermal compensation bias circuit of a power amplifier, which comprises: the system comprises a power input port, a power output port, a first logic control interface, a second logic control interface, a first switch module, a second switch module, a third switch module, a first bias module, a second bias module, a low-pass delay module and a main driving module; the low-pass delay module comprises a capacitor, the logic polarity of the first logic control interface is opposite to that of the second logic control interface, and when the first logic control interface is at a low level, the capacitor in the low-pass delay module follows the voltage of the first port of the first switch module. Has the beneficial effects that: the voltage of the voltage output port is the same as the voltage of the capacitor of the low-pass delay module, and when the level of the first logic control interface module changes from high level to low level, the voltage of the voltage output port follows the voltage change of the capacitor in the low-pass delay module, so that the thermal response of the amplifier is compensated.
Description
Technical Field
The utility model relates to the field of integrated circuits, in particular to a transient thermal compensation bias circuit of a power amplifier.
Background
Since the Power Amplifier generates heat more, a certain time is required from the start of the chip to thermal stabilization, and this time often affects the response speed of the system and consumes redundant Power consumption, so the thermal response of the chip often needs to be compensated.
The existing solution needs to add an additional CMOS control chip, which not only increases the packaging cost and increases the packaging risk, but also fails to meet the small-size packaging requirement.
SUMMERY OF THE UTILITY MODEL
The purpose of the utility model is: the existing power amplifier thermal compensation device is improved, the realization of the chip thermal compensation function is ensured, the packaging risk is reduced, and the small-size packaging requirement is met.
In order to achieve the above object, the present invention provides a transient thermal compensation bias circuit for a power amplifier, comprising: the system comprises a power input port, a power output port, a first logic control interface, a second logic control interface, a first switch module, a second switch module, a third switch module, a first bias module, a second bias module, a low-pass delay module and a main driving module;
the first logic control interface is connected with a first port of a first switch module, a second port of the first switch module is connected with a first port of a first bias module, a second port of the first bias module is connected with a power input port, a first port of the first bias module is connected with a first port of a low-pass delay module, a second port of the low-pass delay module is connected with a first port of a main drive module, a second port of the main drive module is connected with the power input port, a third port of the main drive module is connected with a first port of a third switch module, a second port of the third switch module is connected with a power output port, and a third port of the third switch module is connected with a second logic control interface;
the first logic control interface is connected with a first port of a second switch module, a second port of the second switch module is connected with a first port of a second bias module, a second port of the second bias module is connected with a power supply input port, and a first port of the second bias module is connected with a third port of the low-pass delay module;
the low-pass delay module comprises a capacitor, the logic polarities of the first logic control interface and the second logic control interface are opposite, when the first logic control interface is at a high level, the first switch module and the second switch module are in a conducting state, the third switch module is in a turn-off state, and the voltages of the second port of the first switch module, the second port of the second switch module, the third port of the low-pass delay module and the first port of the third switch module are zero; when the first logic control interface is at a low level, the first switch module and the second switch module are in an off state, the third switch module is in an on state, and the capacitor voltage in the low-pass delay module changes along with the voltage change of the first port of the first switch module.
Further, the first biasing module includes: a first resistor, a first transistor, a second transistor, and a third transistor; a first port of the first resistor is connected with the power supply input port, a second port of the first resistor is connected with a first end of the first transistor, a first end of the first transistor is connected with a second end of the first transistor, a third end of the first transistor is connected with a first end of the second transistor, a first end of the second transistor is connected with a second end of the second transistor, a third end of the second transistor is connected with a first end of the third transistor, a first end of the third transistor is connected with a second end of the third transistor, and a third end of the third transistor is grounded; the second port of the first resistor is connected with the second port of the first switch module, and the second port of the first resistor is connected with the first port of the low-pass delay module.
Further, the first transistor, the second transistor and the third transistor are all HBT transistors or all FET transistors.
Further, the second biasing module includes: a second resistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first port of the second resistor is connected with the power supply input port, the second port of the second resistor is connected with the first end of the fourth transistor, the first end of the fourth transistor is connected with the second end of the fourth transistor, the third end of the fourth transistor is connected with the first end of the fifth transistor, the first end of the fifth transistor is connected with the second end of the fifth transistor, the third end of the fifth transistor is connected with the first end of the sixth transistor, the first end of the sixth transistor is connected with the second end of the sixth transistor, and the third end of the sixth transistor is grounded; and the second port of the second resistor is connected with the second port of the second switch module, and the second port of the second resistor is connected with the third port of the low-pass delay module.
Further, the fourth transistor, the fifth transistor and the sixth transistor are all HBT transistors or all FET transistors.
Further, the low-pass delay module includes: a third resistor, a first capacitor and a second capacitor; the first port of the third resistor is connected with the first port of the second bias module, the second port of the third resistor is connected with the first port of the first capacitor, the second port of the first capacitor is connected with the first port of the first bias module, the second port of the third resistor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, and the second port of the third resistor is connected with the first port of the main drive module.
Further, the main driving module includes a seventh transistor, a second terminal of the seventh transistor is connected to the second port of the low-pass delay module, a first terminal of the seventh transistor is connected to the power input port, and a third terminal of the seventh transistor is connected to the first port of the third switching module.
Furthermore, the third switch module includes a fourth resistor and an eighth transistor, a first end of the eighth transistor is connected to the third port of the main driving module, a second end of the eighth transistor is connected to the first port of the fourth resistor, a second port of the fourth resistor is connected to the second logic control interface, and a third end of the eighth transistor is connected to the power output port.
Further, the first switch module includes a fifth resistor and a ninth transistor, a first port of the fifth resistor is connected to the first logic control interface, a second port of the fifth resistor is connected to a second terminal of the ninth transistor, a first terminal of the ninth transistor is connected to the first port of the first bias module, and a third terminal of the ninth transistor is grounded.
Further, the second switch module includes a sixth resistor and a tenth transistor, a first port of the sixth resistor is connected to the first logic control interface, a second port of the sixth resistor is connected to a second terminal of the tenth transistor, a first terminal of the tenth transistor is connected to the first port of the second bias module, and a third terminal of the tenth transistor is grounded.
Compared with the prior art, the transient thermal compensation bias circuit of the power amplifier has the beneficial effects that: the voltage of the voltage output port is the same as the voltage of the capacitor of the low-pass delay module, and when the level of the first logic control interface module changes from high level to low level, the voltage of the voltage output port follows the voltage change of the capacitor in the low-pass delay module, so that the thermal response compensation of the amplifier is realized.
Drawings
FIG. 1 is a block diagram of a power amplifier transient thermal compensation bias circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a transient thermal compensation bias circuit for a power amplifier according to the present invention;
fig. 3 is a schematic diagram illustrating the operation of the transient human offset circuit of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the utility model but are not intended to limit the scope of the utility model.
As shown in fig. 1, a transient thermal compensation bias circuit for a power amplifier includes: the system comprises a power input port, a power output port, a first logic control interface, a second logic control interface, a first switch module, a second switch module, a third switch module, a first bias module, a second bias module, a low-pass delay module and a main driving module;
the first logic control interface is connected with a first port of a first switch module, a second port of the first switch module is connected with a first port of a first bias module, a second port of the first bias module is connected with a power input port, a first port of the first bias module is connected with a first port of a low-pass delay module, a second port of the low-pass delay module is connected with a first port of a main drive module, a second port of the main drive module is connected with the power input port, a third port of the main drive module is connected with a first port of a third switch module, a second port of the third switch module is connected with a power output port, and a third port of the third switch module is connected with a second logic control interface;
the first logic control interface is connected with a first port of the second switch module, a second port of the second switch module is connected with a first port of the second bias module, a second port of the second bias module is connected with the power input port, and a first port of the second bias module is connected with a third port of the low-pass delay module.
In this embodiment, the low-pass delay module includes a capacitor, the first logic control interface and the second logic control interface have opposite logic polarities, when the first logic control interface is at a high level, the first switch module and the second switch module are in an on state, the third switch module is in an off state, and voltages of the second port of the first switch module, the second port of the second switch module, the third port of the low-pass delay module, and the first port of the third switch module are zero; when the first logic control interface is at a low level, the first switch module and the second switch module are in an off state, the third switch module is in an on state, and the capacitor voltage in the low-pass delay module changes along with the voltage change of the first port of the first switch module.
In this embodiment, the logic polarities of the first logic control interface and the second logic control interface are opposite, when the first logic control interface is at a high level, the second logic control interface is at a low level, and when the first logic control interface is at a low level, the second logic control interface is at a high level.
When the first logic control interface is at a low level, the first switch module and the second switch module are in an off state, the third switch module is in an on state, at the moment, the voltage of the second port of the first switch module and the voltage of the second port of the second switch module are quickly established, the voltage of the capacitor of the low-pass delay module cannot change suddenly, the voltage of the capacitor follows the voltage of the first port of the first switch module, and the voltage of the second port of the second switch module charges the capacitor through the third resistor to change the voltage of the capacitor. The voltage of the capacitor is slowly changed, transmitted to the third switch module through the main driving module and finally transmitted to the power output port through the third switch module. The voltage of the power output port is consistent with the voltage of the capacitor of the low-pass delay module, and the thermal response of the amplifier is compensated.
In this embodiment, the first bias module includes: a first resistor, a first transistor, a second transistor, and a third transistor; a first port of the first resistor is connected with the power supply input port, a second port of the first resistor is connected with a first end of the first transistor, a first end of the first transistor is connected with a second end of the first transistor, a third end of the first transistor is connected with a first end of the second transistor, a first end of the second transistor is connected with a second end of the second transistor, a third end of the second transistor is connected with a first end of the third transistor, a first end of the third transistor is connected with a second end of the third transistor, and a third end of the third transistor is grounded; the second port of the first resistor is connected with the second port of the first switch module, and the second port of the first resistor is connected with the first port of the low-pass delay module.
In this embodiment, the first transistor, the second transistor, and the third transistor are all HBT transistors or all FET transistors.
In the present embodiment, three electrodes of the FET transistor are a gate, a source, and a drain, respectively; three electrodes of the HBT transistor are respectively a collector electrode, a base electrode and an emitter electrode.
In this embodiment, the first terminal of the transistor corresponds to the collector of the HBT transistor or the drain of the FET transistor, the second terminal of the transistor corresponds to the base of the HBT transistor or the gate of the FET transistor, and the third terminal of the transistor corresponds to the emitter of the HBT transistor or the source of the FET transistor.
In this embodiment, the second bias module includes: a second resistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first port of the second resistor is connected with the power supply input port, the second port of the second resistor is connected with the first end of the fourth transistor, the first end of the fourth transistor is connected with the second end of the fourth transistor, the third end of the fourth transistor is connected with the first end of the fifth transistor, the first end of the fifth transistor is connected with the second end of the fifth transistor, the third end of the fifth transistor is connected with the first end of the sixth transistor, the first end of the sixth transistor is connected with the second end of the sixth transistor, and the third end of the sixth transistor is grounded; and the second port of the second resistor is connected with the second port of the second switch module, and the second port of the second resistor is connected with the third port of the low-pass delay module.
In this embodiment, the fourth transistor, the fifth transistor, and the sixth transistor are all HBT transistors or all FET transistors.
In this embodiment, the low-pass delay module includes: a third resistor, a first capacitor and a second capacitor; the first port of the third resistor is connected with the first port of the second bias module, the second port of the third resistor is connected with the first port of the first capacitor, the second port of the first capacitor is connected with the first port of the first bias module, the second port of the third resistor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, and the second port of the third resistor is connected with the first port of the main drive module.
In this embodiment, the main driving module includes a seventh transistor, a second terminal of the seventh transistor is connected to the second port of the low-pass delay module, a first terminal of the seventh transistor is connected to the power input port, and a third terminal of the seventh transistor is connected to the first port of the third switching module.
In this embodiment, the third switching module includes a fourth resistor and an eighth transistor, a first end of the eighth transistor is connected to the third port of the main driving module, a second end of the eighth transistor is connected to the first port of the fourth resistor, a second port of the fourth resistor is connected to the second logic control interface, and a third end of the eighth transistor is connected to the power output port.
In this embodiment, the first switch module includes a fifth resistor and a ninth transistor, a first port of the fifth resistor is connected to the first logic control interface, a second port of the fifth resistor is connected to a second terminal of the ninth transistor, a first terminal of the ninth transistor is connected to the first port of the first bias module, and a third terminal of the ninth transistor is grounded.
In this embodiment, the second switch module includes a sixth resistor and a tenth transistor, a first port of the sixth resistor is connected to the first logic control interface, a second port of the sixth resistor is connected to a second terminal of the tenth transistor, a first terminal of the tenth transistor is connected to the first port of the second bias module, and a third terminal of the tenth transistor is grounded.
In the present embodiment, all transistors are HBT transistors.
The working principle of the utility model is further explained with reference to the circuit diagram in fig. 2:
under the fixed power source VCC, the voltage of the two points A, B in the off state of the switches T9 and T10 can be adjusted by adjusting the resistance values of R1 and R2. The resistance values of R1 and R2 can thus be determined by a preliminary adjustment.
When in use
When high, VC is low, the switches T9 and T10 are in an on state, the switch T8 is in an off state, and the voltage at A, B, C, D four points is zero; when in use
When VC is high, the switches T9 and T10 are in an off state, and the switch T8 is in an on state; at this time, T1, T2 and T3 in the first bias module are turned on, the voltage at the point a is determined by the divided voltages between R1 and T1, and T2 and T3, the voltage at the point a can be determined because R1 is predetermined, T4, T5 and T6 in the second bias module are turned on, the voltage at the point B is determined by the divided voltages between R2 and T4, and T5 and T6, and the voltage at the point B can be determined because R2 is predetermined; at the moment, A, B two-point voltage is quickly established, A, B two-point voltage is the same, one end of the point C is connected with the point A through the point C1, the other end of the point C is connected with the point B through the point R3, therefore, the voltage of the point C is influenced by the voltage of A, B two points and can be changed into the voltage of the point A or the point B, the voltage of the point C can follow the voltage of the point A because the voltage of two ends of a capacitor can not change suddenly, then the voltage of the point B can charge and discharge the capacitor of the point C through a resistor R3, so that the voltage of the point C is changed instantly, finally, the voltage of the point C is the same as the voltage of the point B, the charging and discharging time is changed by adjusting the resistance value of the resistor R3 and the capacitance values of the C1 and the C2, the voltage of the point D follows the change of the voltage of the point C through a transistor T7, the voltage of the point D is transmitted to the out through a T8 switching tube, so that the change form of the out voltage is consistent with the voltage of the point C, and the compensation of the thermal response of the amplifier is realized.
Referring to fig. 3, the transient thermal compensation circuit described above is applied to achieve a thermal response compensated for transient changes in amplifier bias voltage. The voltage is high after switching on and then decreases exponentially towards settling.
To sum up, the embodiment of the present invention provides a transient thermal compensation bias circuit for a power amplifier, which has the beneficial effects that the voltage at the voltage output port is the same as the voltage of a capacitor of the low-pass delay module, and when the level of the first logic control interface module changes from a high level to a low level, the voltage at the voltage output port changes along with the voltage of the capacitor in the low-pass delay module, so as to compensate the thermal response of the amplifier.
The technical scheme of the utility model does not need to additionally add a CMOS control chip, thus not increasing the packaging cost and the packaging risk. Because no control chip is additionally arranged, the packaging size cannot be increased, and the requirement of small-size packaging can be met.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (10)
1. A power amplifier transient thermal compensation bias circuit, comprising: the system comprises a power input port, a power output port, a first logic control interface, a second logic control interface, a first switch module, a second switch module, a third switch module, a first bias module, a second bias module, a low-pass delay module and a main driving module;
the first logic control interface is connected with a first port of a first switch module, a second port of the first switch module is connected with a first port of a first bias module, a second port of the first bias module is connected with a power input port, a first port of the first bias module is connected with a first port of a low-pass delay module, a second port of the low-pass delay module is connected with a first port of a main drive module, a second port of the main drive module is connected with the power input port, a third port of the main drive module is connected with a first port of a third switch module, a second port of the third switch module is connected with a power output port, and a third port of the third switch module is connected with a second logic control interface;
the first logic control interface is connected with a first port of the second switch module, a second port of the second switch module is connected with a first port of the second bias module, a second port of the second bias module is connected with the power input port, and a first port of the second bias module is connected with a third port of the low-pass delay module.
2. The power amplifier transient thermal compensation bias circuit of claim 1, wherein the first bias module comprises: a first resistor, a first transistor, a second transistor, and a third transistor; a first port of the first resistor is connected with the power supply input port, a second port of the first resistor is connected with a first end of the first transistor, a first end of the first transistor is connected with a second end of the first transistor, a third end of the first transistor is connected with a first end of the second transistor, a first end of the second transistor is connected with a second end of the second transistor, a third end of the second transistor is connected with a first end of the third transistor, a first end of the third transistor is connected with a second end of the third transistor, and a third end of the third transistor is grounded; the second port of the first resistor is connected with the second port of the first switch module, and the second port of the first resistor is connected with the first port of the low-pass delay module.
3. The power amplifier transient thermal compensation bias circuit of claim 2, wherein said first, second and third transistors are HBT transistors or FET transistors.
4. The power amplifier transient thermal compensation bias circuit of claim 1, wherein the second bias module comprises: a second resistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first port of the second resistor is connected with the power supply input port, the second port of the second resistor is connected with the first end of the fourth transistor, the first end of the fourth transistor is connected with the second end of the fourth transistor, the third end of the fourth transistor is connected with the first end of the fifth transistor, the first end of the fifth transistor is connected with the second end of the fifth transistor, the third end of the fifth transistor is connected with the first end of the sixth transistor, the first end of the sixth transistor is connected with the second end of the sixth transistor, and the third end of the sixth transistor is grounded; and the second port of the second resistor is connected with the second port of the second switch module, and the second port of the second resistor is connected with the third port of the low-pass delay module.
5. The transient thermally compensated bias circuit of claim 4, wherein the fourth transistor, the fifth transistor and the sixth transistor are all HBT transistors or all FET transistors.
6. The power amplifier transient thermal compensation bias circuit of claim 1, wherein the low pass delay module comprises: a third resistor, a first capacitor and a second capacitor; the first port of the third resistor is connected with the first port of the second bias module, the second port of the third resistor is connected with the first port of the first capacitor, the second port of the first capacitor is connected with the first port of the first bias module, the second port of the third resistor is connected with the first port of the second capacitor, the second port of the second capacitor is grounded, and the second port of the third resistor is connected with the first port of the main drive module.
7. The transient thermally compensated bias circuit of claim 1, wherein the main driver module comprises a seventh transistor, a second terminal of the seventh transistor is connected to the second port of the low-pass delay module, a first terminal of the seventh transistor is connected to the power input port, and a third terminal of the seventh transistor is connected to the first port of the third switch module.
8. The transient thermally compensated bias circuit of claim 1, wherein the third switching module comprises a fourth resistor and an eighth transistor, a first terminal of the eighth transistor is connected to the third port of the main driving module, a second terminal of the eighth transistor is connected to the first terminal of the fourth resistor, a second terminal of the fourth resistor is connected to the second logic control interface, and a third terminal of the eighth transistor is connected to the power output port.
9. The transient thermal compensation bias circuit of claim 1, wherein the first switch module comprises a fifth resistor and a ninth transistor, a first port of the fifth resistor is connected to the first logic control interface, a second port of the fifth resistor is connected to a second terminal of the ninth transistor, a first terminal of the ninth transistor is connected to the first port of the first bias module, and a third terminal of the ninth transistor is connected to ground.
10. The transient thermal compensation bias circuit of claim 1, wherein the second switch module comprises a sixth resistor and a tenth transistor, a first port of the sixth resistor is connected to the first logic control interface, a second port of the sixth resistor is connected to a second terminal of the tenth transistor, a first terminal of the tenth transistor is connected to the first port of the second bias module, and a third terminal of the tenth transistor is connected to ground.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123026918.8U CN216599552U (en) | 2021-12-02 | 2021-12-02 | Transient thermal compensation bias circuit of power amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202123026918.8U CN216599552U (en) | 2021-12-02 | 2021-12-02 | Transient thermal compensation bias circuit of power amplifier |
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| CN216599552U true CN216599552U (en) | 2022-05-24 |
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