CN1421789A

CN1421789A - Realizing method of double-channel shared memory

Info

Publication number: CN1421789A
Application number: CN 01135091
Authority: CN
Inventors: 涂君; 雷春
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2001-11-27
Filing date: 2001-11-27
Publication date: 2003-06-04
Anticipated expiration: 2021-11-27
Also published as: CN1180356C

Abstract

The double-channel shared memory is realized by means of several technological measures in setting work clock frequency, switching control signal and I/O signal sequence. The work clock frequency of the shared memory is set to be twice the system clock frequency of connected logic IC or ASIC chip, the switching control signal is set to be the switch selected signal in the same frequency and phase as that of system clock of connected logic IC or ASIC chip, one single-port memory is equivalent to a double-port memory to make two different modules inside the logic IC or ASIC chip obtain separate memory access interfaces with the same clock frequency as the system. The external shared memory has high comprehensive performance.

Description

A kind of implementation method of double-channel shared memory

Affiliated field

The present invention relates to a kind of method for designing of external memory interface circuit, exactly, the implementation method that relates to the double-channel shared memory of many-sided parameters such as a kind of capacity of taking into account technical complexity, cost, storer and performance belongs to the circuit design technique field of logic IC or asic chip.

Background technology

In the design process of logic IC or asic chip, often to use shared storage, restriction owing to reasons such as the memory span of logic IC or asic chip inside and costs, jumbo shared storage is placed on logic IC or asic chip inside is unpractical often or inappropriate, therefore all is that outside shared storage is used in configuration usually.At present, the common method that realizes outside shared storage has use push-up storage (FIFO), two-port RAM and visits outside shared storage by the method timesharing of bus arbitration, but the defective of aspect such as above-mentioned several method all exists more or less that technical sophistication, cost are higher, the capacity of storer or performance.

Use push-up storage (FIFO) as outside shared storage, design for logic IC or asic chip, implement fairly simple, but logic IC or asic chip can not be controlled the address of accessed memory cell, can only visit the content of memory cell among the FIFO in a certain order, therefore can only use FIFO as outside shared storage in some specific application scenarios, not have the ubiquity of application; And the price of FIFO is higher, and capacity is very little.

Use two-port RAM as outside shared storage, for the design of logic IC or asic chip, it implements also fairly simple, does not also have the defective of memory cell content among the necessary sequential access FIFO, has the ubiquity of application.And because the Different Logic module of logic IC or asic chip inside can be visited two-port RAM simultaneously by the different port of two-port RAM, need not to wait for bus arbitration, make the work efficiency of this logic IC or asic chip and performance all than higher.But two-port RAM has the price height equally, the shortcoming that capacity is very little; And its needed signal wire is a lot, is the twice of normal memory, can greatly waste the pin resource of logic IC or asic chip.

If use the outside shared storage of the way access of bus arbitration, though this outside shared storage can use the relatively more cheap also bigger memory chip of capacity simultaneously, do not need to take logic IC or the too many pin resource of asic chip yet, but need the design bus arbitration circuit, the distribution bus right to use need be applied for and wait for to the inner logic module of this shared storage of using of logic IC or asic chip simultaneously, the complicacy of the logic of entire chip is improved, and its work efficiency and performance also can reduce simultaneously.

Summary of the invention

The purpose of this invention is to provide a kind of obvious drawback that can solve top three kinds of schemes preferably, a kind of many-sided relatively good to obtain in conjunction with getting in capacity, cost, design complexity and system performance etc., and the implementation method of double-channel shared memory that can widespread usage

The implementation method of double-channel shared memory of the present invention is such: this method includes the following step: (1) at first the working clock frequency of this shared storage is set to the twice of the system clock frequency of its logic IC that connects or asic chip, make method that two disparate modules of this logic IC or asic chip inside can adopt timesharing from two independently access path visit this outside shared storage respectively; (2) because the logical organization of this double-channel shared memory module is a multichannel either-or switch that is subjected to switch-over control signal control gating, the system clock that this switch-over control signal is set to the logic IC that is connected with this shared storage or asic chip with frequently, the switch of homophase selects signal, address signal, data-signal and the read-write control signal that makes above-mentioned two independent access passages is sent to the output terminal of multichannel either-or switch respectively for moment of " 1 " and " 0 " at this switch-over control signal; (3) address signal, data-signal and the control signal of above-mentioned multichannel either-or switch output are carried out the sequential adjustment, and then it is outputed to the respective pin of outside shared storage, to satisfy outside shared storage for the sequential requirement between each signal; (4) data-signal of input is carried out the sequential adjustment respectively and latchs processing after, obtain the data input signal of two passages.

Described multichannel either-or switch includes following each binary channels at least: the address signal of two passages, the data output signal of the control signal of two passages and two passages.

Described switch-over control signal can be to select signal with the system clock of its logic IC that is connected or asic chip with frequency, anti-phase switch.

Characteristics of the present invention are the hardware logic structures at logic IC or asic chip, adopt certain technical measures on working clock frequency and the signal sequence, just the storer of a single port can be equivalent to the storer of a dual-port, make two disparate modules of logic IC or asic chip inside, can obtain an independently memory access interface respectively, and the clock frequency of this interface is identical with the clock frequency of total system, very convenient on using, thereby solved the obvious drawback of several outside shared storage scheme commonly used at present, obtain a kind of capacity at shared storage, cost, many-side such as design complexity and system performance all in conjunction with relatively good, and the implementation method of outside shared storage that can widespread usage.Can predict, method of the present invention will obtain the excellent popularization application from now on.

Description of drawings

Fig. 1 is the logic block-diagram of double-channel shared memory of the present invention.

Fig. 2 is the logic block-diagram of the embodiment of double-channel shared memory of the present invention.

Embodiment

The present invention is a kind of implementation method of double-channel shared memory, logic block-diagram referring to this double-channel shared memory shown in Figure 1, its logical organization comes down to a multichannel either-or switch that is subjected to switch-over control signal control gating, this multichannel either-or switch includes the address signal of following each binary channels shown in Figure 1: A, two passages of B at least, the data output signal of the control signal of A, two passages of B and A, two B passages.So method of the present invention be will switch-over control signal wherein be set to the system clock of the logic IC that is connected with this double-channel shared memory or asic chip with frequently, the switch of homophase (or anti-phase) selects signal, make address signal, data-signal and the read-write control signal of above-mentioned two independent access passages can be in the cycle of a system clock, be sent to the output terminal of multichannel either-or switch respectively at this switch-over control signal for moment of " 1 " and " 0 ".Also the working clock frequency of this shared storage to be arranged to the twice of the system clock frequency of its logic IC that connects or asic chip, so that can provide according to the method for timesharing two independently access path visit this outside shared storage for two disparate modules timesharing of logic IC or asic chip inside respectively, and do not need to carry out bus arbitration.In addition, address signal, data-signal and the control signal of above-mentioned multichannel either-or switch output all needs through suitable sequential adjustment, just can be output to the respective pin of outside shared storage then, to satisfy outside shared storage for the sequential requirement between each signal; And the data-signal of input also will could obtain the data input signal of two passages respectively after carrying out the sequential adjustment and latching processing.

Referring to the logical organization block scheme of the embodiment of double-channel shared memory of the present invention shown in Figure 2, the outside shared storage that uses among this embodiment is synchronous static memory (SSRAM).The hardware logic structure of this double-channel shared memory also is one and (claimed again: the multichannel either-or switch U1 of the SWITCH control gating time slot allocation switch) by switch-over control signal, this multichannel either-or switch U1 includes the address signal UA_ADD and the UB_ADD of following each binary channels: A, two passages of B, the read-write control signal UA_WEN and the UB_WEN of A, two passages of B, the data output signal UA_DTO and the UB_DTO of A, two B passages.The signal waveform of the switch-over control signal here (that is: time slot allocation switch) SWITCH requires and system clock CLK frequency homophase (or anti-phase) together, so that the SCLK clock period of correspondence is distributed to A channel visit shared storage when making signal SWITCH for " 0 ", the SCLK clock period of correspondence was distributed to B channel access shared storage when SWITCH was " 1 ", thereby above-mentioned two A have been realized making, the address signal of B autonomous channel, data-signal and read-write control signal can be in the cycles of a system clock, are sent to the output terminal of multichannel either-or switch U1 respectively for moment of " 0 " and " 1 " at this switch-over control signal.CLK is a clock signal of system among the figure, and SCLK is the two frequency multiplication clock signals of system clock CLK, is obtained after to system clock CLK phase locking frequency multiplying by the inner or outside phaselocked loop of this logic chip.Similarly, address signal SRMADD, the data-signal SRMDTO of above-mentioned multichannel either-or switch U1 output needs just can be output to the address signal PINSRMADD that is connected with external memory storage, the respective pin of data-signal PINSRMDAT, read-write control signal PINSRMWEN through after the suitable sequential adjustment with control signal SRMWEN, to satisfy outside shared storage for the sequential requirement between each signal; And the data-signal SRMDTI of the input of this external memory storage also will carry out the sequential adjustment and latch after could obtain the data input signal UA_DTI and the UB_DTI of A, two passages of B respectively.U2 among the figure, U3, U4, U5, U7, U8, U9 and U10 are the circuit that is used to finish sequential adjustment and data latching.The capacity of this synchronous static memory (SSRAM) is much bigger with respect to two-port RAM, and its price is much lower simultaneously, promptly uses this synchronous static memory (SSRAM) to have the good ratio of performance to price as shared storage; And the operating rate that SSRAM allows is very high, relatively is fit to the occasion higher to performance requirement.

The applicant has carried out implementing test according to method of the present invention, and the embodiment of above-mentioned synchronous static memory (SSRAM) is one of them, and the enforcement test of these double-channel shared memories is successful, has realized the goal of the invention of expection.

Claims

1, a kind of implementation method of double-channel shared memory, it is characterized in that: this method includes the following step: (1) at first the working clock frequency of this shared storage is set to the twice of the system clock frequency of its logic IC that connects or asic chip, make method that two disparate modules of this logic IC or asic chip inside can adopt timesharing from two independently access path visit this outside shared storage respectively; (2) because the logical organization of this double-channel shared memory module is a multichannel either-or switch that is subjected to switch-over control signal control gating, the system clock that this switch-over control signal is set to the logic IC that is connected with this shared storage or asic chip with frequently, the switch of homophase selects signal, address signal, data-signal and the read-write control signal that makes above-mentioned two independent access passages is sent to the output terminal of multichannel either-or switch respectively for moment of " 1 " and " 0 " at this switch-over control signal; (3) address signal, data-signal and the control signal of above-mentioned multichannel either-or switch output are carried out the sequential adjustment, and then it is outputed to the respective pin of outside shared storage, to satisfy outside shared storage for the sequential requirement between each signal; (4) data-signal of input is carried out the sequential adjustment respectively and latchs processing after, obtain the data input signal of two passages.

2, the implementation method of double-channel shared memory according to claim 1, it is characterized in that: described multichannel either-or switch includes following each binary channels at least: the address signal of two passages, the data output signal of the control signal of two passages and two passages.

3, the implementation method of double-channel shared memory according to claim 1 is characterized in that: described switch-over control signal can be to select signal with the system clock of its logic IC that is connected or asic chip with frequency, anti-phase switch.