CN1417850A - Shallow-channel insulation making process - Google Patents
Shallow-channel insulation making process Download PDFInfo
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- CN1417850A CN1417850A CN 01137817 CN01137817A CN1417850A CN 1417850 A CN1417850 A CN 1417850A CN 01137817 CN01137817 CN 01137817 CN 01137817 A CN01137817 A CN 01137817A CN 1417850 A CN1417850 A CN 1417850A
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Abstract
The present invention provides shallow-channel insulation making process, which includes: providing substrate material and forming stacked mask layer comprising backing oxide layer and barrier layer, which at least one opening to expose the substrate and on the substrate; drying itching the substrate via the opening to form shallow channel and depositing CVD lining layer; oxidizing the CVD lining layer to form oxide lining layer and depositing one dielectric layer to fill the shallow channel; and final flattening, eliminating the dielectric layer and oxide lining layer over the barrier layer to expose the barrier layer and eliminating and barrier layer.
Description
Invention field
(particularly a kind of shallow-channel insulation making process of avoiding producing in the shallow ridges corner areas depression flaw (spot) is to guarantee the good electrical properties of product for shallow trench isolation, STI) manufacturing method thereof to the invention provides a kind of shallow-channel insulation.
Background of invention
In manufacture of semiconductor; have good insulation performance in order to make on the wafer between each electronic component; produce short circuit phenomenon to avoid the mutual interference of element phase; generally all adopt regional oxidizing process (localizedoxidation isolation, LOCOS) or the shallow-channel insulation method insulate with the protection.Because it is too big that the field oxide (field oxide) that produces in the LOCOS processing procedure occupies the area of wafer, and generative process can be followed the generation of beak (bird ' s beak) phenomenon, and therefore the manufacture of semiconductor of live width below 0.25 μ m nearly all adopts the shallow-channel insulation method at present.The shallow-channel insulation method is to make a shallow ridges and insert megohmite insulant to produce the effect of electric insulation at each interelement of wafer surface.
Please refer to Fig. 1 to Fig. 3, Fig. 1 to Fig. 3 is the shallow-channel insulation method schematic diagram in the manufacture of semiconductor of knowing.As shown in Figure 1, semiconductor wafer 10 includes a silicon substrate 12, and one silica layer (siliconoxide) 14 is located on the silicon substrate 12, and a silicon nitride layer (silicon nitride) 16 is deposited on the silicon oxide layer 14.Silicon oxide layer 14 and silicon nitride layer 16 are pad oxide (pad oxide) and the cover curtains (mask) that are used as successive process respectively.
The method of known making shallow-channel insulation is to utilize photoetch method (photolithography) and anisotropic etching processing procedures such as (anisotropic etching) earlier, in semiconductor wafer 10 lip-deep presumptive areas, form shallow ridges 18, and make shallow ridges 18 pass silicon nitride layer 16 and silicon oxide layer 14 gos deep in the silicon substrate 12 to certain depth.Subsequently as shown in Figure 2, because the surface of insulating channel 18 is through after the etching, may form the lattice defect of part, therefore utilize oxidation process again, in 800 ℃ to 1000 ℃ high temperature furnace pipe, feed the dry type oxidation of purity oxygen or the wet oxidation of aerating oxygen and steam, form lining oxide layer (liner oxide layer) 22 with 12 surfaces of the silicon substrate in insulating channel 18, and make the sharp corners between insulating channel 18 and silicon substrate 12 surfaces be oxidized to slick and sly profile, cause " corner slynessization " (corner-rounding), and then avoid causing engaging leakage current.
Then as shown in Figure 3, (chemical vapor deposition CVD) is formed uniformly one dielectric layer 20 on semiconductor wafer 10 surfaces, and fills up shallow ridges 18 to utilize chemical vapour deposition technique, be used as megohmite insulant, make shallow ridges 18 reach the effect of electric insulation.Then carry out the planarization processing procedure again, (chemical mechanical polishing CMP), removes the dielectric layer 20 of a part to utilize chemico-mechanical polishing.Utilize the chemical solvent of knowing at last, for example hot phosphoric acid, remove silicon nitride layer 16 fully, dielectric layer 20 in only remaining silicon oxide layer 14 and the shallow ridges 18, and make that dielectric layer 20 surfaces of inserting in the shallow ridges 18 are rough to trim with silicon oxide layer 14 surfaces, make semiconductor wafer 10 form even curface, to finish shallow-channel insulation making.
Yet the shallow-channel insulation method of knowing but can produce several main problems.At first, when utilizing the anisotropic etching processing procedure, when in semiconductor wafer 10 lip-deep presumptive areas, forming shallow ridges 18, because the etch-rate of silicon oxide layer 14, therefore can produce oxide layer depression (oxide-recesses portion) 24 greater than the etch-rate of silicon nitride layer 16 at shallow ridges corner areas 23 places in shallow ridges zone 18.When inserting dielectric layer 20,,, cause the element electrical property unusual follow-up so its part that is not filled can form the depression flaw because this oxide layer depression 24 can't be filled up fully.Even when inserting dielectric layer 20, this oxide layer depression 24 is filled up fully, the density of its contained dielectric layer 20 certainly will be less, cause shallow ridges corner areas 23 in follow-up Wet-type etching (wet etching) processing procedure, to have higher etch-rate, thereby make shallow ridges corner areas 23 and shallow ridges sidewall be vulnerable to gate fringe field (fringingelectric field) induction.The high field effect of this shallow ridges corner areas 23 can cause the carrier counter-rotating of shallow ridges corner areas, and forms the low start voltage passage that is parallel to major component, causes the element leakage current to increase, time start voltage neck joint (sub-threshold kink) phenomenon that Here it is.In addition, this oxide layer depression 24 will make shallow ridges corner areas 23 in follow-up acid soak manufacturing process for cleaning, as easy as rolling off a logly be subjected to etching, and the electric insulating effect of reduction shallow-channel insulation, and then cause semiconductor element conductivity undesired, for example the Id/Vg curve produces not good two protuberances (double hump) variation, reduces the reliability of product.
Summary of the invention
Therefore main purpose of the present invention is to provide a kind of manufacturing method thereof of shallow-channel insulation, avoids producing the depression flaw in the shallow ridges corner areas, solving the problem of the above-mentioned manufacture method of knowing, and guarantees the good electrical properties of product.
In most preferred embodiment of the present invention, semiconductor wafer comprises base material.At first on this substrate surface, form one by pad oxide and thickness be about 800 to 2500 dusts (angstrom) stop that layer (stoplayer) constituted pile up cover curtain layer (stacked mask), and this piles up cover curtain layer and has at least one opening (opening) to expose the part surface of this base material.Then carry out dry ecthing procedure, via this this substrate surface of opening etching, to form a shallow ridges, and carry out low-pressure chemical vapor deposition (low pressurechemical vapor deposition, LPCVD) processing procedure is to pile up deposition one deck on the cover curtain layer surface by silicon nitride was constituted and thickness is less than or equal to the CVD laying (liner) of 200 dusts in this shallow ridges and this.Afterwards, utilize on the spot vapor-grown (in-situ steam growth, ISSG) technology, this CVD laying of oxidation, forming the oxide liner layer, and on this oxide liner layer deposition one dielectric layer to fill up this shallow ridges.Carry out the planarization processing procedure at last, remove this and stop dielectric layer and oxide liner layer directly over the layer, stop layer, afterwards, remove this and stop layer to expose this.
Because manufacture method of the present invention is to avoid consuming under the prerequisite of siliceous base material, rely on the oxide liner layer that forms with the ISSG technology, the oxide layer depression of shallow ridges corner areas is fully closely filled up, therefore, removing fully with hot phosphoric acid when stopping layer, can avoid the shallow ridges corner areas to be subjected to the etching of hot phosphoric acid, and cause semiconductor element conductivity undesired, for example the Id/Vg curve produces not good two protuberance variations, and be subjected to gate fringe field (fringing electric field) induction because of the shallow ridges sidewall, cause the carrier counter-rotating of shallow ridges corner areas, and the element leakage current that is caused increases, i.e. time start voltage neck joint phenomenon.So comparatively speaking, the present invention can guarantee the electric insulating effect of shallow-channel insulation, promotes the reliability of product, and then promotes product competitiveness.
The accompanying drawing summary
Fig. 1 to Fig. 3 is the shallow-channel insulation method schematic diagram in the manufacture of semiconductor of knowing.
Fig. 4 to Fig. 8 is a shallow-channel insulation making process schematic diagram of the present invention.
Illustrated symbol description
10 semiconductor wafers, 12 silicon substrates
14 silicon oxide layers, 16 silicon nitride layers
18 shallow ridges, 20 dielectric layers
22 lining oxide layers, 23 shallow ridges corner areas
24 oxide layers, 30 semiconductor wafers that cave in
32 silicon substrates, 33 shallow ridges corner areas
34 pad oxides 36 stop the upper strata
37 pile up cover curtain layer 38 shallow ridges
40 dielectric layer 42CVD layings
44 oxide layers, 46 openings that cave in
48 oxide liner layers, 50 silicon oxide layer
Detailed Description Of The Invention
Please refer to Fig. 4 to Fig. 8, Fig. 4 to Fig. 8 is a shallow-channel insulation making process schematic diagram of the present invention.As shown in Figure 4, semiconductor wafer 30 includes a silicon substrate 32 and by pad oxide 34 with stop 36 on layer and constitute, and have at least one opening 46 expose part silicon substrate 32 surfaces pile up cover curtain layer 37.Wherein stopping layer 36 is to be a silicon nitride layer.
As shown in Figure 5, at first carry out the anisotropic dry etch processing procedure,, go deep in the silicon substrate 32 to certain depth on semiconductor wafer 30, to form shallow ridges 38 via opening 46 etching silicon base materials 32 surfaces.Because the etch-rate of pad oxide 34 is greater than the etch-rate that stops layer 36, so the time can produce oxide layer depression 44 at shallow ridges corner areas 33 places in shallow ridges zone 18, easily in successive process in causing shallow ridges corner areas 33 places to produce the depression flaw, cause the semiconductor element electric can be unusual.
Subsequently as shown in Figure 6, carry out the low-pressure chemical vapor deposition processing procedure, with in shallow ridges 38 and pile up cover curtain layer 37 surface and go up the CVD laying 42 that deposition is made of silicon nitride and thickness is less than or equal to 200 dusts.CVD laying 42 can fill up the oxide layer depression 44 at shallow ridges corner areas 33 places in growth fully.
Then as shown in Figure 7, carry out oxidation process, have to oxidation (oxidized) laying 48 of the SiON layer of small part substrate surface CVD laying 42 is oxidized to one, and on oxide liner layer 48 dielectric layer 40, to fill up shallow ridges 38.Wherein the method for this CVD laying of oxidation is to utilize to contain oxygen radical and hydroperoxyl radical, and use in addition balance of nitrogen, be higher than the technology of vapor-grown on the spot of being carried out under 800 ℃ of temperature, wherein the flow of hydroperoxyl radical is lower than 50% of oxygen radical and hydroperoxyl radical total flow.CVD laying 42 is oxidized to oxide liner layer 48 back volumes can be expanded to 1.3 to 1.5 times of original volume.In addition, as shown in Figure 8, in another embodiment of the present invention, when CVD laying 42 was oxidized to oxide liner layer 48, part is made of silicon nitride to be stopped layers 36 and also can be oxidized to SiON layer 50.
At last as shown in Figure 9, carry out the planarization processing procedure, utilize chemical mechanical polishing manufacture procedure, removal stops dielectric layer 40 and the oxide liner layer 48 directly over the layer 36, stops layer 36 to expose this.Utilize the chemical solvent of knowing subsequently, for example hot phosphoric acid, remove fully and stop layer 36, dielectric layer 40 in only remaining pad oxide 34 and the shallow ridges 38, and make that dielectric layer 40 surfaces of inserting in the shallow ridges 38 are rough to trim with pad oxide 34 surfaces, make semiconductor wafer 30 form even curface, to finish shallow-channel insulation making.
Wherein, the vapor-grown technology is a kind of low pressure wet type rapid thermal oxidation method with high reproducibility on the spot, can in single wafer RTP reactor, carry out, the RTP XEplus Centura type of Applied Materials (Applied MaterialsCo.) for example, its top disposes 15 to 20 tungsten filament halogen heating fluorescent tubes (tungsten halogen lamp) that are arranged in parallel, fast wafer is warming up to desired high temperature.
Compared to the technology of knowing, shallow-channel insulation making process of the present invention is to adopt the ISSG technology CVD laying 42 to be oxidized to the oxide liner layer 48 with higher resistance to corrosion.In addition, CVD laying 42 can cave in oxide layer and 44 fill up fully, therefore can avoid time start voltage neck joint phenomenon.In addition, because the oxide layer of shallow ridges corner areas depression can fully closely be filled up by the preferable oxide liner layer of corrosion stability, therefore removing fully with hot phosphoric acid when stopping layer, can avoid the shallow ridges corner areas to be subjected to the etching of hot phosphoric acid, and cause the semiconductor element electric conductivity undesired, for example the Id/Vg curve produces not good two protuberance variations.So the present invention can avoid consuming under the prerequisite of siliceous base material, rely on to form the oxide liner layer, solve above-mentioned all items and be present in the problem of knowing in the technology, to guarantee the electric insulating effect of shallow-channel insulation, promote the reliability of product.
The above preferred embodiment only of the present invention, all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (11)
1. shallow-channel insulation making process, this method comprises the following steps:
Base material is provided;
On this substrate surface, form by pad oxide and stop the cover curtain layer that piles up that layer constituted, and this piles up cover curtain layer and has this substrate surface that at least one opening exposes part;
Carry out dry ecthing procedure, via this this substrate surface of opening etching, to form shallow ridges;
Pile up cvd nitride silicon liner layer on the cover curtain layer surface at this shallow ridges and this;
This silicon nitride liner layer of oxidation is to have this silicon nitride layer oxidation shape on the oxide liner layer to the small part silicon oxynitride layer;
Dielectric layer on this oxide liner layer, and this dielectric layer fills up this shallow ridges;
Carry out the planarization processing procedure, remove this and stop dielectric layer and oxide liner layer directly over the layer, stop layer to expose, and
Remove this and stop layer.
2. the process of claim 1 wherein that this stops layer is to be silicon layer.
3. the method for claim 2, wherein the thickness of this silicon layer is about 800 to 2500 dusts.
4. the process of claim 1 wherein that this oxide liner layer is to be the SiON layer.
5. the process of claim 1 wherein that this CVD laying is made of silicon nitride.
6. the process of claim 1 wherein that this SiON layer is close to this substrate surface.
7. the method for claim 6, wherein this stops that the part near the oxide liner layer also can be silicon oxynitride layer in the layer.
8. the method for claim 5, wherein this CVD laying is formed by Low Pressure Chemical Vapor Deposition.
9. the method for claim 5, wherein the thickness of this CVD laying is less than or equal to 200 dusts.
10. the method for claim 5, wherein the method for this CVD laying of oxidation is to utilize vapor-grown technology on the spot.
11. the process of claim 1 wherein that this base material is a silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01137817 CN1202570C (en) | 2001-11-08 | 2001-11-08 | Shallow-channel insulation making process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01137817 CN1202570C (en) | 2001-11-08 | 2001-11-08 | Shallow-channel insulation making process |
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| CN1417850A true CN1417850A (en) | 2003-05-14 |
| CN1202570C CN1202570C (en) | 2005-05-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01137817 Expired - Fee Related CN1202570C (en) | 2001-11-08 | 2001-11-08 | Shallow-channel insulation making process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102652364A (en) * | 2009-12-18 | 2012-08-29 | 英特尔公司 | Isolation for nanowire devices |
| CN105448923A (en) * | 2014-08-07 | 2016-03-30 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
-
2001
- 2001-11-08 CN CN 01137817 patent/CN1202570C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102652364A (en) * | 2009-12-18 | 2012-08-29 | 英特尔公司 | Isolation for nanowire devices |
| CN105448923A (en) * | 2014-08-07 | 2016-03-30 | 旺宏电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1202570C (en) | 2005-05-18 |
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