CN1416179A - Silicon solar cell of nesa with transparent conductive folm front electrode - Google Patents
Silicon solar cell of nesa with transparent conductive folm front electrode Download PDFInfo
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- CN1416179A CN1416179A CN01129013A CN01129013A CN1416179A CN 1416179 A CN1416179 A CN 1416179A CN 01129013 A CN01129013 A CN 01129013A CN 01129013 A CN01129013 A CN 01129013A CN 1416179 A CN1416179 A CN 1416179A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 27
- 239000010703 silicon Substances 0.000 title claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 239000011248 coating agent Substances 0.000 claims description 52
- 238000000576 coating method Methods 0.000 claims description 52
- 230000004888 barrier function Effects 0.000 claims description 29
- 230000005611 electricity Effects 0.000 claims description 20
- 229910006404 SnO 2 Inorganic materials 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 21
- 238000000034 method Methods 0.000 description 18
- 239000002184 metal Substances 0.000 description 13
- 238000002360 preparation method Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Engineering & Computer Science (AREA)
- Sustainable Energy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The transparent electric film is utilized as the front electrode to replace the fence type from electrode and the layer for reducing the reflection. The from electrode of the transparent electric film in the invention is laminated structure. That is prepared by following steps. The transparent electric film with high resistance and the thickness less than 100nm are prepared on the silicon substrate with the n-p node having been formed. Then, the transparent electric film with high conductance and the thickness larger than 150nm is prepared according to the requirement of the conductance and the reduced reflection. Comparing to the prior art, the invention makes the conversion efficiency increase 25-35%.
Description
One, technical field
The invention belongs to the photovoltaic cell of new construction.
Two, background technology
The basic structure of existing crystalline silicon (monocrystalline silicon, polysilicon) solar cell as shown in Figure 1.It is the crystalline silicon (B) that is shaped on planar semiconductor n-p knot (C) by, adds that back electrode (A) and preceding electrode (E) constitute.Preceding electrode is very crucial, and it can not block incident light and enter in the n-p knot to guarantee most of incident light, again photo-generated carrier is had sufficient collection.This is the requirement of two mutual contradictions.Present technology is to adopt the metal gate-shaped electrode to solve this to contradiction.
In order to reduce the reflection of sunlight, used optics antireflection layer (F) usually at silicon face.They are refractive index silicon monoxide (SiO), silicon nitride insulation films such as (SiN) between 2.0～2.2.
As seen from Figure 1: electrode is reserved exhibiting high surface before the palisade, to accept incident light.Photogenerated current then relies on the transverse movement of photo-generated carrier at solar cell top layer (D), is collected and forms by electrode before the palisade.For n-p type crystal silicon solar energy battery, why photo-generated carrier can do the transverse movement of longer distance, is because they have long diffusion length on the n-Si top layer.Certainly, also require the top layer that enough thickness is arranged, to reduce the resistance on top layer as far as possible.Like this, before adopting palisade under the situation of electrode, also to handle another well to contradiction: on the one hand, wish that the top layer is thin, promptly tie shallowly that this is to improving short wave response, the short circuit current of solar cell, and all favourable to the performance that improves battery; On the other hand, wish to increase skin depth again, reducing the top layer lateral resistance, thereby electricity increases short circuit current and fill factor, curve factor.The prior art of crystal silicon solar energy battery is that the top layer is controlled at about 1 micron.Therefore, the preceding electrode of palisade that present crystal silicon solar energy battery is used, the distance between each strip electrode can be than broad, and promptly the density of grid is rarer, and shape can be not too accurate.
In the crystal silicon solar energy battery, also have a kind of structure to be called the solar cell of MIS.The basic structure of MIS solar cell as shown in Figure 2.It is to drive photo-generated carrier and produce electromotive force with the schottky junction (J) that metal and semiconductor form.Between metal and semiconductor, one deck very thin (about tens dusts), the good oxide insulating layer of quality (I) also must be arranged, as SiO
2, Al
2O
3Deng.
Because schottky junction is very shallow, and the top layer is very thin, also because the topped whole semiconductor surface of schottky junction that needs metal electrode and semiconductor to form, therefore just requires the distance between each bar gate-shaped electrode (E) must be quite little, the density that is grid is quite high, and shape must be very accurate.
In sum, there are the following problems for prior art:
Electrode approximately will cover 6～10% surface area before the palisade that adopts, and the effective area of solar cell is reduced, thereby conversion efficiency is reduced.
(1) using the result of the preceding electrode of palisade is that photo-generated carrier must be done transverse movement on the top layer.This has brought extra series resistance, and short circuit current and fill factor, curve factor are descended.Calculating shows: when skin resistance is 245 Ω .cm
2The time, the effective area that is equivalent to solar cell drops to 40%; Skin resistance is 4.6 Ω .cm
2The time, effective area drops to 60%; Skin resistance is 1 Ω .cm
2The time, effective area also only has about 80%.On the other hand, for improving spectral response, make shallow junction.The thing followed must be made close grid.Calculating shows: when skin depth is 0.15 μ, just need the close grid of 30/cm, this using light lithography could be realized.So make the cost of solar cell increase greatly.
(2) for the resistance that makes the top layer is low, the top layer must be thicker, is generally about 1 μ.Thick like this heavily doped layer is called as " dead layer ".It can absorb many incident lights, and (for example: the silicon of 0.5 μ can absorb 9% sunlight; Sunlight almost completely was absorbed when 2 μ were thick), but can not be converted to electric power.It also has a large amount of faults of construction, can catch photo-generated carrier, makes it and can not make contributions to photogenerated current.Therefore, thick top layer also is to improving the very important restriction of solar cell conversion efficiency.
Amid all these factors, rough calculating shows: even the skin depth that existing crystal silicon solar energy battery adopts the shallow density of appropriate grid and matches still can make the conversion efficiency loss about 30% of solar cell.
Three, summary of the invention
Purpose of the present invention is exactly the shortcoming that will overcome prior art, obtains a kind of conversion efficiency height, crystal silicon solar energy battery that cost of manufacture is low.
The technological means that the present invention adopts is, is back electrode/be shaped on the solar cell of the crystalline silicon/preceding electrode of n-p knot to structure, and the preceding electrode of employing is an electrode before the nesa coating, to replace electrode before the palisade.The kind and the preparation method of appropriate selection nesa coating, can make its refractive index is 1.8～2.0, adds to be prepared into appropriate thickness and just will to have the antireflective effect.So, electrode and antireflecting double action before electrode will play before the nesa coating that the present invention adopts.
For the better effect that the present invention is obtained, adopt high electricity to lead nesa coating if consider nesa coating, it is the very high broad-band gap degenerate semiconductor of a kind of doping content, can produce a large amount of interfacial states between it and the highly doped silicon.Therefore, the present invention leads at high electricity and introduces a barrier layer between nesa coating and the n-type silicon, promptly be to lead the enough thin high resistance nesa coating barrier layer of nesa coating conductive layer and one deck with the enough thick high electricity of one deck to constitute electrode before the nesa coating, replace electrode and antireflection layer before the palisade.
For realizing the present invention, according to the existing preparation technology, the high electricity before the nesa coating in the electrode is led the nesa coating conductive layer and can be adopted ITO (In
2O
3: SnO
2), SnO
2, ZnO or Cd
2SnO
4Deng polycrystal film, doping content is 10
19-10
21/ cm
3Their energy gap width is between 3.3～4.2eV, and bulk conductivity is 10
3～10
4(Ω .cm)
-1, refractive index is 1.8～2.00.It is thick that film can be made 300--900nm.Making preceding electrode with it has three effects, and brings significant effect:
(1) allow incident light pass through.In the prior art, the absorption coefficient of light of nesa coating is very little; The transmitance of the nesa coating that 500～600nm is thick is about 95%.
(2), increase the incident of light as antireflection layer.Calculating shows, is about 1.95 transparent medium in the topped refractive index of silicon face, concerns nL=K (λ when the optical thickness of transparent dielectric layer satisfies
0/ 4) time, be λ to wavelength
0Light anti-reflection effect is arranged.In the formula, n is the transparent medium refractive index, and L is its thickness, λ
0Be selected optical wavelength, K is a positive integer.When n gets 2, λ
0Be taken as 600nm, the electrically conducting transparent film thickness is L=75,150,225,300,375,525,600 so ... has best anti-reflective effect during nm.This is in the present invention, selects the basic principle of electrically conducting transparent film thickness.
(3), collect photogenerated current as conductive electrode.To the thick nesa coating of 600nm, the about 6 Ω .cm of its rete resistance
2, 1/10th of not enough shallow junction silicon skin resistance is less than 1/3rd of dark knot silicon skin resistance.Therefore, can improve collection greatly to photogenerated current.
High resistance nesa coating barrier layer before the nesa coating in the electrode can be plain SnO
2, ZnO or Zn
2SnO
4Deng polycrystal film or plain SnO
2, noncrystalline membrane such as ZnO (allows " 10 in manufacturing process
16/ cm
3Impurity concentration ".With the change of preparation technology, component and micro-structural, its resistivity is 1～1000 Ω .cm.It plays passivation to highly doped silicon surface, can reduce high electricity greatly and lead interfacial state on nesa coating/highly doped silicon interface, also can modification be arranged to the band structure at this interface.Therefore, it is referred to as the barrier layer.The thickness on barrier layer is determined by its resistivity own.Basic consideration is, should play passivation and can be with modification, can not bring extra series resistance again.As, when resistivity was 1-10 Ω .cm, thickness was advisable with 100nm.When volume resistivity was 100-1000 Ω .nm, thickness was reduced to 10nm or thinner.
The present invention makes the performance of crystal-silicon solar cell that following improvement be arranged:
(a) improved the amount about 5% of incident light;
(b) lead by improving horizontal electricity, be equivalent to the effective area about 15～20% that increases solar cell;
(c) can make crystal-silicon solar cell be made into shallow junction, improve the shortwave spectral response, make power output that 5～10% raising be arranged.
More than 3 effects integrate, can make conversion efficiency improve 35～40%.Can believe that along with the improvement of electrically conducting transparent film properties, its effect also can be more remarkable.In addition, implementing the present invention descends the cost of crystal-silicon solar cell.Because it is suitable with the cost of making antireflective coating to make the cost of nesa coating, and the preparation cost of preceding electrode is more much lower than making close grid with photoetching technique, it is low also to make common gate-shaped electrode than screen printing technique.Therefore, cost will reduce more than 10%.
Four, description of drawings
Fig. 1 is the structure chart of existing crystal-silicon solar cell;
Fig. 2 is the structure chart of MIS solar cell;
Fig. 3 is the structure chart of crystal-silicon solar cell of the present invention.
Five, embodiment
Describe embodiments of the present invention in detail below in conjunction with accompanying drawing.
According to solar battery structure shown in Figure 3: crystalline silicon (B)/high resistance nesa coating barrier layer (the G)/high electricity of back electrode (A)/be shaped on n-p knot (C) is led nesa coating conductive layer (H)/metal electrode (K), the order of making the preceding electrode of crystal-silicon solar cell nesa coating is: on the crystalline silicon substrate that forms the n-p knot, deposit the high resistance nesa coating barrier layer of 10-100nm earlier, deposit the thick high electricity of 300--900nm then and lead the nesa coating conductive layer, make metal electrode at last.According to the size of silicon chip, can make one or several metal electrode in parallel, the interelectrode width of bullion can be equal to or greater than 10mm.
Following implementation process is all carried out on the silicon base (B) that forms n-p knot (C).
Embodiment 1:
Amorphous Sn O is adopted on high resistance nesa coating barrier layer
2,, can obtain very high resistivity with the PECVD preparation.Be generally resistivity 〉=10
4Ω .cm.High electricity is led the nesa coating conductive layer and is adopted the SnO that mixes
2Concrete enforcement is as follows: earlier with the thick barrier layer (G) of PECVD technology preparation 5～10nm.Prepare high electricity with sputtering method, low pressure chemical vapor deposition method or atmospheric pressure cvd method again and lead nesa coating conductive layer (H).Thickness is controlled to be 150～750nm by the antireflective condition, and is perhaps thicker.Make the preceding electrode (K) of metal with silk screen printing, sputter or vacuum evaporation at last.The density of electrode strip is 0.5-2 bar/cm before general.
As amorphous Sn O
2The resistivity on barrier layer is 10
4Ω .cm, thickness are 5nm; The SnO that mixes
2The conductivity of nesa coating conductive layer is 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 30% than electrode before using palisade.
Embodiment 2:
Amorphous Sn O is adopted on high resistance nesa coating barrier layer
2, high electricity is led the nesa coating conductive layer and is adopted ito thin film, also can use ZnO film or the Cd that mixes
2SnO
4Film.The barrier layer (G) for preparing 5～10nm earlier with the PECVD technology.Prepare high electricity with sputtering method or APCVD method again and lead nesa coating conductive layer (H), thickness is 150～750nm or thicker.At last, electrode (K) before the preparation metal, method is as described in the example 1.
As amorphous Sn O
2The resistivity on barrier layer is 10
4Ω .cm, thickness are 5nm; The conductivity of ITO nesa coating conductive layer is 1.5 * 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 35% than electrode before using palisade.
Embodiment 3:
High resistance nesa coating barrier layer SnO
2Adopt polycrystal film, high electricity is led the nesa coating conductive layer and is adopted the SnO that mixes
2Film or ITO film, or the ZnO film, the Cd that mix
2SnO
4Film.Earlier prepare plain high resistance nesa coating barrier layer (G) with low pressure chemical vapor deposition or atmospheric pressure cvd method.Because its resistivity is between 5～10 Ω .cm, its THICKNESS CONTROL is about 100nm.By example 1 or example 2 described technology, make high electricity and lead nesa coating conductive layer (H) then, thickness is 150～750nm, also can be thicker.Be that available sputtering method, low pressure chemical vapor deposition method or atmospheric pressure cvd method prepare SnO
2Polycrystal film nesa coating conductive layer; Or use sputtering method, the atmospheric pressure cvd method prepares the ITO film; Or the ZnO film, the Cd that mix with the preparation of other method
2SnO
4Film.At last, make the preceding electrode (K) of metal by the method for example 1.
As the SnO that undopes
2The resistivity on barrier layer is 1～10 Ω .cm, and thickness is 50～100nm; The conductivity of ITO layer is 1.5 * 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 25% than using gate-shaped electrode.
Embodiment 4:
Zn is adopted on high resistance nesa coating barrier layer
2SnO
4Film, high electricity are led the material that the nesa coating conductive layer adopts can be identical with embodiment 3.Earlier prepare barrier layer (G) with sputtering method or other method.Because its resistivity is between 10～1000 Ω .nm, barrier layer thickness is controlled between 20～50nm.Then, by example 1 or the fabrication techniques 150～750nm of example 2 or thicker nesa coating conductive layer (H).At last, by electrode (K) before the fabrication techniques metal of example 1.
Work as Zn
2SnO
4The resistivity on barrier layer is 1000 Ω .cm, and thickness is 10nm; Cd
2SnO
4The conductivity of layer is 1.5 * 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 35% than using gate-shaped electrode.
Embodiment 5:
Plain ZnO noncrystalline membrane is adopted on high resistance nesa coating barrier layer, and it can be the ZnO film that mixes that high electricity is led the nesa coating conductive layer, or the ITO in the foregoing description, doping SnO
2Or Cd
2SnO
4Deng.Do barrier layer (G) with PECVD or the preparation of other method earlier.Because resistivity is between 1～100 Ω .nm, the ZnO barrier layer thickness is controlled between 5～50nm, makes 150～750nm or thicker nesa coating conductive layer (H) then.At last, make the preceding electrode (K) of metal by example 1.
Resistivity when the ZnO barrier layer is 1000 Ω .cm, and thickness is 10nm; The conductivity of the ZnO layer that mixes is 0.8 * 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 25% than using gate-shaped electrode.
Embodiment 6:
High resistance nesa coating barrier layer can be the higher sull of resistivity, as: TiO
2Or Al
2O
3, SiO
2Film.High electricity is led ITO or the other materials that the nesa coating conductive layer can adopt with the foregoing description.Make nesa coating barrier layer (G) earlier, THICKNESS CONTROL is 2～10nm.And then press the method that the foregoing description adopts, make 150～750nm or thicker nesa coating conductive layer (H).Make the preceding electrode (K) of metal by example 1 at last.
Work as TiO
2The resistivity on barrier layer is higher than 1000 Ω .cm, and thickness is 2nm; The conductivity of ITO layer is 0.8 * 10
4(Ω .cm)
-1, when thickness was 600nm, conversion efficiency was higher by about 35% than using gate-shaped electrode.
Claims (3)
1. crystal silicon solar energy battery, its structure are back electrode/be shaped on the crystalline silicon/preceding electrode of n-p knot, and electrode is an electrode before the nesa coating before it is characterized in that.
2. solar cell as claimed in claim 1 is characterized in that the preceding electrode of nesa coating is led the nesa coating conductive layer by high electricity and high resistance nesa coating barrier layer constitutes.
3. solar cell as claimed in claim 2 is characterized in that it is 10 that high electricity is led nesa coating conductive layer employing doping content
19-10
21/ cm
3ITO or ZnO or SnO
2Or Cd
2SaO
4Polycrystal film; Plain SnO is adopted on high resistance nesa coating barrier layer
2Or ZnO or Zn
2SnO
4Polycrystal film or SnO
2Attitude film or TiO
2Or Al
2O
3Or SiO
2Film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011290137A CN1180486C (en) | 2001-10-31 | 2001-10-31 | Silicon solar cell of nesa with transparent conductive folm front electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011290137A CN1180486C (en) | 2001-10-31 | 2001-10-31 | Silicon solar cell of nesa with transparent conductive folm front electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1416179A true CN1416179A (en) | 2003-05-07 |
| CN1180486C CN1180486C (en) | 2004-12-15 |
Family
ID=4668820
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011290137A Expired - Fee Related CN1180486C (en) | 2001-10-31 | 2001-10-31 | Silicon solar cell of nesa with transparent conductive folm front electrode |
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2001
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