CN1416145A - Inductor with low substrate wastage - Google Patents
Inductor with low substrate wastage Download PDFInfo
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- CN1416145A CN1416145A CN 02154862 CN02154862A CN1416145A CN 1416145 A CN1416145 A CN 1416145A CN 02154862 CN02154862 CN 02154862 CN 02154862 A CN02154862 A CN 02154862A CN 1416145 A CN1416145 A CN 1416145A
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Abstract
The inductance with low substrate wastage is composed of the substrate, the multiple p-type adulteration areas and the multiple n-type adulteration areas, the insulation layer and the metallic coil. The p-type adulteration areas and the multiple n-type adulteration areas are alternately formed in the substrate. The insulation layer is formed on the substrate, and the metallic coil is formed on the insulation layer. The insulation layer insulates the metallic coil from the multiple p-type and n-type adulteration area. The multiple p-type and n-type adulteration area are arranged in the mode perpendicular to the metallic coil.
Description
Technical field
The present invention relates to a kind of inductance, relate in particular to the low substrate loss inductance of a kind of semiconductor integrated circuit technology manufacturing.
Background technology
Passive component as inductance or transformer, is widely used in microwave (microwave) or the high frequency wireless communication line.Because the semiconductor integrated circuit improvement of Manufacturing Technology, and under the system applies demand of small size, low cost, high integration, passive component is integrated in the one chip gradually.In chip, inductance element designs on the dielectric substrate of high impedance or almost noenergy loss usually, as GaAs (gallium arsenide, GaAs), to obtain the inductance element of the high quality factor and the high natural frequency of vibration, but because the cost of this type of substrate is too high, major part also is to use low-impedance silicon substrate (impedance is about the 0.01-10ohm-cm grade), to reduce chip cost.
Please refer to Fig. 1, Fig. 2 and Fig. 3, Fig. 1 is the schematic diagram of existing silicon substrate inductance 13, Fig. 2 is Fig. 1 silicon substrate inductance 13 profiles along tangent line 2-2, Fig. 3 is the schematic diagram of the equivalent electric circuit of Fig. 1 silicon substrate inductance 13, wherein Ls and Rs are respectively the inductance value and the resistance values of inductance 14, Cox is the parasitic capacitance of 10 of inductance 14 and substrates, and Csub and Rsub then are parasitic capacitance and the resistance that substrate 10 is caused.As shown in Figures 1 and 2, inductance 14 utilizes a plain conductor to form in the mode of spiral surrounding, has an insulating barrier 12 to be used for isolating inductance 14 and substrate 10 between inductance 14 and the substrate 10, generally uses silicon dioxide (SiO
2) as the material of insulating barrier 12.Inductance 14 comprises two end points, electric current is flowed into by an end, and flow out from the other end, when if the electric current on the inductance 14 flows in a clockwise direction, can produce a magnetic field penetration substrate 10, just can produce counterclockwise induction (image) electric current 18 on the substrate 10, or be called eddy current (eddy current), induced current 18 will cause energy loss.
Please refer to Fig. 4, Fig. 5 and Fig. 6, Fig. 4 is the schematic diagram of depletion region overcoat induction structure 21, and Fig. 5 is the profile of Fig. 4 induction structure 21 along tangent line 5-5, and Fig. 6 is the schematic diagram of the equivalent electric circuit of Fig. 4 induction structure 21, succinct for what illustrate, components identical is used identical Reference numeral among the figure.Because induced current 18 causes energy loss, in the prior art of Fig. 4 to Fig. 6, (patterned GroundShield, PGS) overcoat 16, as Fig. 4 and shown in Figure 5 to use polysilicon or metal to form a pattern type ground connection between inductance 14 and substrate 10.Because groove is arranged between the strip conductor of pattern type ground protection layer 16 to be separated, and the sense of current on its arrangement mode and the inductance 14 is orthogonal, can prevent the induced current 18 that cause in the magnetic field of inductance 14, reduce the energy loss on the substrate 10, to improve the quality factor of inductance 14.Though yet use pattern type ground protection layer 16 can prevent the induced current 18 that cause in the magnetic field of inductance 14, but also shorten simultaneously because of the distance between inductance 14 and the overcoat 16, and the parasitic capacitance of increasing inductance 14, make the natural frequency of vibration of inductance 14 reduce, reduced the frequency application scope of inductance 14.Because it is big that Cox becomes, the parasitic capacitance value of the induction structure of pattern type ground protection layer is greater than existing silicon substrate induction structure, and the product root side of the natural frequency of vibration of inductance 14 and parasitic capacitance value and inductance value is inversely proportional to, the product value of parasitic capacitance value and inductance value is big more, and then the natural frequency of vibration of inductance 14 is more little.
From the above, use the existing designed induction structure 13 of silicon substrate,, cause energy loss, cause the quality factor of inductance 14 to reduce because the magnetic field of inductance 14 produces induced current 18 on substrate 10.Though and use polysilicon or metal level come layout type ground protection layer 16 can prevent the induced current 18 that cause in the magnetic field of inductance 14, but also shorten simultaneously because of the distance between inductance 14 and the overcoat 16, and the parasitic capacitance of increasing inductance 14, make the natural frequency of vibration of inductance 14 reduce, reduced the frequency application scope of inductance 14.
Summary of the invention
Therefore main purpose of the present invention provides the low substrate loss inductance of a kind of semiconductor integrated circuit technology manufacturing, to address the above problem.
The invention provides a kind of inductance, it comprises a substrate, and a plurality of p type doped regions and a plurality of n type doped region are formed in this substrate in the mode that replaces, and an insulating barrier is formed at the top of this substrate, and a wire coil, is formed on this insulating barrier.Wherein this insulating barrier can be isolated this wire coil and these a plurality of p types, n type doped region, and arrangement mode and this wire coil of these a plurality of p types, n type doped region are orthogonal.
Description of drawings
Fig. 1 is the schematic diagram of existing silicon substrate induction structure;
Fig. 2 is the profile of Fig. 1 silicon substrate induction structure along tangent line 2-2;
Fig. 3 is the schematic diagram of the equivalent electric circuit of Fig. 1 induction structure;
Fig. 4 is the schematic diagram of the induction structure of pattern type ground protection layer;
Fig. 5 is the profile of Fig. 4 induction structure along tangent line 5-5;
Fig. 6 is the schematic diagram of the equivalent electric circuit of Fig. 4 induction structure;
Fig. 7 is the schematic diagram of the low substrate loss induction structure of the present invention;
Fig. 8 is the profile of Fig. 7 induction structure along tangent line 8-8;
Fig. 9 is the schematic diagram of the equivalent electric circuit of Fig. 7 induction structure;
Figure 10 is the schematic diagram of another low substrate loss induction structure of the present invention; And
Figure 11 is the profile of Figure 10 induction structure along tangent line 11-11.
Description of reference numerals in the accompanying drawing is as follows:
10 substrates, 12 insulating barriers
13 existing silicon substrate induction structure 14 inductance
16 poly-silicon pattern type ground protection layers, 18 induced current
20 n+ doped regions, 21 pattern type ground protection layer inductance
Ring insulation blocking circle in the 22 p+ doped regions 24
26 outer shroud insulation blocking circles, 28 X-shaped metal wires
30 depletion regions, 31 low substrate loss induction structures
32 n type traps, 33 low substrate loss inductance second structures
34 depletion regions
Embodiment
Please refer to Fig. 7 and Fig. 8, Fig. 7 is the schematic diagram of the low substrate loss induction structure 31 of the present invention, and Fig. 8 is the profile of Fig. 7 induction structure 31 along tangent line 8-8.The present invention is low, and substrate loss induction structure 31 is on a p type substrate 10 top layers, use n type and the formed n+ doped region 20 of two kinds of dopants of p type and a p+ doped region 22 of high concentration, wherein contain a plurality of n+ strip conductors in the n+ doped region 20, and also contain a plurality of p+ strip conductors in the p+ doped region 22.Strip conductor in n+ doped region 20 and the p+ doped region 22 is arranged in the mode that replaces mutually, between just per two n+ strip conductors a p+ strip conductor is arranged, and a n+ strip conductor is also arranged between per two p+ strip conductors, and between n+ strip conductor and p+ strip conductor, there is a groove that it is separated.There is an insulating barrier 12 that itself and the formed inductance 14 of a wire coil are isolated in the top of n+ doped region 20 and p+ doped region 22.In the present embodiment, inductance 14 can be a balanced-to-unbalanced transformer (balanced-unbalancedtransformer, the wire coil of arbitrary primary side BALLN).
As shown in Figure 7, the n type of use high concentration and the formed n+ doped region 20 of two kinds of dopants of p type and a p+ doped region 22 are realized pattern type ground protection layer, strip conductor in n+ doped region 20 and the p+ doped region 22 is arranged in the mode that p type n type interts, and the flow direction of electric current is orthogonal on the orientation of strip conductor and the inductance 14, because when there is electric current at inductance 14 upper reaches, can produce a magnetic field penetration substrate 10, just can produce an induced current that flows on the substrate 10 in the other direction, this induced current will cause energy loss, and the strip conductor in n+ doped region 20 and the p+ doped region 22 is to be used for blocking the induced current that the magnetic field of inductance 14 is produced on substrate 10.
Because existing polysilicon or the metal level of using realized pattern type ground protection layer 16, can cause the parasitic capacitance value of inductance 14 belows to increase, and reduce the natural frequency of vibration of inductance 14.In induction structure of the present invention, can produce a depletion region (depletionregion) 30 between the pn knot of n+ doped region 20 and p type substrate 10, in order to control the degree of depth of depletion region 30, between n+ doped region 20 and p+ doped region 22, add a reversed bias voltage, as shown in Figure 8, just n+ doped region 20 connects a high voltage, and p+ doped region 22 connects a low-voltage, usually this low-voltage is a ground connection, utilizes this reversed bias voltage can control the degree of depth of the depletion region 30 between pn knot in the substrate 10.Because the depletion region 30 of pn knot contains a depletion region capacitance, this depletion region capacitance is series at the parasitic capacitance between substrate and inductance, and whole equivalent capacity is reduced.In addition; in Fig. 7; pattern type ground protection layer periphery contained two ring-type insulation blocking circles (guard ring) in addition; the dopant of wherein interior ring 24 is identical with n+ doped region 20; and be connected to this high voltage; the dopant of external toroidal ring 26 is then identical with p+ doped region 22, and receives this low-voltage.The method that p+ doped region 22 and external toroidal ring 26 are connected to this low-voltage is shown in X-shaped metal wire 28 among the figure, and each netted lattice 25 of Fig. 7 are the contact that metal wire 28 is connected to p+ doped region 22 and external toroidal ring 26.
Please refer to Fig. 9, Fig. 9 is the equivalent circuit diagram of Fig. 7, and wherein Ls and Rs are respectively the inductance value and the resistance value of inductance 14, and Cox is the parasitic capacitance of 10 of inductance 14 and substrates, Rsub is the resistance that Low ESR substrate 10 is caused, and Cd is the depletion region capacitance that pn ties the depletion region 30 that is produced.By in the equivalent circuit diagram of Fig. 9 as can be known, the depletion region capacitance Cd series inductance 14 of the depletion region 30 that pn in the substrate 10 knot forms and the parasitic capacitance Cox of 10 of substrates because the equivalent capacity Ct after connecting can diminish, its relational expression is
1/Ct=1/Cox+1/Cd utilizes the depletion region capacitance of depletion region 30 to reduce the parasitic capacitance of inductance 14 below integral body, and the natural frequency of vibration that can improve inductance 14 is to expand the range of application of inductance 14.
Please refer to Figure 10, Figure 10 is the schematic diagram of another low substrate loss induction structure 33 of the present invention.As shown in figure 10, in p type substrate 10 top layers, form n type trap 32 with low concentration n type dopant earlier, then in n type trap 32 zones, the n type of use high concentration and the formed n+ doped region 20 of two kinds of dopants of p type and p+ doped region 22 are realized pattern type ground protection layer, wherein contain a plurality of n+ strip conductors in the n+ doped region 20, and also contain a plurality of p+ strip conductors in the p+ doped region 22, strip conductor in n+ doped region 20 and the p+ doped region 22 is arranged in the mode that replaces mutually, between just per two n+ strip conductors a p+ strip conductor is arranged, and a n+ strip conductor is also arranged between per two p+ strip conductors, and between n+ strip conductor and p+ strip conductor, there is a groove that it is separated.In n+ doped region 20 and the p+ doped region 22 on the orientation of strip conductor and the inductance 14 flow direction of electric current be orthogonal, when there is electric current at inductance 14 upper reaches, can produce a magnetic field penetration substrate 10, just can produce an induced current that flows in the other direction on the substrate 10, and the strip conductor in n+ doped region 20 and the p+ doped region 22 is to be used for blocking the induced current that the magnetic field of inductance 14 is produced on substrate 10.
Please refer to Figure 11, Figure 11 is the profile of Figure 10 induction structure along tangent line 11-11.Because existing polysilicon or the metal level of using realized pattern type ground protection layer 16, can cause the parasitic capacitance value of inductance 14 belows to increase, and reduce the natural frequency of vibration of inductance 14.In order to reduce the parasitic capacitance of inductance 14 below integral body, in second embodiment of induction structure of the present invention, the pn knot of utilization between p+ doped region 22 and n type trap 32 produces a depletion region 30, depletion region 30 contains a depletion region capacitance, because this depletion region capacitance is series at the parasitic capacitance of 14 of substrate 10 and inductance, make whole equivalent capacity reduction.As shown in figure 11, between n+ doped region 20 and p+ doped region 22, add a reversed bias voltage, just n+ doped region 20 connects a high voltage, p+ doped region 22 connects a low-voltage, usually this low-voltage is a ground connection, so, just, can utilize the degree of depth of the depletion region 30 between the pn knot in this reversed bias voltage control substrate 10.In addition, the pn that n type trap 32 and p type substrate are 10 ties formed depletion region 34, can isolate inductance 14 and other circuit, avoids interfering with each other.
In Figure 10; two ring-type insulation blocking circles are also contained in pattern type ground protection layer periphery, and wherein the dopant of interior ring 24 is identical with n+ doped region 20, and is connected to this high voltage; the dopant of external toroidal ring 26 is then identical with p+ doped region 22, and receives this low-voltage.With different among Fig. 7 be, the interior ring 24 of the ring-type insulation blocking circle among Figure 10 is positioned within the n type trap 32, and external toroidal ring 26 then is positioned at outside the n type trap 32.And connect p+ doped region 22 and external toroidal ring 26 to the method for this low-voltage shown in X metal wire 28 among the figure, and each netted lattice 25 of Figure 10 are the contact that metal wire 28 is connected to p+ doped region 22 and external toroidal ring 26.
From the above, two embodiment of the low substrate loss induction structure of the present invention all use cheaply, and Cmos transistor (CMOS) technology of silicon substrate and standard designs, chip cost can be reduced, also technology must be do not changed.In the low substrate loss induction structure of the present invention, utilize two kinds of high concentration n types and the formed pattern type ground protection of p type dopant layer, can prevent the induced current that the magnetic field of inductance 14 is caused on substrate 10,, improve the quality factor of inductance 14 to reduce the energy loss on the substrate 10.N+ type doped region 20 and p+ type doped region 22 in this pattern type ground protection layer add a reversed bias voltage, the degree of depth of the depletion region 30 that the pn knot in the control substrate 10 produces, depletion region capacitance in the depletion region 30 can reduce the whole parasitic capacitance of inductance 14 belows, improves the natural frequency of vibration of inductance 14 and the range of application of inductance 14.The wherein a kind of and substrate 10 of two kinds of doped regions in the pattern type ground protection layer belongs to identical form in addition, as the n+ doped region 20 in p+ doped region 22 in the p type substrate 10 or the n type trap 32, can make substrate 10 zones of inductance 14 belows see through strip conductor, and make current potential to be evenly distributed.
Compared with prior art, induction structure of the present invention mainly is to utilize n type and two kinds of high-concentration dopant districts of p type to realize pattern type ground protection floor, the energy loss that induced current caused that when penetrating substrate, produces except the magnetic field that can prevent inductance, also can avoid existing polysilicon or the metal level of using to realize pattern type ground protection layer, cause the parasitic capacitance value of inductance below to increase, and reduce the natural frequency of vibration of inductance.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (9)
1. inductance element, it comprises:
One substrate;
A plurality of strip doped regions, the mode that replaces with p type, n type is formed in this substrate;
One insulating barrier is formed at the top of this substrate; And
One wire coil is formed on this insulating barrier;
Wherein this insulating barrier is isolated this wire coil and these a plurality of strip doped regions, and the arrangement mode of these a plurality of strip doped regions is to be orthogonal with this wire coil.
2. inductance element as claimed in claim 1, wherein these a plurality of strip doped regions form a pattern type ground protection layer.
3. inductance element as claimed in claim 2, wherein these a plurality of p type strip doped regions are connected to a low-voltage, and these a plurality of n type strip doped regions are connected to a high voltage, are used for increasing the depletion region of p-n junction.
4. inductance element as claimed in claim 3, it comprises ring doped region in addition, it is a n type doped region, be located at the periphery of this pattern type ground protection layer, and be connected in this high voltage, and an external toroidal ring doped region, it is a p type doped region, be located at the periphery of ring doped region in this, and be connected in this low-voltage.
5. inductance element as claimed in claim 1, wherein this wire coil is arbitrary primary side of a transformer.
6. inductance element as claimed in claim 5, wherein this transformer is a balanced-to-unbalanced transformer.
7. inductance element as claimed in claim 1, wherein this substrate is a p type substrate.
8. inductance element as claimed in claim 7, it comprises a n type trap in addition, be formed on this substrate, and these a plurality of p types and n type doped region is formed in this n type trap.
9. inductance element, it comprises:
One p type substrate;
One n type trap is formed on this p type substrate;
A plurality of strip doped regions, the mode that replaces with p, n type is formed in this n type trap;
One insulating barrier is formed at the top of this substrate; And
One wire coil is formed on this insulating barrier;
Wherein this insulating barrier is isolated this wire coil and these a plurality of strip doped regions, and the arrangement mode of these a plurality of strip doped regions is to be orthogonal with this wire coil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02154862 CN1290127C (en) | 2002-12-03 | 2002-12-03 | Inductor with low substrate wastage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02154862 CN1290127C (en) | 2002-12-03 | 2002-12-03 | Inductor with low substrate wastage |
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|---|---|
| CN1416145A true CN1416145A (en) | 2003-05-07 |
| CN1290127C CN1290127C (en) | 2006-12-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02154862 Expired - Lifetime CN1290127C (en) | 2002-12-03 | 2002-12-03 | Inductor with low substrate wastage |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1295718C (en) * | 2003-12-25 | 2007-01-17 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit inductance |
| CN100341133C (en) * | 2004-10-28 | 2007-10-03 | 复旦大学 | Optimized design method for PN junction underlay isolation on-chip inductance |
| CN101640196A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Integrated inductor |
| CN101471343B (en) * | 2007-12-29 | 2011-05-11 | 瑞昱半导体股份有限公司 | Integrated inductance structure |
| CN101533839B (en) * | 2009-04-21 | 2012-05-23 | 上海宏力半导体制造有限公司 | Inductance device and manufacturing method thereof |
| CN101510547B (en) * | 2008-01-16 | 2013-03-27 | 雷凌科技股份有限公司 | Sliced electromagnetic cage for inductors |
| US8471357B2 (en) | 2007-12-07 | 2013-06-25 | Realtek Semiconductor Corp. | Integrated inductor structure |
| CN103474419A (en) * | 2012-06-05 | 2013-12-25 | 飞思卡尔半导体公司 | Inductive element with interrupter region and method for forming |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
| CN105575959A (en) * | 2014-11-21 | 2016-05-11 | 威盛电子股份有限公司 | Integrated circuit device |
| CN110349939A (en) * | 2019-07-17 | 2019-10-18 | 上海华虹宏力半导体制造有限公司 | Induction structure and preparation method thereof |
| JP7545503B2 (en) | 2023-02-08 | 2024-09-04 | 合肥晶合集成電路股▲ふん▼有限公司 | Semiconductor Devices |
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| CN108198800B (en) * | 2017-12-28 | 2020-06-05 | 建荣半导体（深圳）有限公司 | high-Q-value and interference-resistant on-chip integrated inductor, substrate isolation structure thereof and chip |
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- 2002-12-03 CN CN 02154862 patent/CN1290127C/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1295718C (en) * | 2003-12-25 | 2007-01-17 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit inductance |
| CN100341133C (en) * | 2004-10-28 | 2007-10-03 | 复旦大学 | Optimized design method for PN junction underlay isolation on-chip inductance |
| US8471357B2 (en) | 2007-12-07 | 2013-06-25 | Realtek Semiconductor Corp. | Integrated inductor structure |
| CN101471343B (en) * | 2007-12-29 | 2011-05-11 | 瑞昱半导体股份有限公司 | Integrated inductance structure |
| CN101510547B (en) * | 2008-01-16 | 2013-03-27 | 雷凌科技股份有限公司 | Sliced electromagnetic cage for inductors |
| CN101533839B (en) * | 2009-04-21 | 2012-05-23 | 上海宏力半导体制造有限公司 | Inductance device and manufacturing method thereof |
| CN101640196A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Integrated inductor |
| CN103474419B (en) * | 2012-06-05 | 2017-08-04 | 飞思卡尔半导体公司 | Inductive element with interruptive area and forming method thereof |
| CN103474419A (en) * | 2012-06-05 | 2013-12-25 | 飞思卡尔半导体公司 | Inductive element with interrupter region and method for forming |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
| CN104064547B (en) * | 2014-06-26 | 2017-02-15 | 珠海市杰理科技股份有限公司 | Inductor substrate isolation structure of integrated circuit |
| CN105575959A (en) * | 2014-11-21 | 2016-05-11 | 威盛电子股份有限公司 | Integrated circuit device |
| CN107658288A (en) * | 2014-11-21 | 2018-02-02 | 威盛电子股份有限公司 | Integrated circuit device |
| CN105575959B (en) * | 2014-11-21 | 2018-06-15 | 威盛电子股份有限公司 | Integrated circuit device |
| CN107658288B (en) * | 2014-11-21 | 2020-02-07 | 威锋电子股份有限公司 | Integrated circuit device |
| CN110349939A (en) * | 2019-07-17 | 2019-10-18 | 上海华虹宏力半导体制造有限公司 | Induction structure and preparation method thereof |
| JP7545503B2 (en) | 2023-02-08 | 2024-09-04 | 合肥晶合集成電路股▲ふん▼有限公司 | Semiconductor Devices |
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