CN108198800B - high-Q-value and interference-resistant on-chip integrated inductor, substrate isolation structure thereof and chip - Google Patents
high-Q-value and interference-resistant on-chip integrated inductor, substrate isolation structure thereof and chip Download PDFInfo
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- 238000002955 isolation Methods 0.000 title claims abstract description 48
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
The invention belongs to the field of radio frequency integrated circuits, and discloses an on-chip integrated inductor with high Q value and interference resistance, a substrate isolation structure and a chip thereof, wherein the substrate isolation structure comprises: the inductor substrate comprises an inductor substrate chassis arranged in the middle area, and a DNW ring and a Psub ring which are sequentially arranged outside the inductor substrate chassis; the DNW ring and the Psub ring keep a certain distance to form a reverse-biased diode DNP structure, so that the load resistance of the P substrate is increased, the noise from the external P substrate is isolated, and the anti-interference capability of the inductor is improved. The inductance substrate isolation structure adopted by the invention not only can effectively inhibit the eddy current effect of the inductor working in a high-frequency state, but also can improve the anti-interference capability of the inductor; thereby greatly improving the Q value of the integrated inductor. The invention can be realized in the existing common process without using a special process with high resistivity, thereby greatly reducing the manufacturing cost of the chip and improving the competitiveness of the same industry.
Description
Technical Field
The invention belongs to the field of radio frequency integrated circuits, and particularly relates to an on-chip integrated inductor with high Q value and interference resistance, a substrate isolation structure and a chip thereof.
Background
In the Radio Frequency Integrated Circuit (RFIC) process, the manufacturing of a high-Q passive device inductor with interference resistance is very important. However, the inductors integrated on-chip are the most difficult parts to integrate in passive devices. The stability of the RF circuit module and the circuit design efficiency can be greatly improved by using the high-Q and interference-resistant on-chip integrated inductor. In RFICs in silicon technologies (CMOS and BiCMOS), noise is easily coupled to the inductor coil through the substrate due to the low substrate resistivity ratio, which causes the inductor to have poor stability during operation and a reduced Q value. For example: in the VCO of the RF circuit Synthesizer, it is highly desirable to achieve a Q value of 10 to 15, or even higher. Therefore, it is particularly challenging to fabricate high Q integrated inductors.
The design of the isolation structure of the inductor substrate is an important link for improving the Q value of the inductor. The good substrate isolation structure can effectively inhibit the eddy current effect of the inductor working in a high-frequency state and greatly improve the anti-interference capability of the inductor.
At present, a well isolation technology is adopted in some designs, specifically, an inductance coil is arranged on an N-well layer, noise from an external P substrate is isolated through the N-well layer, and the anti-interference capability is effectively improved. However, the electron mobility of the N-type semiconductor material is greater than that of the P-type semiconductor material, i.e., the resistivity of the N-well layer is smaller. When the inductor works in a high-frequency state, a stronger eddy current effect and more heat are easily generated; thereby reducing the quality factor Q of the inductor.
At present, a P-substrate isolation technology is also adopted in some designs, and an inductance coil is directly manufactured on a P substrate of a wafer, because at least the resistivity of the P substrate is larger than that of an N-type semiconductor material, the inhibition capability of the eddy current effect is slightly improved. However, the resistivity of the substrate of the wafer P substrate is only (8-12) Ohm-cm, so that the substrate is easily coupled with noise from the outside, the anti-interference capability is not high, and finally the quality factor Q of the inductor is not high.
Disclosure of Invention
The embodiment of the invention aims to provide an on-chip integrated inductor with a high Q value and interference resistance, a substrate isolation structure and a chip thereof, and aims to solve the problem that the quality factor Q of the inductor is not high due to the fact that the existing integrated inductor is easily coupled with noise from the outside and weak in interference resistance.
The invention provides a substrate isolation structure of an on-chip integrated inductor with high Q value and interference resistance, which comprises: the inductor substrate comprises an inductor substrate chassis arranged in the middle area, and a DNW ring and a Psub ring which are sequentially arranged outside the inductor substrate chassis; the DNW ring and the Psub ring keep a certain distance to form a reverse-biased diode DNP structure, so that the load resistance of the P substrate is increased, the noise from the external P substrate is isolated, and the anti-interference capability of the inductor is improved.
Preferably, the DNW ring is an unclosed ring with a small opening at the upper end. The inductor is mainly used for generating excessive tail energy to the substrate when the inductor works at high frequency.
Preferably, the Psub ring is a closed ring.
Further preferably, the DNW ring and the Psub ring keep a certain small distance, so that a reverse-biased diode DNP structure can be formed, the load resistance of a P substrate is increased, a certain isolation effect on noise from an external P substrate is achieved, and the anti-interference capability of an inductor is improved.
Preferably, the DNW ring is arranged in and connected with a high potential; the Psub ring is disposed externally and connected to a "0" potential GND.
Preferably, the inductance substrate chassis is square in shape. Because the square is the largest area in the same wide and long pattern, the area of the substrate isolation structure under the inductor is slightly larger, the noise isolation effect is better, and the improvement of the Q value of the inductor is helpful for the inductor.
Preferably, the inductive substrate chassis comprises: the device comprises an active area, polycrystalline silicon, N-type injection, P-type injection, a barrier layer, a contact hole and a metal layer; the DNW ring comprises: the device comprises an active region, an N well, a deep well, an N-type injection, a contact hole and a metal layer; the Psub ring includes: an active region, a P-type implant, a contact hole and a metal layer.
Further preferably, the active region includes: a P-type active region and an N-type active region; the P-type active region and the N-type active region are arranged in a fork shape. The fork structure enables the AA resistor and the Poly resistor to be crossed and not overlapped, and the high central symmetry of the substrate isolation structure pattern layer can be kept.
Preferably, the metal layer is arranged around the P-type active region and the N-type active region which are arranged in a fork shape; and the metal layer M1 connects it to GND having a potential of "0"; the metal layer is a ring with an upper end opening which is not closed.
Further preferably, the P-type active regions are located on four sides and four diagonal lines of the chassis, the polysilicon and the N-type active region are arranged in a fork manner, and vertically and horizontally distributed in four right triangle regions equally divided by the P-type active regions on the diagonal lines; the N-type active region is not in contact with the P-type active region. The main reason for the disconnection between the two parts is that when the inductor works at high frequency, the alternating magnetic field in the centremost area is strongest, so that the eddy current effect is easily caused, therefore, the disconnection structure can induce the energy in the centremost area to be gradually diffused and released to the periphery, and finally the purpose of preventing the eddy current effect is achieved.
The invention also provides an on-chip integrated inductor which comprises an inductance coil and a substrate isolation structure arranged below the inductance coil, wherein the substrate isolation structure is the substrate isolation structure.
The invention also provides a radio frequency integrated chip which comprises the on-chip integrated inductor.
The inductance substrate isolation structure adopted by the invention not only can effectively inhibit the eddy current effect of the inductor working in a high-frequency state, but also can improve the anti-interference capability of the inductor; thereby greatly improving the Q value of the integrated inductor. The invention can be realized in the existing common process without using a special process with high resistivity, thereby greatly reducing the manufacturing cost of the chip and improving the competitiveness of the same industry.
Drawings
FIG. 1 is a schematic diagram of an analytical model for obtaining an on-chip integrated inductor by using a spiral integrated inductor in the prior art;
fig. 2 is a schematic diagram of a substrate isolation structure of an on-chip integrated inductor provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of a shape structure of DNW ring and Psub ring layers in an on-chip integrated inductor according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a square inductor substrate chassis in an on-chip integrated inductor according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a P-type active region and a polysilicon in an on-chip integrated inductor, which are symmetric about a center, according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of the shape of polysilicon in the on-chip integrated inductor according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram of a strip-shaped active region in the middle of a substrate base plate and a barrier layer covered on polysilicon in an on-chip integrated inductor provided by an embodiment of the present invention;
fig. 8 is a schematic diagram of an analytic model of an on-chip integrated inductor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In an RFIC (radio frequency integrated circuit) in a silicon process (CMOS and BiCMOS), in order to manufacture an integrated inductor with a high Q value and interference resistance, a substrate isolation structure design of the inductor becomes an important link for improving the Q value of the inductor. The good substrate isolation structure can effectively inhibit the eddy current effect of the inductor working in a high-frequency state and can greatly improve the anti-interference capability of the inductor. However, the resistivity of the wafer substrate is very low, generally only (8-12) Ohm-cm, which is far from the design requirement. If the P substrate is directly used as an isolation structure of the inductor, noise is easily coupled to the inductor coil through the substrate, so that the stability of the inductor during working is poor, and the Q value is reduced. If the well isolation technology is adopted, the inductance coil is arranged on the N well layer, although the noise from the external P substrate can be isolated through the N well layer, and the anti-interference capacity of the inductance is improved. However, the electron mobility of the N-type semiconductor material is greater than that of the P-type semiconductor material, i.e., the resistivity of the N-well layer is lower than that of the P-substrate. When the inductor works in a high-frequency state, stronger eddy current effect and more heat are easily generated. Thereby reducing the quality factor Q of the inductor.
At present, spiral integrated inductor is generally adopted for manufacturing integrated inductor on chip, and quality factor of inductor
The inductance analytical model is shown in FIG. 1, wherein RSIs a series resistance of the metal coil itself, CSCapacitor being a metal coil element, Cox1And Cox2Respectively, the capacitance, R, between the metal coil and the substratesub1And Rsub2Respectively, the load resistance of the substrate itself, Csub1And Csub2Respectively the load capacitance of the substrate itself. From the equation for the quality factor Q of the inductor, it can be seen that: q is the resistance R of the following coilSAnd a capacitor CSInversely proportional; as can be seen from the analysis model of FIG. 1, in order to ensure the inductance lineThe energy in the entire path from the PLUS terminal of the ring to the MINUS terminal is sufficient to reduce the electromagnetic loss of the inductor to the substrate. Therefore, it is required to reduce the parasitic capacitance C between the coil and the P substrateox1And Cox2It is further desirable to increase the substrate load resistance Rsub1And Rsub2. The most straightforward approach is to use a high resistance substrate (2K Ohm-cm) to reduce substrate parasitics, but this approach is not compatible with CMOS and BiCMOS processes, in which the substrate resistivity typically does not exceed 30 Ohm-cm. For example: the substrate resistivity of the SMIC process is only (8-12) Ohm-cm. The integrated inductor works in a high-frequency state, so that a stronger eddy current effect and more heat are easily generated; thereby reducing the quality factor Q of the inductor. In addition, the integrated inductor is easily coupled to noise from an external P substrate through the P substrate, so that the output frequency of the inductor is unstable, and the anti-interference capability is poor.
Therefore, to increase the Q value of the inductor, the parameters in the above aspects must be optimized. The invention provides an on-chip integrated inductor comprising: inductance coils, the substrate isolation structure of setting in inductance coils below, wherein, substrate isolation structure includes: as shown in fig. 2, the substrate isolation structure provided by the present invention mainly optimizes the resistivity and isolation of the substrate under the inductor coil, so as to increase the load impedance of the P substrate and the anti-interference capability of the inductor.
The structure of the present invention for specific layout of the isolation structure of the inductor substrate provided in the embodiment of the present invention is shown in fig. 3, and mainly includes 9 layers, which are respectively: the manufacturing method comprises the steps of forming an Active Area (AA), an N-well (NW), a deep well (DNW), Polysilicon (POLY), N-type injection (SN), P-type injection (SP), a barrier layer (SAB), a contact hole (CT) and a metal layer (M1), forming the deep well (DNW) through N-type injection on a P substrate, forming a common N-well (NW) and an N-type active area, and finally connecting the metal layer (M1) through contact holes (CT) formed in the Active Area (AA) and the Polysilicon (POLY) so as to achieve the purpose of providing contact points for the deep well (DNW), the N-type active area, the P-type active area and the Polysilicon (POLY).
The inductance substrate isolation structure of the invention is divided into two parts: an inductor substrate 1 having a part of a middle region; the other part is two isolating rings outside the chassis. The inductor substrate chassis 1 comprises 7 pattern layers, which are respectively: the Active Area (AA)100, the Polysilicon (POLY)101, the N-type implantation (SN) 102, the P-type implantation (SP)103, the barrier layer (SAB)104, the contact hole (CT)105 and the metal layer (M1) 106 are used for manufacturing an AA resistor and a Poly resistor under the induction coil so as to achieve the purpose of increasing the load resistance value of the substrate. And the two spacer rings are DNW ring 2 and Psub ring 3, respectively, wherein DNW ring 2 comprises: an Active Area (AA)200, an N-well (NW)201, a deep well (DNW)202, an N-type implant (SN)203, a contact hole (CT)204, and a metal layer (M1) 205; and Psub ring 3 includes: an Active Area (AA)300, a P-type implant (SP)301, a contact hole (CT)302, and a metal layer (M1) 304.
The DNW ring 2 and the Psub ring 3 are characterized in that as shown in fig. 3, the Psub ring 3 formed by 4 layers of an active region (AA), a P-type implant (SP), a contact hole (CT) and a metal layer (M1) is a closed ring, while the DNW ring 2 is an unclosed ring with a small opening at the upper end, and is mainly used for discharging excessive tail energy generated by the inductor to a substrate when the inductor works at a high frequency. The size of the opening is determined according to the size of the inductance coil, and the larger the coil is, the larger the opening size is; the smaller the coil is, the smaller the opening size is, but the DRC size meeting the technological production needs to be ensured, meanwhile, the isolation effect is poor when the opening is too large, and the purpose of discharging tail energy cannot be achieved when the opening is too small.
In the embodiment of the present invention, the main shape feature of the inductive substrate chassis may be a square (as shown in fig. 4), or may be a regular polygon or a circle; preferably, the shape of the substrate chassis of the inductor is preferably square, and the effect of isolating noise is better because the area of the substrate isolation structure under the inductor is slightly larger, which is helpful for improving the Q value of the inductor, and the square is better because the area is the largest in the same wide and long pattern. However, sometimes, in order to save the chip area, the isolation structure of the inductor substrate with the same width and length is made into a polygon or a circle, and the area of four corners of the original square can be saved to put other circuit modules.
In embodiments of the present invention, the body structure consists of a fork structure of Active Area (AA) and Polysilicon (POLY), which makes AA resistor and POLY resistor cross and not overlap, and therefore it is better to use the fork structure in order to maintain the high degree of centrosymmetry of the patterned layer of the substrate isolation structure.
In the embodiment of the present invention, the shape of the active area 100(AA) is characterized as shown in fig. 4, and the active area 100 is composed of a P-type active area 1001 and an N-type active area 1002; the P-type active areas 1001 are distributed on two diagonal lines and the peripheral boundary of the substrate chassis, but the P-type active areas 1001 on the diagonal lines of the four corners are disconnected and not connected in the central area, as shown in fig. 5, the P-type active areas AA are located on the four diagonal lines, and the Polysilicon (POLY) and the N-type active areas AA are arranged in a fork manner, distributed in four right triangle areas equally divided by the P-type active areas AA on the diagonal lines, and are all arranged in a medium-small symmetrical manner with respect to the inductor coil. The main reason for the disconnection in the middle is that when the inductor works at high frequency, the alternating magnetic field in the centremost area is strongest, so that the eddy current effect is easily caused, therefore, the disconnection structure can induce the energy in the centremost area to diffuse and release towards the periphery step by step, and finally the purpose of preventing the eddy current effect is achieved. The N-type active regions are vertically and horizontally distributed in the four right-angle triangular regions, are not in contact with the P-type active regions, keep a certain distance, and the P-type active regions 1001 and the N-type active regions 1002 are not in contact with each other, so that a reverse-biased diode DNP structure is manufactured, and a certain distance needs to be kept. Finally, the P-type and N-type active regions are both connected to a potential "0" GND by the surrounding M1.
In the embodiment of the present invention, the shape and characteristics of the polysilicon 101 are as shown in fig. 6, and the polysilicon 101 is vertically and horizontally distributed in four right-angled triangular regions, and is not in contact with the P-type active region 1001 and the N-type active region 1002, and keeps a certain distance, and the purpose that the P-type active region and the N-type active region are not in contact is to make a back-biased diode DNP structure mentioned below, the distance between them should refer to the production process requirements, and the production process requirements of different wafer factories are also different, and accordingly, the distance only needs to satisfy the production process rules adopted by the project. The P-type active region 1001 and the N-type active region 1002 are arranged in a fork shape; finally, all the metal layers are connected to GND with the potential of 0 through the metal layer M1 on the periphery, and the metal layer M1 is a ring with an open top and is not closed.
As shown in fig. 7, the strip-shaped active region 100 and the polysilicon 101 in the middle of the inductor substrate chassis 1 of the present invention are covered with a barrier layer 104; the barrier layer 104 has a main function in the process of blocking doping on the upper surfaces of the active region and the polysilicon, so that the doping concentration on the surfaces of the active region and the polysilicon is too low to form a resistor body; in popular terms, the substrate chassis under the inductor is made into an N-type active area resistor, a P-type active area resistor and a POLY resistor. The resistivity of the resistors is between 200 and 1000 Ohm-cm, is dozens of and hundreds of times of the resistivity of a common P substrate, and the load resistance R of the P substrate is increasedsub1And Rsub2As shown in fig. 8.
In the embodiment of the present invention, the N-type active regions and the four diagonal lines in the four vertical triangular regions and the surrounding P-type active regions are kept at a small distance, so that a diode DNP structure with PN junction is formed, as shown in fig. 8, so that the load resistance of the P-substrate can be greatly increased by reversely biasing the diode.
In the embodiment of the invention, the inductance coil is arranged on the substrate chassis with high load resistivity, so that the energy loss is little; and the eddy current effect of the inductor working in a high-frequency state can be effectively inhibited, the performance stability is enhanced, and the Q value is greatly improved. The invention can be realized in the existing common process without using a special process with high resistivity, thereby greatly reducing the manufacturing cost of the chip and improving the competitiveness of the same industry.
In the embodiment of the invention, DNW ring 2 and Psub ring 3 are used as the isolation rings, DNW ring 2 is connected with high potential VDD; psub ring 3 is external and connected to a "0" potential GND. And the double rings keep a certain small distance, so that a reverse-biased diode DNP structure can be formed, the load resistance of the P substrate is increased, a certain isolation effect on noise from the external P substrate is achieved, and the anti-interference capability of the inductor is improved. Meanwhile, the invention uses DNW ring 2 with larger width W; compared with the ordinary NW ring, the DNW ring 2 in the present invention is fabricated several tens times as deep on the wafer as the ordinary NW ring; therefore, the anti-interference capability of the inductor can be greatly improved.
The embodiment of the invention also provides an on-chip integrated inductor which comprises an inductance coil and a substrate isolation structure arranged below the inductance coil, wherein the substrate isolation structure is the substrate isolation structure.
The embodiment of the invention also provides a radio frequency integrated chip which comprises the on-chip integrated inductor.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A substrate isolation structure of a high Q and interference tolerant on-chip integrated inductor, comprising:
the inductor comprises an inductor substrate chassis (1) arranged in the middle area, and a deep well ring (2) and a P-type substrate ring (3) which are sequentially arranged outside the inductor substrate chassis (1);
the inductive substrate chassis (1) comprises: the manufacturing method comprises the steps of forming an active region (100), polycrystalline silicon (101), N-type implantation (102), P-type implantation (103), a barrier layer (104), a contact hole (105) and a metal layer (106);
the deep well ring (2) comprises: the device comprises an active region (200), an N well (201), a deep well (202), an N-type injection (203), a contact hole (204) and a metal layer (205);
the P-type substrate ring (3) includes: an active region (300), a P-type implant (301), a contact hole (302) and a metal layer (304);
the deep well ring (2) and the P-type substrate ring (3) keep a certain distance to form a reverse-biased diode DNP structure;
the deep trap ring (2) is an unclosed ring with an opening at the upper end; the P-type substrate ring (3) is a closed ring;
the deep well ring (2) is arranged in the deep well ring and is connected with a high potential; the P-type substrate ring (3) is arranged outside and connected with zero potential.
2. A substrate isolation structure according to claim 1, wherein the inductive substrate chassis (1) is square in shape.
3. The substrate isolation structure of claim 1, wherein the active region (100) comprises: a P-type active region (1001) and an N-type active region (1002); the P-type active region (1001) and the N-type active region (1002) are arranged in a fork shape.
4. The substrate isolation structure of claim 1 or 2, wherein the metal layer (106) is disposed around the P-type active region (1001) and the N-type active region (1002) in a fork-like arrangement; and the metal layer connects it to zero potential; the metal layer (106) is a ring with an opening at the upper end.
5. The substrate isolation structure of claim 3, wherein the P-type active regions (1001) are located on four sides and four diagonal lines of the bottom plate, the polysilicon (101) and the N-type active region (1002) are arranged in a fork manner, and are vertically and horizontally distributed in four right triangle areas equally divided by the P-type active regions (1001) on the diagonal lines; the N-type active region (1002) is not in contact with the P-type active region (1001).
6. An on-chip integrated inductor comprising an inductor winding and a substrate isolation structure disposed below the inductor winding, wherein the substrate isolation structure is the substrate isolation structure of any one of claims 1-5.
7. A radio frequency integrated chip comprising the on-chip integrated inductor of claim 6.
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| CN1290127C (en) * | 2002-12-03 | 2006-12-13 | 威盛电子股份有限公司 | Inductor with low substrate wastage |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
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| CN102214640A (en) * | 2010-04-08 | 2011-10-12 | 联发科技股份有限公司 | Semiconductor device |
| US9218903B2 (en) * | 2013-09-26 | 2015-12-22 | International Business Machines Corporation | Reconfigurable multi-stack inductor |
| TWI622068B (en) * | 2015-02-02 | 2018-04-21 | 瑞昱半導體股份有限公司 | Integrated inductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1290127C (en) * | 2002-12-03 | 2006-12-13 | 威盛电子股份有限公司 | Inductor with low substrate wastage |
| CN104064547A (en) * | 2014-06-26 | 2014-09-24 | 珠海市杰理科技有限公司 | Inductor substrate isolation structure of integrated circuit |
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