CN1404136A - 增加低介电层涂布能力的方法 - Google Patents

增加低介电层涂布能力的方法 Download PDF

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CN1404136A
CN1404136A CN02126852A CN02126852A CN1404136A CN 1404136 A CN1404136 A CN 1404136A CN 02126852 A CN02126852 A CN 02126852A CN 02126852 A CN02126852 A CN 02126852A CN 1404136 A CN1404136 A CN 1404136A
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谢宗棠
蔡正原
黄稚铵
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United Microelectronics Corp
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Abstract

一种增加低介电层涂布能力的方法。本发明的方法包括：旋涂一蚀刻终止层在底材上，旋涂一吸附促进层在蚀刻终止层上。为了增加在蚀刻终止层与有机低介电层之间的涂布能力，在已经烘烤过的吸附促进层上进行预润湿的步骤，使得经过烘烤之后的吸附促进层的涂布品质可以增加，也可以增加在蚀刻终止层与低介电层之间的涂布能力。

Description

增加低介电层涂布能力的方法
(1)技术领域
本发明有关一种增加低介电层的涂布能力的方法。
(2)背景技术
在半导体制程技术的应用上，在目前正在制造中的是具有次微米(sub-micron)以及次半微米(sub-half-micron)的集成电路(integrated circuit)元件。而趋向于深次微米的技术(deep sub-micron technology)(如，包括小于0.35微米尺寸)，对于多层内连线技术而言是必须的。
因此，在集成电路晶片中，集成电路效能在深次微米中是做为在数百万个闸极(gate)以及晶体管(transistor)之间移动的电子信号的延迟时间(delaytime)。寄生电容(parasitic capacitance)与电阻效应(resistance effect)产生使得这些保护内连接线结构必须控制良好。由此趋势来看，最近是注重在低电阻值金属(例如，铜)的使用，此种金属与具有低介电常数(low dielectric constant，low-k dielectric)的绝缘材料在金属线之间连接。一低介电材料为一其介电常数比传统的介电材料为低的介电材料，如氟化硅玻璃(Fluornated Silicate Glass，FSG)，其介电常数值约为3.5。铜的导电性是非常的高且比其他的金属(如，铝)的电漂移(electromigration)要低。
在半导体制程技术中，内连接线层的制程是利用化学机械研磨(chemicalmechanical polishing，CMP)的方法，特别是当有数层以及导线本身的特性采用一高宽比(aspect ratio)(例如，导线是以0.25微米的宽以及1.0微米的高度)时。
在0.25微米的高效能集成电路的制程中，制作内连接线结构须利用所谓的镶嵌(damascene)技术。因为在半导体元件尺寸的原因，传统的金属铝的沉积以及蚀刻逐渐变得困难。同时，在效能的考虑上须要利用低阻值的金属例如，铜。
就像是集成电路的尺寸持续的朝着缩小尺寸进行，特有的高分子材料很明显的已经用于内介电层(ILD，inter-layer dielectric)，这是由于这些高分子材料本身具有低介电常数，特别是用在0.13毫微米制程或是更小尺寸的制程中。
在传统的技术上，将厚度为100埃的吸附促进层涂布在晶片上，此晶片可以是第二层金属层(M2，metal 2)，且在此晶片上有一层以氮化硅(SiN，siliconnitride)做为材料的蚀刻终止层(etching stop layer)，接着，将整个晶片在150℃的温度下，大约120秒的时间进行烘烤。接着，再将有机高分子低介电层，例如，SiLK，其厚度大约为3000埃涂布在晶片上，然后将晶片在一平板上且温度为23℃，时间大约为60秒的条件下，进行冷却而随后紧接着再进行300℃的烘烤步骤，其烘烤时间大约为100秒。虽然吸附促进层的烘烤步骤可以有利于与底层的蚀刻终止层之间的键结，但是经烘烤之后的吸附促进层干的表面不能促进低介电材料的涂布能力。
当涂布能力在其极限状态，若预润湿步骤没有采用时，则在晶片的四周会有涂布缺陷产生。
根据以上的描述，须要采用一种方法来改善吸附促进层的可润湿性使得在低介电层的涂布品质可以增加。
(3)发明内容
本发明的主要目的在于提供一种利用一种有机溶剂以改善经烘烤之后的吸附促进层的可润湿性的方法。
本发明的另一目的在于提供一种改善在经过预润湿步骤的吸附促进层对低介电层的涂布品质的方法。
本发明的又一目的在于提供一种改善低介电层的涂怖能力的方法。
根据本发明一方面提供一种增加吸附促进层可润湿性的方法，其特点是，该方法至少包括：提供一吸附促进层在一半导体底材上，其中该吸附促进层为一种界面活性剂材料；烘烤该吸附促进层以除去在该吸附促进层内的溶剂；以及利用有机溶剂润湿该吸附促进层使得该吸附促进层的表面的可润湿性增加。
根据本发明另一方面提供一种在吸附促进层在预润湿步骤中增加涂布能力的方法，其特点是，该方法至少包括：旋涂一吸附促进层在一底材上，其中，该吸附促进层的特性为一种界面活性剂材料；烘烤该吸附促进层以去除在该吸附促进层内的溶剂；以及利用有机溶剂预润湿该吸附促进层，以使该吸附促进层的表面的可润湿性增加。
根据本发明又一方面提供一种增加低介电层涂布能力的方法，其特点是，该方法至少包括：提供一底材以及一蚀刻终止层在该底材上；旋涂一吸附促进层在该蚀刻终止层上；烘烤该吸附促进层使得在该吸附促进层内的溶剂可以去除以及与该蚀刻终止层键结；利用有机溶剂预润湿该吸附促进层，以使该吸附促进层的表面的可润湿性增加；以及旋涂一有机高分子低介电层在该吸附促进层上。
为进一步说明本发明的目的、结构特点和效果，以下将结合附图对本发明进行详细的描述。
(4)附图说明
图1是根据本发明的方法在底材上形成蚀刻终止层的截面示意图；
图2是根据本发明的方法在图1的结构上形成吸附促进层的截面示意图；以及
图3是根据本发明的方法在经过预润湿以及烘烤步骤之后在图2的结构上形成一低介电层的截面示意图。
(5)具体实施方式
本发明的一些实施例会详细描述如下。然而，除了详细描述外，本发明还可以广泛地以其他的实施例施行，且本发明的范围不受其限定，而是以权利要求的专利范围为准。
在以下所描述的各个步骤是在涂布反应室(coating chamber)中进行，且在反应室内的相对湿度(relative humidity)大约为30％至60％，最佳的条件为35％至45％，同时在反应室内的温度范围为20℃至30℃，最佳的温度范围为23℃至27℃。参考图1，在底材10上形成一层蚀刻终止层12，这是用来作为之后在蚀刻步骤中蚀刻位置停止的层。蚀刻终止层12的材料可以是无机低介电材料例如，氮化硅(SiN，silicon nitride)或是碳化硅(SiC，siliconcarbide)，而形成的方式则是利用化学气相沉积方法(CVD，chemical vapordeposition method)，而底材可以是第二层金属层(M2，metal 2)。而碳化硅具有较低的介电常数同时若与一般常使用的氮化硅比较，在内连线结构，单或是双镶嵌结构中，对于金属铜而言，碳化硅有较佳的扩散阻力，且对于先进的制程而言，碳化硅与低介电材料是最常被使用的。0
参考图2，利用旋涂的方式将吸附促进层14涂布在蚀刻终止层12上。吸附促进层的化学结构具有硅单键(silicon-)以及未饱和的有机化学键，例如，乙烯三乙醯氧基硅氧烷(vinyltriacetoxysilane)，其商品名为AP 4000 TM由Dow Chemical所制造。而吸附促进层14旋涂在蚀刻终止层12上的厚度大约为100埃。而吸附促进层14为一种类似于界面活性剂(surfactant)的材料，且通常是用于吸附促进层14的制程以及强化以有机高分子做为材料的低介电层16(在图3表示)与蚀刻终止层12之间的接着能力。
接着，为了要将吸附促进层14的分子与底材10之间相互固定，则是将旋涂的吸附促进层14经过烘烤步骤而发生化学键结反应。然而，在烘烤的步骤中也会造成将吸附促进层14内的溶剂除去，但也不会全部移除。而烘烤的温度大约在100℃至200℃之间，最佳的烘烤温度为150℃至180℃。对于在后续步骤中，要将低介电层16旋涂在吸附促进层14上，则一个干燥的吸附促进层14的表面，并不能成为一个合适的条件。在本发明的最佳实施例中，是提供一个将经过烘烤步骤的吸附促进层14利用有机溶剂(organic solvent)进行润湿的步骤，这步骤不只是将吸附促进层14与底材10之间结合，此外也可以调整吸附促进层14表面的可润湿性。
接着，在一实施例中，晶片在经过烘烤之后，将晶片进行冷却，其冷却的温度大约为23℃，冷却时间大约为30秒。接着，利用喷嘴(nozzle)将做为预润湿的有机溶剂，在1.5秒的时间将1毫升的有机溶剂喷洒在静止的晶片上。而晶片在2000每分钟的转速(revolution per minute，rpm)以及0.5秒的时间，加速度至10000rpm2的条件下进行旋转干燥以除去残留在晶片上的有机溶剂，而此有机溶剂可以是1，3，5-三甲基苯(1，3，5-trimethyl benzene)或是单甲基醚丙二醇醋酸酯(PGMEA，propylene glycol monomethyl etheracetate)。
在另一个实施例中，经过烘烤之后，晶片也是同样在温度为23℃且时间为30秒的条件下进行冷却。接着，也是利用喷嘴将1毫升的有机溶剂喷洒分散在以转速大约为2000rpm在旋转的晶片上。而晶片在一秒钟的时间减速至0rpm，接着再以0.5秒的时间加速至2000rpm的条件下进行旋转干燥(spin-dry)以除去残留在晶片上的有机溶剂。
接着，参考图3，利用旋涂的方式将低介电层16涂布在吸附促进层14上。有机高分子材料如SiLK可以做为低介电层16，而SiLK是由Dow Chemical所提供。而SiLK的介电常数值的范围大约在2.6至2.7之间。且低介电层14旋涂在吸附促进层14上的厚度大约为3000埃。然后，在低介电层16旋涂在吸附促进层14之后，将晶片在温度300℃且时间为100秒的条件下进行烘烤。
根据以上的描述可以得知，为了增加低介电层的接着能力，利用吸附促进层旋涂在蚀刻终止层以及低介电层之间，且在低介电层旋涂之前，在吸附促进层上进行预润湿步骤以增加涂布品质。
当然，本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本发明，而并非用作为对本发明的限定，只要在本发明的实质精神范围内，对以上所述实施例的变化、变型都将落在本发明权利要求书的范围内。

Claims (17)

1.一种增加吸附促进层可润湿性的方法，其特征在于，该方法至少包括：
提供一吸附促进层在一半导体底材上，其中该吸附促进层为一种界面活性剂材料；
烘烤该吸附促进层以除去在该吸附促进层内的溶剂；以及
利用有机溶剂润湿该吸附促进层使得该吸附促进层的表面的可润湿性增加。
2.如权利要求1所述的方法，其特征在于，所述有机溶剂至少包括1，3，5-三甲基苯。
3.如权利要求2所述的方法，其特征在于，所述有机溶剂至少包括单甲基醚丙二醇醋酸酯。
4.如权利要求3所述的方法，其特征在于，还包括一喷嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于静止状态。
5.如权利要求4所述的方法，其特征在于，还包括一喷嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于旋转状态。
6.一种在吸附促进层在预润湿步骤中增加涂布能力的方法，其特征在于，该方法至少包括：
旋涂一吸附促进层在一底材上，其中，该吸附促进层的特性为一种界面活性剂材料；
烘烤该吸附促进层以去除在该吸附促进层内的溶剂；以及
利用有机溶剂预润湿该吸附促进层，以使该吸附促进层的表面的可润湿性增加。
7.如申请专利范围6所述的方法，其特征在于，所述有机溶剂至少包括1，3，5-三甲基苯。
8.如权利要求7所述的方法，其特征在于，所述有机溶剂至少包括单甲基醚丙二醇醋酸酯。
9.如权利要求8所述的方法，其特征在于，还包括一喷嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于静止状态。
10.如权利要求9所述的方法，其特征在于，还包括一喷嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于旋转状态。
11.如权利要求6所述的方法，其特征在于，还包括一低介电层旋涂在该吸附促进层上。
12.一种增加低介电层涂布能力的方法，其特征在于，该方法至少包括：
提供一底材以及一蚀刻终止层在该底材上；
旋涂一吸附促进层在该蚀刻终止层上；
烘烤该吸附促进层使得在该吸附促进层内的溶剂可以去除以及与该蚀刻终止层键结；
利用有机溶剂预润湿该吸附促进层，以使该吸附促进层的表面的可润湿性增加；以及
旋涂一有机高分子低介电层在该吸附促进层上。
13.如权利要求12所述的方法，其特征在于，所述有机溶剂至少包括1，3，5-三甲基苯。
14.如权利要求13所述的方法，其特征在于，所述有机溶剂至少包括单甲基醚丙二醇醋酸酯。
15.如权利要求14所述的方法，其特征在于，还包括一喷嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于静止状态。
16.如权利要求15所述的方法，其特征在于，还包括一嘴喷洒该有机溶剂到一晶片上，其中，该晶片是处于旋转状态。
17.如权利要求12所述的方法，其特征在于，还包括一在该预润湿该吸附促进层步骤之后的旋涂干燥步骤。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101772413A (zh) * 2007-08-01 2010-07-07 Aki公司Dba 化妆工具及其制造方法
CN106558483A (zh) * 2015-09-25 2017-04-05 三星Sdi株式会社 制造二氧化硅层的方法、二氧化硅层以及电子装置

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806182B2 (en) * 2002-05-01 2004-10-19 International Business Machines Corporation Method for eliminating via resistance shift in organic ILD
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7268058B2 (en) * 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) * 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US20070090408A1 (en) * 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US20080206467A1 (en) * 2007-02-23 2008-08-28 Vlad Mitlin Method of prevention of coating defects
ES2489615T3 (es) * 2007-12-11 2014-09-02 Apoteknos Para La Piel, S.L. Uso de un compuesto derivado del acido p-hidroxifenil propionico para el tratamiento de la psoriasis
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
KR101968224B1 (ko) * 2015-11-24 2019-04-11 삼성에스디아이 주식회사 실리카 막의 제조방법, 실리카 막 및 전자소자

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4692398A (en) * 1985-10-28 1987-09-08 American Hoechst Corporation Process of using photoresist treating composition containing a mixture of a hexa-alkyl disilazane, propylene glycol alkyl ether and propylene glycol alkyl ether acetate
US4806458A (en) * 1985-10-28 1989-02-21 Hoechst Celanese Corporation Composition containing a mixture of hexa-alkyl disilazane and propylene glycol alkyl ether and/or propylene glycol alkyl ether acetate
US5998103A (en) * 1998-04-06 1999-12-07 Chartered Semiconductor Manufacturing, Ltd. Adhesion promotion method employing glycol ether acetate as adhesion promoter material
US5962621A (en) * 1998-04-28 1999-10-05 The Dow Chemical Company Process for preparing hydroxy-functionalized polyesters
US6245690B1 (en) * 1998-11-04 2001-06-12 Applied Materials, Inc. Method of improving moisture resistance of low dielectric constant films

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101772413A (zh) * 2007-08-01 2010-07-07 Aki公司Dba 化妆工具及其制造方法
CN106558483A (zh) * 2015-09-25 2017-04-05 三星Sdi株式会社 制造二氧化硅层的方法、二氧化硅层以及电子装置

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