CN1399423A - Phase demodulator, sign and time sequence restoring circuit and method - Google Patents
Phase demodulator, sign and time sequence restoring circuit and method Download PDFInfo
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- CN1399423A CN1399423A CN 01120673 CN01120673A CN1399423A CN 1399423 A CN1399423 A CN 1399423A CN 01120673 CN01120673 CN 01120673 CN 01120673 A CN01120673 A CN 01120673A CN 1399423 A CN1399423 A CN 1399423A
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Abstract
The sign and time sequence restoring circuit includes a conversion value producing circuit, a selector circuit, several accumulators and one comparator module. It can find out the sign of the optimal sample point by utilizing directly the digital in-phase signal components and digital orthogonal signal components in two adjacent signs without needing phase difference operating process. in addition, the present invention also provides a phase demodulator with simple structure.
Description
Invention field
The present invention relates to a kind of phase demodulator, symbol sequential reflex circuit and method thereof, be meant a kind of phase demodulator, symbol sequential reflex circuit and method thereof that is used in the tdma system that uses PI/4-DQPSK fundamental frequency rectification technology especially.
Background technology
With regard to digital radio fundamental frequency rectification technology, PI/4-DQPSK fundamental frequency rectification technology is one of technology for common, and this PI/4-DQPSK fundamental frequency rectification technology is widely used at present in as systems such as the PDC of the USDC of North America and PACS system or Japan and PHS.In addition, with regard to PI/4-DQPSK fundamental frequency rectification technology, usually utilize a phase demodulator to carry out, existing phase demodulator as shown in Figure 1, it is one to include the phase demodulator 1 of a symbol sequential reflex circuit 15, as shown in the drawing, this phase demodulator 1 also comprises a radio circuit 11, an analog-digital converter 12, a matched filter 13, reaches phase difference generation circuit 14.
Wherein, this radio circuit 11 is in order to receive an analog high frequency and to convert thereof into an analog if signal; This analog if signal is again through the conversion of this analog-digital converter 12 and matched filter 13 and filtering and then produce a homophase (in-phase) signal I, an and quadrature (quadrature) signal Q, generally speaking this in-phase signal I, and orthogonal signalling Q be respectively a digital signal that has a sign; This phase difference produces circuit 14 and asks for a phase difference θ according to in-phase signal I and orthogonal signalling Q; 15 phase differences of being exported according to this phase difference generation circuit 14 of this symbol sequential reflex circuit carry out symbol sequential and reply.
From the above, existing symbol sequential reflex circuit 15 is for calculating the optimal sampling point of a symbol, usually to produce circuit 14 by above-mentioned phase difference earlier and ask for a phase difference θ, utilize for this symbol sequential reflex circuit 15, this symbol sequential reflex circuit 15 calculates optimal sampling point by phase difference θ again, carries out symbol sequential according to this and replys.This technology is found in United States Patent (USP) the 4th, 941, the content shown in No. 155.With regard to the content disclosed in this patent, its shortcoming is: it is when asking for optimal sampling point, must between polar coordinates and I-Q rectangular coordinate, carry out mathematical operation conversion repeatedly, and it also must so will cause the increase of time of implementation through the complex calculations process when asking for phase difference θ.
Have and state shortcoming in view of this, how in seeking the optimal sampling point process, to simplify calculation step, and then to shorten operation time be an important topic in fact.In addition, how to simplify computing, the required circuit of simplification computing of optimal sampling point, and then the formation of simplification phase demodulator also is an important topic.
Summary of the invention
The object of the present invention is to provide a kind of calculating process of seeking optimal sampling point of simplifying, and then shorten symbol sequential reflex circuit and the method thereof of operation time.
Another object of the present invention is to provide a kind of calculating process of seeking optimal sampling point of simplifying, and then simplify the phase demodulator of the required circuit of computing.
In order to achieve the above object, the present invention adopts following technical scheme: symbol sequential reflex circuit of the present invention, be in order to receive an in-phase signal and orthogonal signalling, and seek, export a optimal sampling point in the symbol period according to in-phase signal component and quadrature signal component, comprise: a conversion value produces circuit, utilizes the in-phase signal of same sampling point in the two adjacent symbols and orthogonal signalling to produce a pair of conversion value that should sampling point; One selects circuit, is electrically connected in this conversion value and produces circuit, produces the conversion value that circuit is exported in order to receive this conversion value, and according to the order of sampling point this conversion value is exported in regular turn; A plurality of accumulators, in order to receive the pairing conversion value of being exported from this selection circuit of each sampling point respectively, wherein, the number of this accumulator is same as the sampling point number, and each accumulator is in order to the conversion value of same sampling point in the two adjacent symbols that add up, to obtain the pairing aggregate-value of each sampling point; And a comparison module, be electrically connected in this accumulator, in order to receiving the aggregate-value that this accumulator is exported, and it is compared, to obtain a largest cumulative value, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
The invention provides another symbol sequential reflex circuit, in order to receive an in-phase signal and orthogonal signalling, and seek, export a optimal sampling point in the symbol period according to in-phase signal component and quadrature signal component, comprise: a conversion value produces circuit, utilizes the in-phase signal component of the same sampling point in the two adjacent symbols and quadrature signal component to produce a pair of conversion value that should sampling point; One computing circuit is electrically connected in this conversion value and produces circuit, produces the conversion value that circuit is exported in order to receive this conversion value, and itself and another conversion value addition is exported; A plurality of delay circuits, connected in series respectively, its preceding and the most last delay circuit is electrically connected in this computing circuit respectively, and above-mentioned another conversion value is exported by this last delay circuit, this delay circuit is then exported an aggregate-value that conversion value added up by the sampling point correspondence respectively behind a certain hour; And a comparison module, be electrically connected in this delay circuit, in order to receiving the aggregate-value that this delay circuit is exported, and it is compared, to obtain a largest cumulative value, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
The present invention also provides a kind of symbol sequential answering method, the in-phase signal component of adjacent two symbols of foundation and quadrature signal component are sought the optimal sampling point in the symbol period, may further comprise the steps: under same sampling point, the product of the in-phase signal component of adjacent two symbols is added the product of the quadrature signal component of this two symbol, to obtain one first conversion component, simultaneously, with the in-phase signal component of the last symbol of this adjacent-symbol and the in-phase signal component of a symbol before the quadrature signal component product of symbol deducts at present and the product of the quadrature signal component of symbol at present, to obtain one second conversion component; With this first the conversion component square value add this second the conversion component square value, to obtain a conversion value; At a plurality of symbols, the pairing conversion value of same sampling point is added up, to obtain an aggregate-value; And comparing the maximum in a plurality of aggregate-values, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
The present invention also provides a kind of phase demodulator, comprises: a radio circuit, in order to receive an analog high frequency and to convert thereof into an analog if signal; One analog-digital converter is electrically connected with this radio circuit, in order to receiving this analog if signal, and converts thereof into digital signal; One matched filter is electrically connected with this analog-digital converter, and produces an in-phase signal, reaches orthogonal signalling according to this digital signal; One symbol sequential reflex circuit is electrically connected with this matched filter, and asks for an optimal sampling point position according to this in-phase signal component and quadrature signal component.
In other words, the invention provides and a kind ofly need not carry out the calculating process of phase difference θ, and can directly utilize the digital inphase signal component of adjacent two symbols and symbol sequential reflex circuit and the method thereof that the digital quadrature signal component is asked for optimal sampling point.
Of the present inventionly the calculating process of phase difference θ need not be carried out, and the digital inphase signal component of adjacent two symbols and the phase demodulator that the digital quadrature signal component is asked for optimal sampling point can be directly utilized.
Advantage of the present invention is: because symbol sequential reflex circuit of the present invention can directly utilize in-phase signal component and quadrature signal component to ask for optimal sampling point, and the polar coordinates and the coordinate computation between the I-Q rectangular coordinate that need not carry out as prior art are repeatedly changed, and need not be through complicated phase difference θ calculating process, therefore, can shorten the operation time of seeking optimal sampling point.And phase demodulator of the present invention can reduce by a phase difference and produce circuit, and therefore, phase demodulator of the present invention can reach the calculating process of simplifying optimal sampling point, and then simplifies the required circuit of computing.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is the calcspar of the forming circuit of existing phase demodulator;
Fig. 2 is the process block diagram of symbol sequential answering method of the present invention;
Fig. 3 is the analogous diagram that a plurality of clumps of conversion of signals become X-Y plane, and wherein each clump signal comprises 60 symbols (being M=60), and comprises 25 sampling points (N=25) in each symbol;
Fig. 4 is the formation key diagram of preferred embodiment symbol sequential reflex circuit of the present invention;
Fig. 5 is the formation key diagram that conversion value of the present invention produces circuit;
Fig. 6 is another formation calcspar of symbol sequential reflex circuit of the present invention;
Fig. 7 is the formation calcspar of another symbol sequential reflex circuit of the present invention;
Fig. 8 is the formation calcspar of phase demodulator of the present invention.
Symbol description among the figure:
The step of 21～24 symbol sequential answering methods of the present invention
3 phase demodulators
31 radio circuits
32 analog-digital converters
33 matched filters
35 symbol sequential reflex circuits
351 conversion values produce circuit
3,511 first computing circuits
3,512 second computing circuits
352 select circuit
353 accumulators
354 comparison modules
355 phase-locked loops
356 computing circuits
357 delay circuits
Embodiment
The symbol sequential answering method:
Symbol sequential answering method of the present invention can be under need not the phase place and phase difference of signal calculated ripple (signalwaveform), and a symbol sequential (symboltiming) that utilizes PI/4-DQPSK modulation technique (modulationtechnology) to be produced can be replied (recover).More detailed it, symbol sequential answering method of the present invention can be under need not the phase place and phase difference of signal calculated ripple (signalwaveform), directly utilize the digital inphase signal component of adjacent two symbols (symbol) and digital quadrature signal component to seek a optimal sampling point (bestoroptimalsamplingpoint) in the symbol period, and then carry out symbol sequential according to this optimal sampling point and reply.
Before specifying symbol sequential answering method of the present invention, what illustrate earlier is that in the present embodiment, each clump (burst) signal packet contains M symbol (symbol); And include N sampling point (samplingpoints) in each symbol (symbol), wherein M, N are respectively a positive integer.In addition, I (kN+i), Q (kN+i) represent pairing digital inphase signal component of a certain sampling point and the digital quadrature signal component in a certain symbol respectively, are designated hereinafter simply as I (n), Q (n), wherein, i, k are respectively integer, and 0≤k≤M-l, 1＜i≤N.Again, I ((kN+i)-N), Q ((kN+i)-N) represent respectively to be designated hereinafter simply as I with respect to pairing digital inphase signal component of a certain sampling point and digital quadrature signal component in the symbol before a certain symbol
d(n), Q
d(n), wherein, i, k are divided into integer, and 0≤k≤M-1,1＜i≤N.In addition, for adjacent two symbols of same sampling point, pairing digital inphase signal component of a certain sampling point of its last symbol and digital quadrature signal component also can be expressed as I (n-N), Q (n-N) respectively, that is I
d(n)=I (n-N), Q
d(n)=Q (n-N).
As shown in Figure 2, symbol sequential answering method of the present invention is in step 21, the product of the in-phase signal component of adjacent two symbols of same sampling point is added the product of the quadrature signal component of this two symbol, to obtain one first conversion component (X (n)), simultaneously, the in-phase signal component of the last symbol of this adjacent-symbol and the quadrature signal component product of symbol are at present deducted the product of the quadrature signal component of the in-phase signal component of present symbol and last symbol, to obtain one second conversion component (Y (n)), if represent, then can be expressed as with mathematical expression:
X〔n〕＝I〔n〕I
d〔n〕+Q〔n〕Q
d〔n〕……(1a)
Y〔n〕＝I
d〔n〕Q〔n〕-I〔n〕Q
d〔n〕……(1b)
Again in step 22, square value of this first conversion component (X (n)) is added the square value of this second conversion component (Y (n)), to obtain a conversion value, conversion value is R if make
2When (n), R then
2(n)=X
2(n)+Y
2(n) ... (1c);
In step 23, at M symbol, the pairing conversion value of same sampling point is added up, obtaining an aggregate-value, if when making aggregate-value be Γ, then
In step 24, compare above-mentioned a plurality of aggregate-value Γ
iIn the maximum, this largest cumulative value corresponding to sampling point promptly be optimal sampling point.After the optimal sampling point determining positions, then can adjust sequential according to the position of this optimal sampling point, reply correctly to carry out symbol sequential.
Below further specify the position that to decide optimal sampling point why by the largest cumulative value.
From the above, because I (n), Q (n) represent in-phase signal component and quadrature signal component respectively, therefore, for the I-Q coordinate plane, the component of this I (n), Q (n) also can be expressed as:
I〔n〕＝r×cosθ
n……〔2a)，
Q (n)=r * sin θ
n(2b); R wherein
2=I
2+ Q
2
At this moment, I
d(n), Q
d(n) can be expressed as respectively:
I
d〔n〕＝I〔n-N〕＝r×cosθ
n-N……(2c)，
Q
d〔n〕＝Q〔n-N〕＝r×sinθ
n-N……(2d)；
If during with above-mentioned formula (2a), (2b), (2c), the above-mentioned formula of (2d) substitution (1a), (1b), then
X〔n〕＝r
2cosθ
n·cosθ
n-N+r
2sinθ
n·sinθ
n-N…(3a)，
Y〔n〕＝r
2sinθ
n·cosθ
n-N-r
2cosθ
n·sinθ
n-N…(3b)；
Again, by the trigonometric function theorem as can be known, above-mentioned formula (3a) reaches and (3b) can be expressed as:
cosθ
n·cosθ
n-N+sinθ
n·sinθ
n-N＝cos(θ
n-θ
n-N)..(4a)，
sinθ
n·cosθ
n-N-cosθ
n·sinθ
n-N＝sin(θ
n-θ
n-N)…(4b)；
That is, X (n)=r
2Cos (θ
n-θ
N-N) ... (5a),
Y〔n〕＝r
2sin(θ
n-θ
n-N)……(5b)；
By formula (5a), formula (5b) as can be known, the computing of X (n), Y (n) has in fact had the effect that is equal to phase difference calculating.
In addition, what deserves to be mentioned is, because R
2(n)=r
4{ X
2(n)+Y
2(n) }, therefore, as shown in Figure 3, for the R of arbitrary sampling point
2(n) value is not to be 1 entirely, and works as R
2(n)=1 o'clock, be expression central point O to the maximum average range of putting P, some Q, some R, some S, in other words, when aggregate-value was maximum, its pairing sampling point promptly was an optimal sampling point.
The symbol sequential reflex circuit:
Below, specify symbol sequential reflex circuit of the present invention with Fig. 4～Fig. 7.
As shown in Figure 4, symbol sequential reflex circuit of the present invention (symboltimingrecoverycircuit) 35 comprises a conversion value and produces circuit (transformvaluegenerationcircuit) 351, a selection circuit (selectioncircuit) 352, a plurality of accumulator (accumulator) 353, reaches a comparison module (comparisonmodule) 354, wherein
It is to utilize the in-phase signal component of the same sampling point in the two adjacent symbols and quadrature signal component to produce a pair of conversion value R that should sampling point that this conversion value produces circuit 351
2(n), as shown in Figure 5, this conversion value produces circuit 351 and comprises one first computing circuit 3511, reaches one second computing circuit 3512.
This first computing circuit 3511 be mainly by two delayers, four multipliers, and two adders constituted, it produces one first conversion component X (n) respectively, reaches the second conversion component Y (n) according to in-phase signal component I (n) and quadrature signal component Q (n), wherein this first conversion component X (n) equals under same sampling point, the product of the in-phase signal component of adjacent two symbols adds the product of the quadrature signal component of this two symbol, and its mathematic(al) representation is shown in above-mentioned formula (1a); Again, this second conversion component Y (n) equals under same sampling point, the in-phase signal component of the last symbol of adjacent two symbols and the present quadrature signal component product of symbol deduct the product of the quadrature signal component of the in-phase signal component of present symbol and last symbol, and its mathematic(al) representation is shown in above-mentioned formula (1b);
Second computing circuit 3512 mainly is made of two multipliers and an adder, and it produces a conversion value R according to the above-mentioned first conversion component X (n) and the second conversion component Y (n)
2(n), and this conversion value R
2(n) equals the square value that this first square value of changing component X (n) adds this second conversion component Y (n), and its mathematic(al) representation is shown in above-mentioned formula (1c).
In addition, this selection circuit 352 is electrically connected in this conversion value and produces circuit 351, produces the conversion value R that circuit 351 is exported in order to receive this conversion value
2(n), and according to the order of sampling point with this conversion value R
2(n) exports in regular turn, and in the present embodiment, this selection circuit 352 is a demultiplexer (demultiplexer);
This accumulator 353 is pairing conversion values of each sampling point of being exported from this selection circuit 352 in order to receive respectively, wherein, the number of this accumulator 353 is same as each symbol sampling point number, in the present embodiment, the number of the sampling point of each symbol is 25 points, that is N=25.Each accumulator is in order to the conversion value of the same sampling point in the two adjacent symbols that add up, to obtain the pairing aggregate-value Γ of each sampling point
iMoreover,
This comparison module 354 is electrically connected in this accumulator 353, in order to receiving the aggregate-value that this accumulator 353 is exported, and it is compared respectively, and to obtain wherein largest cumulative value, it promptly is the optimal sampling point position that this largest cumulative is worth pairing sampling point.As shown in Figure 6, the optimal sampling point position p that is exported by comparison module 354, judge again this optimal sampling point is located in which interval of a symbol, and control a phase-locked loop (PLL) 355 with this, carry out clock pulse (clock) adjustment, correctly reply (recover) at the symbol sequential of received signal according to this.For example, in the present embodiment, set optimal sampling point in advance and be positioned at of a symbol
On the sampling point, when p is
The time, that is the p position, optimal sampling point position that this comparison module 354 is exported is in the Qian Ban district of a symbol, the clock pulse (clock) of then transferring fast above-mentioned phase-locked loop 355 to be exported; Otherwise, if p is
The time, the clock pulse (clock) of then transferring slow above-mentioned phase-locked loop 355 to be exported.
Below be another embodiment of symbol sequential reflex circuit of the present invention.Be simplified illustration, assembly same as described above is continued to use above-mentioned figure number, and its explanation is omitted.
As shown in Figure 7, symbol sequential reflex circuit 35 of the present invention also can comprise conversion value generation circuit (transformvaluegenerationcircuit) 351, a computing circuit 356, a plurality of delay circuit (delaycircuit) 357, reach a comparison module (comparisonmodule) 354.
In the present embodiment, this computing circuit 356 can be an adder, and it is in order to the conversion value addition with same sampling point between adjacent-symbol.
This delay circuit (delaycircuit) the 357th, in order to postpone the output of conversion value, the number of this delay circuit 357 equals the number of sampling point in each symbol, and in the present embodiment, the number of sampling point is 25 points in each symbol.That is, when the pairing conversion value of sampling point during through a symbol time, conversion value by the 25th the 1st sampling point that delay circuit 357 is exported can be by the conversion value addition of this computing circuit 356 and the 26th sampling point, in like manner, the conversion value of the 2nd sampling point can be by the conversion value addition of this computing circuit 356 and the 27th sampling point, by that analogy, when total delay time equals the time of 60 symbols, each delay circuit 357 is the aggregate-value of the conversion value of exportable each sampling point, this aggregate-value then can be compared in above-mentioned comparison module (comparisonmodule) 354, to obtain wherein largest cumulative value, it promptly is the optimal sampling point position that this largest cumulative is worth pairing sampling point.
What deserves to be mentioned is at this, present embodiment also can be exported the optimal sampling point position at the comparison module 354 of Fig. 7, and as described which interval of judging the located symbol of this optimal sampling point earlier of Fig. 6 embodiment, control a phase-locked loop (PLL) 355 with this again, carry out clock pulse (clock) adjustment, correctly reply (recover) at the symbol sequential of received signal according to this.
From the above, because symbol sequential reflex circuit of the present invention can directly utilize in-phase signal component and quadrature signal component to ask for optimal sampling point, and the polar coordinates and the coordinate computation between the I-Q rectangular coordinate that need not carry out as prior art are repeatedly changed, and need not be through complicated phase difference θ calculating process, therefore, can shorten the operation time of seeking optimal sampling point.
Phase demodulator:
Above-mentioned explanation is at symbol sequential reflex circuit of the present invention and method thereof.Below be to explain at phase demodulator of the present invention.
As shown in Figure 8, phase demodulator 3 of the present invention comprises a radio circuit 31, an analog-digital converter 32, a matched filter 33, reaches a symbol sequential reflex circuit 35.Because the function of this radio circuit 31, analog-digital converter 32 and matched filter 33 is identical with the function of aforementioned radio circuit 11, analog-digital converter 12 and matched filter 13, therefore, its detailed description is then omitted.In addition, because the function of this symbol sequential reflex circuit 35 is identical with symbol sequential reflex circuit of the present invention, therefore, its detailed description is also omitted.
By as can be known shown in Figure 8, compared to existing phase demodulator 1, phase demodulator 3 of the present invention reduces by a phase difference and produces circuit 14, its main cause is that the symbol sequential reflex circuit 35 of phase demodulator 3 of the present invention does not need to be converted to polar coordinates by phase difference and asks for the optimal sampling point position, but in-phase signal component and the quadrature signal component of directly utilizing above-mentioned matched filter 33 to be exported are come calculating optimum sampling point position, so, phase demodulator 3 of the present invention can reduce by a phase difference and produce circuit, in view of the above, phase demodulator of the present invention can reach the calculating process of simplifying optimal sampling point, and then simplifies the purpose of the required circuit of computing.
The preferred embodiment that is proposed in detailed description is only in order to be easy to illustrate technology contents of the present invention, and be not with narrow sense of the present invention be limited to this embodiment, in the situation that does not exceed spirit of the present invention and claim of the present invention, can make many variations and implement.
Claims (21)
1, a kind of symbol sequential reflex circuit is in order to receiving an in-phase signal and orthogonal signalling, and seeks, exports a optimal sampling point in the symbol period according to in-phase signal component and quadrature signal component, comprising:
One conversion value produces circuit, utilizes the in-phase signal of same sampling point in the two adjacent symbols and orthogonal signalling to produce a pair of conversion value that should sampling point;
One selects circuit, is electrically connected in this conversion value and produces circuit, produces the conversion value that circuit is exported in order to receive this conversion value, and according to the order of sampling point this conversion value is exported in regular turn;
A plurality of accumulators, in order to receive the pairing conversion value of being exported from this selection circuit of each sampling point respectively, wherein, the number of this accumulator is same as the sampling point number, and each accumulator is in order to the conversion value of same sampling point in the two adjacent symbols that add up, to obtain the pairing aggregate-value of each sampling point; And
One comparison module is electrically connected in this accumulator, in order to receiving the aggregate-value that this accumulator is exported, and it is compared, and to obtain a largest cumulative value, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
2, symbol sequential reflex circuit according to claim 1, it is characterized in that: this symbol sequential reflex circuit also comprises a phase-locked loop, the sequential adjustment is carried out in the optimal sampling point position that export by above-mentioned comparison module this phase-locked loop, correctly carries out time sequence reply according to this.
3, symbol sequential reflex circuit according to claim 1, it is characterized in that: this conversion value produces circuit and comprises one first computing circuit, reaches one second computing circuit, wherein, this first computing circuit produces one first conversion component respectively, reaches one second conversion component according to in-phase signal component and quadrature signal component; This second computing circuit is to produce this conversion value according to this first conversion component and the second conversion component.
4, symbol sequential reflex circuit according to claim 3 is characterized in that: this first conversion component equals under same sampling point, and the product of the in-phase signal component of adjacent two symbols adds the product of the quadrature signal component of this two symbol; This second conversion component equals under same sampling point, and the in-phase signal component of the last symbol of adjacent two symbols and the present quadrature signal component product of symbol deduct the product of the quadrature signal component of department's phase signals component of present symbol and last symbol; And this conversion value equals the square value that the square value of this first conversion component adds this second conversion component.
5, symbol sequential reflex circuit according to claim 1 is characterized in that: this selection circuit is a demultiplexer.
6, symbol sequential reflex circuit according to claim 1 is characterized in that: have 25 sampling points in each symbol period, that is sampling rate is 25 times of character rate.
7, a optimal sampling point in the symbol period is sought, exported to a kind of symbol sequential reflex circuit in order to receiving an in-phase signal and orthogonal signalling, and according to in-phase signal component and quadrature signal component, comprising:
One conversion value produces circuit, utilizes the in-phase signal component of the same sampling point in the two adjacent symbols and quadrature signal component to produce a pair of conversion value that should sampling point;
One computing circuit is electrically connected in this conversion value and produces circuit, produces the conversion value that circuit is exported in order to receive this conversion value, and itself and another conversion value addition is exported;
A plurality of delay circuits, connected in series respectively, its preceding and the most last delay circuit is electrically connected in this computing circuit respectively, and above-mentioned another conversion value is exported by this last delay circuit, this delay circuit is then exported an aggregate-value that conversion value added up by the sampling point correspondence respectively behind a certain hour; And
One comparison module is electrically connected in this delay circuit, in order to receiving the aggregate-value that this delay circuit is exported, and it is compared, and to obtain a largest cumulative value, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
8, symbol sequential reflex circuit according to claim 7, it is characterized in that: this symbol sequential reflex circuit also comprises a phase-locked loop, the sequential adjustment is carried out in the optimal sampling point position that export by above-mentioned comparison module this phase-locked loop, correctly carries out time sequence reply according to this.
9, symbol sequential reflex circuit according to claim 7, it is characterized in that: this conversion value produces circuit and comprises one first computing circuit, reaches one second computing circuit, wherein, this first computing circuit produces one first conversion component respectively, reaches one second conversion component according to in-phase signal component and quadrature signal component; This second computing circuit produces this conversion value according to this first conversion component and the second conversion component.
10, symbol sequential reflex circuit according to claim 9 is characterized in that: this first conversion component equals under same sampling point, and the product of the in-phase signal component of adjacent two symbols adds the product of quadrature 1 signal component of this two symbol; This second conversion component equals under same sampling point, and the in-phase signal component of a symbol deducts the in-phase signal component of present symbol and the product of last symbol quadrature signal component with the quadrature signal component product of present symbol before adjacent two symbols; And this conversion value equals the square value that the square value of this first conversion component adds this second conversion component.
11, symbol sequential reflex circuit according to claim 7 is characterized in that: this computing circuit is an adder.
12, symbol sequential reflex circuit according to claim 7 is characterized in that: have 25 sampling points in each symbol period, that is sampling rate is 25 times of character rate.
13, a kind of symbol sequential answering method, the in-phase signal component of adjacent two symbols of foundation and quadrature signal component are sought the optimal sampling point in the symbol period, may further comprise the steps:
Under same sampling point, the product of the in-phase signal component of adjacent two symbols is added the product of the quadrature signal component of this two symbol, to obtain one first conversion component, simultaneously, with the in-phase signal component of the last symbol of this adjacent-symbol and the in-phase signal component of a symbol before the quadrature signal component product of symbol deducts at present and the product of the quadrature signal component of symbol at present, to obtain one second conversion component;
With this first the conversion component square value add this second the conversion component square value, to obtain a conversion value;
At a plurality of symbols, the pairing conversion value of same sampling point is added up, to obtain an aggregate-value; And
Compare the maximum in a plurality of aggregate-values, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
14, symbol sequential answering method according to claim 13 is characterized in that: have 25 sampling points in each symbol period, that is sampling rate is 25 times of character rate.
15, a kind of phase demodulator comprises:
One radio circuit is in order to receive an analog high frequency and to convert thereof into an analog if signal;
One analog-digital converter is electrically connected with this radio circuit, in order to receiving this analog if signal, and converts thereof into digital signal;
One matched filter is electrically connected with this analog-digital converter, and produces an in-phase signal, reaches orthogonal signalling according to this digital signal;
One symbol sequential reflex circuit is electrically connected with this matched filter, and asks for an optimal sampling point position according to this in-phase signal component and quadrature signal component.
16, phase demodulator according to claim 15 is characterized in that: this symbol sequential reflex circuit comprises:
One conversion value produces circuit, utilizes the in-phase signal of same sampling point in the two adjacent symbols and orthogonal signalling to produce a pair of conversion value that should sampling point;
One selects circuit, is electrically connected in this conversion value and produces circuit, produces the conversion value that circuit is exported in order to receive this conversion value, and according to the sampling point order this conversion value is exported in regular turn;
A plurality of accumulators, in order to receive the pairing conversion value of being exported from this selection circuit of each sampling point respectively, wherein, the number of this accumulator is same as the sampling point number, and each accumulator is in order to the conversion value of same sampling point in the two adjacent symbols that add up, to obtain the pairing aggregate-value of each sampling point; And
One comparison module is electrically connected in this accumulator, in order to receiving the aggregate-value that this accumulator is exported, and it is compared, and to obtain a largest cumulative value, it promptly is optimal sampling point that this largest cumulative is worth pairing sampling point.
17, phase demodulator according to claim 16, it is characterized in that: this symbol sequential reflex circuit also comprises a phase-locked loop, the sequential adjustment is carried out in the optimal sampling point position that export by above-mentioned comparison module this phase-locked loop, correctly carries out time sequence reply according to this.
18, phase demodulator according to claim 16, it is characterized in that: this conversion value produces circuit and comprises one first computing circuit, reaches one second computing circuit, wherein, this first computing circuit produces one first conversion component respectively, reaches one second conversion component according to in-phase signal component and quadrature signal component; This second computing circuit produces this conversion value according to this first conversion component and the second conversion component.
19, phase demodulator according to claim 18 is characterized in that: this first conversion component equals under same sampling point, and the product of the in-phase signal component of adjacent two symbols adds the product of the quadrature signal component of this two symbol; This second conversion component equals under same sampling point, and the in-phase signal component of a symbol and the quadrature signal component product of symbol at present deduct the product of the quadrature signal component of the in-phase signal component of present symbol and last symbol before adjacent two symbols; And this conversion value equals the square value that the square value of this first conversion component adds this second conversion component.
20, phase demodulator according to claim 16 is characterized in that: this selection circuit is a demultiplexer.
21, phase demodulator according to claim 16 is characterized in that: have 25 sampling points in each symbol period, that is sampling rate is 25 times of character rate.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120673 CN1215665C (en) | 2001-07-24 | 2001-07-24 | Phase demodulator, sign and time sequence restoring circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01120673 CN1215665C (en) | 2001-07-24 | 2001-07-24 | Phase demodulator, sign and time sequence restoring circuit and method |
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| CN1399423A true CN1399423A (en) | 2003-02-26 |
| CN1215665C CN1215665C (en) | 2005-08-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020249106A1 (en) * | 2019-06-14 | 2020-12-17 | 第四范式（北京）技术有限公司 | Programmable device for processing data set, and method for processing data set |
| CN113639650A (en) * | 2021-08-10 | 2021-11-12 | 安徽大学 | Optical frequency domain reflectometer type sensing demodulation method based on phase accumulation measurement method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020249106A1 (en) * | 2019-06-14 | 2020-12-17 | 第四范式（北京）技术有限公司 | Programmable device for processing data set, and method for processing data set |
| US11791822B2 (en) | 2019-06-14 | 2023-10-17 | The Fourth Paradigm (Beijing) Tech Co Ltd | Programmable device for processing data set and method for processing data set |
| CN113639650A (en) * | 2021-08-10 | 2021-11-12 | 安徽大学 | Optical frequency domain reflectometer type sensing demodulation method based on phase accumulation measurement method |
| CN113639650B (en) * | 2021-08-10 | 2023-12-12 | 安徽大学 | Optical frequency domain reflectometer type sensing demodulation method based on phase accumulation measurement method |
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| CN1215665C (en) | 2005-08-17 |
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