CN1167234C - Sign timing restoring circuit of phase demodulator and its method - Google Patents
Sign timing restoring circuit of phase demodulator and its method Download PDFInfo
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- CN1167234C CN1167234C CNB001325558A CN00132555A CN1167234C CN 1167234 C CN1167234 C CN 1167234C CN B001325558 A CNB001325558 A CN B001325558A CN 00132555 A CN00132555 A CN 00132555A CN 1167234 C CN1167234 C CN 1167234C
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Abstract
The present invention relates to a symbol time sequence restoring circuit and a method for a phase demodulator. The circuit comprises a difference value generating circuit, a selecting circuit, an accumulator die set and a comparing die set. The method comprises the following steps: after the phase difference of an in-phase signal and an orthogonal signal is obtained by the same sampling point between contiguous symbols in a polar coordinate plane, the preset phase value is subtracted from the phase difference, and the square value is used as an operator; the total value of the phase difference of each sampling point in each symbol is calculated one by one, and the position of the best sampling point in the symbol cycle is found out so as to correctly restore the symbol time sequence of the signal sequence. The present invention has the advantages of simple circuit structure, operating step simplification and executing time reduction.
Description
Technical field
The symbol sequential restore circuit and the method thereof of the present invention relevant a kind of circuit, particularly a kind of phase demodulator, it is a kind of symbol sequential restore circuit and the method thereof that only can try to achieve the optimal sampling point position in the computing of polar coordinates plane.
Background technology
In digital radio fundamental frequency modulation technique, π/4-difference quadrature phase shift keying (DQPSK) fundamental frequency rectification technology is widely used, all adopt π/4-difference quadrature phase shift keying fundamental frequency modulation and rectification technology as system wireless electricity modem designing technique as systems such as the PDC of the USDC of North America and PACS system, Japan and PHS, its major advantage is its frequency band service efficiency height, power usefulness is high and receiver making etc. easily.
Existing π/4-difference quadrature phase shift keying fundamental frequency modulation and demodulation techniques are the modulation that transmit signal at transmitting terminal, and signal with the phase difference value of (π/4,3 π/4,5 π/4 and 7 π/4) four kinds of phase values as the continuous adjacent signal, and is represented the bit information that transmitted with this.
Separate timing when receiving terminal carries out signal, earlier the intermediate-freuqncy signal that is received is converted to digital signal via an analog/digital converter, be resent to a digital front-end (digital front end) and try to achieve digital baseband in-phase signal I
nWith digital baseband orthogonal signalling Q
n, afterwards, be converted to the rectangular coordinates plane and carry out computing and try to achieve best sample position, and recover the transmission signal of transmitting terminal.Above technology has been disclosed in United States Patent (USP) number 4,941,155, title is in the patent specification of " METHOD ANDCIRCUITRY FOR SYMBOL TIMING AND FREQUENCY OFF SETESTIMATION IN TIME DIVISION MULTIPLE ACCESS RIDIOSYSTEMS ".The digital baseband in-phase signal I of the prior art
nWith digital baseband orthogonal signalling Q
nAs input signal, and carry out symbol sequential with the following step and recover:
(1) tries to achieve this phase of input signals difference Δ θ;
(2) this phase difference be multiply by 4;
(3) be converted to rectangular coordinate by polar coordinates;
(X，Y)＝(cos4Δθ，sin4Δθ)
(4) use 16 accumulators, in the hope of 16 vectorial summations, wherein
(5) best sample position is f
i(X Y) peaked position occurs.
Yet aforementioned manner is too complicated, particularly carries out repeatedly mathematical operation conversion between polar coordinates and rectangular coordinates, and not only operation method is too loaded down with trivial details, and can increase the time of implementation.
Summary of the invention
First purpose of the present invention is to provide a kind of symbol sequential restore circuit and method thereof of phase demodulating, utilize to seek the optimal sampling point in the symbol, with the symbol sequential of restoring signal sequence correctly.
Second purpose of the present invention is to provide a kind of symbol sequential restore circuit and method thereof of simplifying demodulator, with the simplification calculation step, and shortens the time of implementation.
In order to achieve the above object, the present invention takes following technical measures:
A kind of symbol sequential restore circuit of the present invention and method thereof, be to utilize after same sampling point is obtained the phase difference of in-phase signal and orthogonal signalling between adjacent-symbol on the polar coordinates plane, subtract each other the squared operator of being used as with a preset phase value, calculate the phase difference total value of each sampling point in the symbol more one by one, and find out optimal sampling point position in the symbol period, with the symbol sequential of restoring signal sequence correctly.
One embodiment of symbol sequential row restore circuit of the present invention, system is used for phase demodulator, after obtaining the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol, to seek the best sample position in symbol period, it comprises that a difference produces circuit, and selects relatively module of circuit, an accumulator module and.This difference produce circuit system earlier by remove described digital inphase signal and described digital quadrature signal front and with the first quartile of above-mentioned phase difference mapping to phase plane, the phase difference numerical value that will map to first quartile again deducts a preset phase value and obtains a difference, and this difference is squared.This is selected circuit system to connect this difference and produces circuit, in order to the corresponding in regular turn output of phase difference square value with first sampling point institute computing in the symbol.This accumulator module system includes the accumulator that is same as the sampling point number in the symbol, and these accumulators receive the output from this selection circuit respectively, each accumulator and with the phase difference of the same sampling point of continuous adjacent intersymbol that adds up.This comparison module system is compared according to above-mentioned accumulator computes gained phase difference total value, and when one of them accumulator computes gained phase difference total value was minimum value, the sampling point of this accumulator correspondence promptly was an optimal sampling point.
Another embodiment of symbol sequential restore circuit of the present invention, system is used for phase demodulator, after obtaining the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol, to seek the optimal sampling point in symbol period, it comprises that a difference produces circuit, a computing circuit, prolongs optimal sampling point, and it comprises that a difference produces relatively module of circuit, a computing circuit, a delay circuit module and.This difference produce circuit system earlier by remove described digital inphase signal and described digital quadrature signal front and with the first quartile of above-mentioned phase difference mapping to phase plane, to map to the phase difference numerical value of first quartile and a preset phase again and subtract each other and obtain a difference, and this difference is squared.This computing circuit system carries out sum operation with the phase difference square value of same sampling point between adjacent-symbol.This delay circuit module system include with a symbol in be same as the delay circuit of sampling point number, each delay circuit is connected in series, and the output of last delay circuit also produces circuit with this difference and carries out computing by this computing circuit and be resent to first delay circuit.This comparison module system is compared according to the phase difference total value of above-mentioned delay circuit module with each sampling phase difference loop computation gained of a symbol, when one of them delay circuit calculating gained phase difference total value was little value, the sampling point of this delay circuit correspondence promptly was an optimal sampling point.
One embodiment of symbol sequential restoration methods of the present invention, system is used for phase demodulator, after obtaining the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol, to seek the optimal sampling point in symbol period, it comprises that step (a) is to (d).Step (a), by remove described digital inphase signal and described digital quadrature signal front the position and with the first quartile of above-mentioned phase difference mapping to phase plane.Step (b) is subtracted each other mapping to the phase difference numerical value and a preset phase value of first quartile, and this difference is squared.Step (c), the phase difference value of each sampling point in computing one symbol, and the phase difference value of the same sampling point of continuous adjacent intersymbol that adds up one by one.Step (d), when the phase difference total value of one of them sampling point was minimum value in comparing, this corresponding sampling point promptly was an optimal sampling point.
Compared with prior art, the present invention has following effect:
The present invention not only circuit structure is simple, and has the advantage of simplifying calculation step and shortening the time of implementation; Device of the present invention also available software is made, and uses software development, has aforementioned advantages equally.
Reaching embodiment in conjunction with the accompanying drawings is described in detail as follows architectural feature of the present invention:
Description of drawings:
Fig. 1: the circuit block diagram that comprises the phase demodulator of symbol sequential restore circuit of the present invention;
Fig. 2: the circuit block diagram of symbol sequential restore circuit embodiment of the present invention;
Fig. 3: the circuit block diagram of another embodiment of symbol sequential restore circuit of the present invention;
Fig. 4: the flow chart of symbol sequential restoration methods of the present invention.
Embodiment
As shown in Figures 1 and 2, Fig. 1 is the circuit block diagram that comprises the phase demodulator of symbol sequential restore circuit of the present invention; Phase demodulator comprises that a radio circuit 10, analog/digital converter 20, matched filter 30, a phase difference produce circuit 40 and a symbol sequential restore circuit 50, wherein, radio circuit 10 produces an analog if signal, through an analog/digital converter 20, convert digital signal to, and be transferred to matched filter 30, produce a homophase (in-phase) signal I
nAnd quadrature (quadrature) signal Q
n, this in-phase signal and orthogonal signalling determine a phase theta, θ=tan
-1(Q
n/ I
n).In the present embodiment, analog/digital converter 20 is with 25 times of sampling rates to character rate (symbol rate) (sample rate) this in-phase signal and orthogonal signalling to be taken a sample, and therefore, 25 sampling points is arranged in the symbol.Phase difference produces in-phase signal and the orthogonal signalling of circuit 40 according to each sampling point correspondence, and determines a phase theta earlier, and the phase difference value that same sampling point determined of phase place 0 and previous symbol is called the first phase difference θ
n 1, Δ θ
n 1Value is to represent with binary digital form, Δ θ
n 1=θ
n 1-θ
1 N-25, wherein, n represents the sequence number of all sampling points, and θ
n 1With θ
1 N-25Represent the phase place of the same sampling point between adjacent-symbol.
As shown in Figure 2, it is the circuit block diagram of symbol sequential restore circuit embodiment of the present invention; The symbol sequential restore circuit 50 of present embodiment comprises that difference produces relatively module 54 of circuit 51, multiplexed splitter 52 (as selecting circuit), accumulator module 53 and, and difference produces circuit 51 earlier with the first phase difference θ
n 1Corresponding to the first quartile of phase plane, in the present embodiment, is to take away the first phase difference θ
n 1Senior Two bit, this moment, the phase place of gained was called the second phase difference θ
n 2, again with the second phase difference θ
n 2Squared with the difference of π/4, i.e. (Δ θ
n 2-π/4)
2What deserves to be mentioned is the first phase difference θ at this
n 1Phase deviation and assorted letter not being arranged ideally, should be the wherein a kind of of π/4,3 π/4,5 π/4 or 7 π/4, at the first phase difference θ
n 1Mapping is to first quartile, the second phase difference θ
n 2Promptly only become π/4, so with the second phase difference θ
n 2Subtract each other with π/4 and to be used as the basis of seeking optimal sampling point.
Multiplexed splitter 52 is that difference is produced (the Δ θ that 51 in circuit calculates 25 sampling points one by one
n 2-π/4)
2Difference is exported this 25 phase difference values in regular turn, also be about to 25 differences and be sent to respectively in included first accumulator to the, 25 accumulators of accumulator module 53 and add up by (25 respectively corresponding its accumulators of sampling points), with the phase difference total value of same sampling point in the continuous adjacent symbol that adds up.
Relatively module 54 is compared according to above-mentioned 25 accumulator computes gained phase difference total values, and when one of them accumulator computes gained phase difference total value was minimum value, the pairing sampling point of this accumulator promptly was an optimal sampling point.
Please refer to shown in Figure 2ly, each sampling point in symbol produces circuit 51 through difference and calculates (Δ θ
n 2-π/4)
2Value, again via multiplexed splitter 52 in regular turn should correspondence phase difference value be sent to (corresponding first accumulator 531 of first sampling point that adds up in the accumulator of accumulator module 53 correspondences, second corresponding second accumulator 532 of sampling point, by that analogy), therefore each symbol has 25 sampling points to come in, each accumulator phase difference value (Δ θ that promptly adds up
n 2-π/4)
2Once, in the present embodiment, be to utilize the phase difference value of same sampling point that adds up between 60 adjacent-symbols to seek optimal sampling point, phase difference value (Δ (θ so each accumulator of accumulator module 53 all adds up
n 2-π/4)
2Totally 60 times; As if the computational process of representing accumulator with mathematical expression, promptly first accumulator 531 calculates
Second accumulator 532 calculates
The 25 accumulator 533 calculates
K=60 wherein.
Please refer to shown in Figure 3, it is the circuit block diagram of another embodiment of the symbol sequential restore circuit among the present invention, among this embodiment, symbol sequential restore circuit 60 comprises that a difference produces circuit 61, a computing circuit 62 (as adder), a delay circuit module 63 and a comparison module 64, wherein, difference produces circuit 61 and relatively module 64 is identical with Fig. 2, and the first included delay circuit 631 of delay circuit module 63, second delay circuit the 632 to the 25 delay circuit 633 corresponds respectively to 25 sampling point phase differences of a symbol, therefore, when a sampling point phase difference through time of delay of 25 delay circuits (from first delay circuit 631, second delay circuit the 632 to the 25 delay circuit 633), promptly representative postpones the time of a symbol; That is, when 25 sampling point phase differences during simultaneously through a delay circuit, the first sampling point phase difference by 633 outputs of the 25 delay circuit can utilize adder 62 and the 26 sampling point phase difference addition, when again through a delay circuit, the second sampling point phase difference via 633 outputs of the 25 delay circuit can utilize adder 62 and the 27 sampling point phase difference addition, by that analogy, during through 25 delay circuits (time that postpones a symbol), the 25 sampling point phase difference of exporting via the 25 delay circuit 633 also can utilize adder 62 and the 50 sampling point phase difference addition; In the present embodiment, be made as the time that postpones 60 symbols, this moment, each delay circuit was with after each sampling point phase difference circulation addition, relatively the module 64 phase difference total value of relatively finding out one of them delay circuit output from 25 delay circuits is for hour, and the pairing sampling point of this delay circuit promptly is an optimal sampling point; Though this kind method is longer operation time, the integrated circuit structure is simpler.
Please refer to shown in Figure 4ly, it is the flow chart of symbol sequential restoration methods of the present invention, utilize obtain the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between the adjacent-symbol of front and back after, to seek the optimal sampling point in symbol period.This flow process comprises the steps: step 71, and the phase difference that same sampling point between the adjacent-symbol of front and back is obtained (is called first phase difference (Δ θ
n 1) mapping is to the first quartile of phase plane, in the present embodiment, takes away the first phase difference θ
n 1The highest two bits with the first quartile of mapping to phase plane, this moment gained phase place be called the second phase difference θ
n 2Step 72 (is the second phase difference θ with mapping to the phase difference of first quartile
n 2) subtract each other with preset phase value π/4, and this difference is squared, can be expressed as (Δ θ
n 2-π/4)
2Step 73 is calculated the phase difference value of first sampling point to the, 25 sampling points in the symbol one by one, and the phase difference value of the same sampling point of continuous adjacent intersymbol that adds up, and can be expressed as
Wherein 1≤i≤25, and k are 60 in the present embodiment, that is the phase difference value of the same sampling point between 60 adjacent-symbols of adding up.In step 74, when the phase difference total value that compares one of them sampling point was minimum value, this corresponding sampling point promptly was an optimal sampling point.
Foregoing of the present invention is to utilize embodiment that technical characterictic of the present invention is described, is not to be used to limit protection scope of the present invention, even there is the people to change slightly on the basis of the present invention's design, must belong in protection scope of the present invention.
Claims (10)
1, a kind of symbol sequential restore circuit of phase demodulator after utilization obtains the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol, to seek the optimal sampling point in symbol period, comprising:
A difference produces circuit, it is used for by the position that removes described digital inphase signal and described digital quadrature signal front the first quartile of phase difference mapping to phase plane, the phase difference numerical value that maps to first quartile is deducted a preset phase value and obtains a difference, and this difference is squared;
Select circuit for one, connect difference and produce circuit, in order to the corresponding in regular turn output of phase difference square value each sampling point institute computing in the symbol;
An accumulator module, include with a symbol in be same as the accumulator of sampling point number, each accumulator receives respectively from the output of selecting circuit, each accumulator is in order to the phase difference of the same sampling point of continuous adjacent intersymbol that adds up;
A comparison module is compared according to accumulator computes gained phase difference total value, and when one of them accumulator computes gained phase difference total value was minimum value, the sampling point of this accumulator correspondence promptly was an optimal sampling point.
2, circuit according to claim 1 is characterized in that, the preset phase value that described difference produces circuit is π/4.
3, circuit according to claim 1 is characterized in that, described selection circuit is a multiplexed splitter.
4, circuit according to claim 1 is characterized in that, has 25 sampling points in the described symbol, and promptly sampling rate is 25 times of character rate.
5, a kind of symbol sequential restore circuit of phase demodulator after utilization obtains the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol, to seek the optimal sampling point in symbol period, comprising:
A difference produces circuit, be used for by the position that removes described digital inphase signal and described digital quadrature signal front the first quartile of phase difference mapping to phase plane, to map to the phase difference numerical value of first quartile and a preset phase again and subtract each other and obtain a difference, and this difference is squared;
A computing circuit carries out sum operation with the phase difference square value of same sampling point between adjacent-symbol;
A delay circuit module, include with a symbol in be same as the delay circuit of sampling point number, each delay circuit polyphone connects, and the output of last delay circuit also produces circuit with difference and utilizes computing circuit to carry out computing to be resent to first delay circuit;
A comparison module, compared according to the phase difference total value of delay circuit module each sampling phase difference loop computation gained of a symbol, when one of them delay circuit calculating gained phase difference total value was minimum value, the sampling point of this delay circuit correspondence promptly was an optimal sampling point.
6, circuit according to claim 5 is characterized in that, the preset phase value that described difference produces circuit is π/4.
7, circuit according to claim 5 is characterized in that, has 25 sampling points in the described symbol, and promptly sampling rate is 25 times of character rate.
8, a kind of symbol sequential restoration methods of phase demodulator, obtain the phase difference of digital inphase signal and digital quadrature signal from the same sampling point between adjacent-symbol after, to seek the optimal sampling point in symbol period, comprise the steps:
By remove described digital inphase signal and described digital quadrature signal front the position and with the first quartile of above-mentioned phase difference mapping to phase plane;
Mapping to the phase difference numerical value and a preset phase value of first quartile subtracted each other, and difference is squared;
The phase difference value of each sampling point in computing one symbol, and the phase difference value of the same sampling point of continuous adjacent intersymbol that adds up one by one;
When the phase difference total value that compares one of them sampling point was minimum value, this corresponding sampling point promptly was an optimal sampling point.
9, method according to claim 8 is characterized in that, described preset phase value is π/4.
10, method according to claim 8 is characterized in that, has 25 sampling points in the described symbol, and promptly sampling rate is 25 times of character rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001325558A CN1167234C (en) | 2000-11-27 | 2000-11-27 | Sign timing restoring circuit of phase demodulator and its method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001325558A CN1167234C (en) | 2000-11-27 | 2000-11-27 | Sign timing restoring circuit of phase demodulator and its method |
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| Publication Number | Publication Date |
|---|---|
| CN1355602A CN1355602A (en) | 2002-06-26 |
| CN1167234C true CN1167234C (en) | 2004-09-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001325558A Expired - Fee Related CN1167234C (en) | 2000-11-27 | 2000-11-27 | Sign timing restoring circuit of phase demodulator and its method |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3755602B2 (en) * | 2003-03-04 | 2006-03-15 | ソニー株式会社 | Signal processing apparatus, program for credit processing apparatus, recording medium recording signal processing apparatus program, and signal processing method |
| CN1968235B (en) * | 2005-11-15 | 2010-05-05 | 凌阳科技股份有限公司 | Preorder detection and symbol time sequence recovery system and method |
| CN101488824B (en) * | 2008-01-15 | 2013-03-27 | 瑞昱半导体股份有限公司 | Time sequence recovery circuit and method |
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2000
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