CN211124352U

CN211124352U - Circuit for transmitting data through clock signal

Info

Publication number: CN211124352U
Application number: CN202020321838.1U
Authority: CN
Inventors: 皮德义; 刘昌�; 刘金亮
Original assignee: Newcosemi Beijing Technology Co ltd
Current assignee: Newcosemi Beijing Technology Co ltd
Priority date: 2020-03-16
Filing date: 2020-03-16
Publication date: 2020-07-28
Anticipated expiration: 2030-03-16

Abstract

The utility model discloses a circuit through clock signal transmission data. The circuit includes: a signal modulator and a signal demodulator; the input end of the signal modulator is connected with the data signal end and the clock signal end; the signal modulator is used for acquiring a data signal and a clock signal, modulating the data signal to obtain a modulated data signal, and loading the modulated data signal to the clock signal to obtain a mixed signal; the input end of the signal demodulator is connected with the output end of the signal modulator; the signal demodulator is used for acquiring the mixed signal and demodulating a data signal from the mixed signal. The utility model discloses can reduce and walk the line, simplify the structure of circuit, reduce the design degree of difficulty.

Description

Circuit for transmitting data through clock signal

Technical Field

The utility model relates to a circuit design field especially relates to a circuit through clock signal transmission data.

Background

With the development of chip technology, more and more devices and denser routing density of chips are achieved, so that the design difficulty is increased. Therefore, the chip design has the problems of high wiring density, complex circuit and high design difficulty.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a circuit for transmitting data through a clock signal, in which a data signal is superimposed on the clock signal, and the data signal and the clock signal are mixed and transmitted through a single transmission line, so as to reduce the number of wires, simplify the structure of the circuit, and reduce the design difficulty.

In order to achieve the above object, the utility model provides a following scheme:

A circuit for transmitting data via a clock signal, comprising: a signal modulator and a signal demodulator;

The input end of the signal modulator is connected with the data signal end and the clock signal end; the signal modulator is used for acquiring a data signal and a clock signal, modulating the data signal to obtain a modulated data signal, and loading the modulated data signal to the clock signal to obtain a mixed signal;

The input end of the signal demodulator is connected with the output end of the signal modulator; the signal demodulator is used for acquiring the mixed signal and demodulating a data signal from the mixed signal.

Optionally, the circuit for transmitting data by using a clock signal further includes a clock restorer;

The input end of the clock restorer is connected with the output end of the signal modulator; the clock restorer is used for acquiring the mixed signal and restoring a clock signal from the mixed signal; the signal demodulator is also used for acquiring the clock signal recovered by the clock recoverer.

Optionally, the modulation mode of the signal modulator includes pulse width modulation, binary on-off keying, and binary phase shift keying.

Compared with the prior art, the beneficial effects of the utility model are that:

The utility model provides a circuit through clock signal transmission data, include: a signal modulator and a signal demodulator; the input end of the signal modulator is connected with the data signal end and the clock signal end; the signal modulator is used for acquiring a data signal and a clock signal, modulating the data signal to obtain a modulated data signal, and loading the modulated data signal to the clock signal to obtain a mixed signal; the input end of the signal demodulator is connected with the output end of the signal modulator; the signal demodulator is used for acquiring the mixed signal and demodulating a data signal from the mixed signal. Data are transmitted through the clock signals, the data signals are superposed on the clock signals, the data signals and the clock signals are transmitted in a mixed mode through one transmission line, wiring can be reduced, the structure of a circuit is simplified, and design difficulty is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a circuit for transmitting data through a clock signal according to embodiment 1 of the present invention;

Fig. 2 is a schematic structural diagram of a circuit for transmitting data through a clock signal according to embodiment 2 of the present invention;

Fig. 3 is a waveform diagram before and after modulation of a PWM signal according to an embodiment of the present invention;

Fig. 4 is a waveform diagram before and after OOK signal modulation provided by the embodiment of the present invention;

Fig. 5 is a waveform diagram before and after modulation of a BPSK signal provided by an embodiment of the present invention;

Fig. 6 is a schematic structural diagram of a clock restorer according to an embodiment of the present invention;

Fig. 7 is a signal waveform diagram of a clock restorer when OOK signal modulation is adopted in the embodiment of the present invention;

Fig. 8 is a waveform diagram of a signal of a clock restorer when BPSK modulation is adopted.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Example 1

Fig. 1 is a schematic structural diagram of a circuit for transmitting data through a clock signal according to embodiment 1 of the present invention. Referring to fig. 1, the circuit for transmitting data by a clock signal of the present embodiment includes: a signal modulator 101 and a signal demodulator 102; the input end of the signal modulator 101 is connected with a data signal end and a clock signal end; the signal modulator 101 is used for acquiring a data signal V _D1And a clock signal Clk ₁And for the data signal V _D1Modulating to obtain modulated data signal, and loading the modulated data signal to the clock signal Clk ₁To obtain a mixed signal Clk ₂(ii) a The input end of the signal demodulator 102 is connected with the output end of the signal modulator 101; the signal demodulator 102 is used for obtaining the mixed signal Clk ₂And from said mixed signal Clk ₂In which a data signal V is demodulated _D3。

The signal modulator 101 and the signal demodulator 102 are very basic circuits in the field of communications. In this embodiment, the signal modulator 101 and the signal demodulator 102 both adopt existing common devices, the selected model is not limited, the signal modulator 101 only needs to be capable of realizing modulation, and the signal demodulator 102 only needs to be capable of realizing demodulation.

As an alternative embodiment, the signal is modulated The device 101 is used for data signal V _D1The Modulation is performed by a Pulse Width Modulation (PWM) method.

The data circuit is transmitted through the clock signal, the data signal is superposed on the clock signal, the data signal and the clock signal are transmitted in a mixed mode through one transmission line, wiring can be reduced, the structure of the circuit is simplified, and design difficulty is reduced.

Example 2

Fig. 2 is a schematic structural diagram of a circuit for transmitting data through a clock signal according to embodiment 2 of the present invention. Referring to fig. 2, the circuit for transmitting data by clock signal of the present embodiment includes: a signal modulator 201, a clock recoverer 202, and a signal demodulator 203, wherein:

The input end of the signal modulator 201 is connected with a data signal V _D1And a clock signal Clk ₁For converting the data signal V _D1Modulated and loaded to clock signal Clk ₁Up, output mixed signal Clk ₂(ii) a The clock restorer 202 for recovering the clock from the mixed signal Clk ₂In-process recovery of clock signal Clk ₃(ii) a The signal demodulator 203 is used for passing the clock signal Clk ₃From the mixed signal Clk ₂In which a data signal V is demodulated _D2。

As an optional implementation, the signal modulator 201 has three signal modulation modes: (1) PWM (Pulse width Modulation) according to the data signal V _D1Modulating a clock signal Clk ₁The duty cycle of (c). Such as: clock signal Clk ₁Duty ratio is 50%, when data signal V _D1When 1, the output mixed signal Clk ₂The duty cycle is 75%; when the data signal V _D1When 0, the output mixed signal Clk ₂The duty cycle is 25% as shown in fig. 3. (2) OOK (On-off keying) according to the data signal V _D1Modulating a clock signal Clk ₁The amplitude of (d). When the data signal V _D1When 1, the output mixed signal Clk ₂Amplitude of and clock signal Clk ₁The same is true; when the data signal V _D1When 0, the output mixed signal Clk ₂The amplitude of (d) is 0 as shown in fig. 4. (3) BPSK (Binary Phase Shift Keying) based on a data signal V _D1Modulating a clock signal Clk ₁The phase of (c). When the data signal V _D1When 1, the output mixed signal Clk ₂And the clock signal Clk ₁The same is true; when the data signal V _D1When 0, the output mixed signal Clk ₂And the clock signal Clk ₁Instead, as shown in fig. 5.

As an alternative embodiment, the data signal V _D1When the PWM method is used for modulation, the clock recovery unit 202 can be selected according to the performance requirement of the circuit. When the data signal V _D1When OOK and BPSK modulation are used, the clock signal is recovered by the clock recoverer 202.

The structure of the clock recoverer 202 is shown in fig. 6. The clock restorer 202 comprises a phase detector 301 and a tunable clock generator 302, and the working principle is as follows: the clock recoverer 202 compares the phase difference between the output signal and the input signal through the phase detector 301, thereby adjusting the frequency of the signal output by the tunable clock generator 302. If the phase of the output signal is smaller than that of the input signal, the phase discrimination signal is slow, and the adjustable clock generator 302 adjusts the frequency fast at the moment; if the phase of the output signal is greater than the phase of the input signal, the phase of the phase-discriminated signal is fast, and the tunable clock generator 302 then tunes the frequency slowly.

When the data signal V _D1When the OOK modulation scheme is adopted, the clock restorer 202 compares the phase difference between the output signal and the input signal only when there is an input signal (when there is no input signal, the phase-detected signal is zero), and the waveform diagram is shown in fig. 7.

When the data signal V _D1When the BPSK modulation method is adopted, the clock restorer 202 compares the phase difference between the output signal and the input signal only at the rising edge and the falling edge of the input signal (when the input signal has no edge, the phase detection signal is zero), and the waveform diagram is as shown in fig. 8.

In the circuit for transmitting data through a clock signal provided by this embodiment, first, a data signal is modulated and loaded onto the clock signal for transmission in a PWM/OOK/BPSK manner; and then recovering the clock signal at the data receiving end, and demodulating the data signal through the recovered clock signal. The utility model provides a circuit is simple to can reduce and walk the line.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principle and the implementation of the present invention are explained herein by using specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. In summary, the content of the present specification should not be construed as a limitation of the present invention.

Claims

1. A circuit for transmitting data via a clock signal, comprising: a signal modulator and a signal demodulator;

2. The circuit for transmitting data by a clock signal according to claim 1, further comprising a clock recoverer;

3. The circuit according to claim 1 or 2, wherein the modulation scheme of the signal modulator comprises pulse width modulation, binary on-off keying and binary phase shift keying.