CN1383299A - Method and circuit for resetting source service clock by residual time mark method - Google Patents

Abstract

This invention relates to a method of a source service clock restoring with the remanent time-mark method and its circuit comprising a remanent time-mark buffer used in receiving the remanent time-marks, a remanent time-mark comparator comparing the received remanent time-marks and the generated local remanent time-marks and a filter which filters the comparison result to generate a control value K, a numerical control oscillator generating local service with the reference clock as the primary frequency and controlled by K and a local remanent time-mark generating module based on the local service clock and a network clock. The whole adjustment process is to recover the source service clock by approximating to the source service clock continuously by the local service clock.

Description

Carry out the method and the circuit of resetting source service clock with residual time mark method

The present invention relates to a kind of clock recovery technology of atm network transmission receiving terminal, relate to a kind of or rather in ATM (asynchronous transfer mode, Asynchronous Transfer Mode) the resetting source service clock implementation method of carrying CBR business (the CBR business also is called circuit emulation service, Constant Bit Rate) and realization circuit in the network.

Atm technology is a kind of technology of transmitting and exchanging multiple business such as voice, data, image can unified in consolidated network.In order to adapt to the carrying to multiple business, ITU-T (International Telecommunications Union) has carried out classification and has formulated corresponding AAL (ATM Adaptation Layer) agreement at the characteristic of business.The AAL agreement that has defined at present has AAL1, AAL2, AAL3/4, AAL5, and wherein the pairing business of AAL1 agreement is exactly the CBR business.Common CBR business has data flow such as E1, E3, T1, T3.The CBR business can realize atm network with original internetwork interconnected based on time division multiplexing, and this has very important meaning for the investment that makes full use of legacy network equipment.

A very crucial technology is exactly to recover the source business clock at receiving terminal in the CBR business.ITU-T has defined two kinds of methods of recovering the source business clock in I.363.1: a kind of is adaptive clock method (ACM, Adaptive Clock Method), is based on the recovery that how much realizes the source business clock of the data of being received in the cell reception buffer; Another is synchronous notation remaining time (SRTS, SynchronousResidual Time Stamp Method), is called for short residual time mark method, is based on the recovery that difference between source business clock and the atm standard network clocking realizes the source business clock.At synchronous remaining time of notation, clearly defined the shake and the drift index of the source business clock that is recovered in the ITU-T suggestion I.363.1, must meet the G.823 regulation of suggestion.Therefore except will recovering the identical clock of homology business clock frequency, the shake and the drift of control clock also are very important.

Clock in ATM physical layer transceiver information is a synchronised clock, is called the ATM system clock.Under the situation of knowing difference between source business clock and the ATM system clock,, just can go out the source business clock by the ATM system clock recovery at receiving terminal according to this difference.

In conjunction with referring to Fig. 1, the sign principle of remaining time synchronously shown in the figure.Fs is source business clock (frequency), and Fn is network clocking (frequency), and Fnx is the derived grid clock, Fnx=Fn/X (directly do not use Fn in actual applications usually, but with the derived grid clock Fnx of Fn behind the X frequency division).N is a source business clock periodicity, and T is the residual time mark cycle, T=N/Fs, and M (normal Mnom, maximum Mmax, minimum Mmin) is the periodicity of Fnx in a residual time mark period T, Mq is the integer that is less than or equal to M.

The cycle of N source business clock Fs is a residual time mark period T, and can obtain thus has Mq Fnx in a residual time mark period T.Since know Mq, Fnx and N, so just can recover source business clock Fs at receiving terminal.Yet Mq can be regarded as and is made up of its nominal section and remainder, the corresponding nominal frequency of the Mnom of nominal section, therefore also can obtain at receiving terminal, what in fact need just passes to receiving terminal with the remainder of Mq and just can realize resetting source service clock at receiving terminal.

According to I.363.1 suggestion, for the E1 business of 2.048MHz, N gets 3008, and Fnx gets 2.43MHz.

More than simple what introduce is the basic conception of synchronous remaining time of sign, more detailed content can be with reference to I.363.1.

Referring to Fig. 2,, further specify to utilize and indicate the technical scheme of recovering the source business clock synchronous remaining time in conjunction with the segmentation of E1 data flow and the realization of reorganization (SAR, Segmentation And Reassembly) function.

21 is the E1 data flow that receive among Fig. 2, the 22nd, the receiver module of E1 data flow, the 23rd, the residual time mark generation module, the 24th, header, the SAR head, residual time mark (SRTS) insert module, the 25th, the cell sending module, the 26th, the cell receiver module, the 27th, header, the SAR head, residual time mark (SRTS) abstraction module, the 28th, residual time mark (SRTS) clock recovery module, the 29th, the cell data buffer, the 210th, the sending module of E1 data flow, the 211st, the E1 data flow that sends, the 212nd, the source business clock Fs that receives, the 213rd, network clocking Fn, the 214th, from the cell signal of atm network, the 215th, the local service clock that recovers, the 216th, to the cell signal of atm network output.

E1 data flow receiver module 22 receives E1 traffic spike 21, and under the control of the source business clock 21 (Fs) that receives the E1 traffic spike is carried out synchronous searching achieve frame location; Residual time mark (SRTS) generation module 23 utilizes network clocking (Fn) 213 and source business clock (Fs) 212 to calculate, and produces residual time mark (SRTS) signal and send header, SAR head, residual time mark (SRTS) insert module 24 with the E1 data flow through frame alignment.Module 24 produces header, SAR head, and the residual time mark (SRTS) of module 23 generations is inserted into the appropriate location, forms cell signal, by cell sending module 25 cell signal is sent to atm network and gets on.

Other direction, receive cell signal 214 by cell receiver module 26 from atm network, by header, the SAR head, residual time mark (SRTS) abstraction module 27 is finished header and is extracted, the SAR head extracts and residual time mark (SRTS) extracts, the payload of 47 bytes in the cell signal is write buffer memory in the cell data buffer 29, and being sent into residual time mark clock recovery module 28, the residual time mark (SRTS) that extracts carries out clock recovery, clock recovery module 28 recovers local source business clock 215 under the control of network clocking (Fn) 213 and reference clock Fr, as the read data clock of cell data buffer 29 with as the E1 signal tranmitting data register of E1 data flow sending module 210, data by E1 data flow sending module self-confident metadata buffer 29 in 210 future send, and form signal 211.

The objective of the invention is to design a kind of method and circuit that carries out resetting source service clock with residual time mark method, be used for solving when atm network carries data flow such as comprising E1, E3, T1, T3, in the residual time mark clock recovery module, utilize residual time mark method to recover a kind of implementation method of source business clock.

The technical scheme that realizes the object of the invention is such: a kind of method of carrying out resetting source service clock with residual time mark method, residual time mark (SRTS), reference clock (Fr) and network clocking (Fn) in residual time mark receive direction utilization reception, recovery source business clock (Fsl) is characterized in that comprising:

A. the residual time mark (SRTS) that receives and the local residual time mark of generation are carried out numeric ratio;

B. compared result (Delta_rec_loc) is carried out digital filtering, produces the control signal value K of digital controlled oscillator;

C. with digital controlled oscillator under K value control the generation local service clock of reference clock (Fr) as reference frequency;

D. according to the local residual time mark of this local service clock generating;

E. continuous execution in step A to D, the local service clock that is produced by step C is exactly the source business clock (Fsl) that recovers.

Described steps A is finished by a residual time mark buffer with by a residual time mark comparator, by the temporary transient residual time mark (SRTS) that stores described reception of residual time mark buffer, and send the residual time mark comparator one end; The local residual time mark that described step D produced send the residual time mark comparator other end.

Described residual time mark comparator is finished is that to deduct the local residual time mark of generation with residual time mark (SRTS) difference that receives poor.

The residual time mark of described reception (SRTS) difference is residual time mark poor of the residual time mark of current reception and previous reception; The local residual time mark difference of described generation is local residual time mark poor of the local residual time mark of current generation and previous generation.

Described step B further comprises: by add 1/ subtract 1 arithmetic unit according to described comparative result (Delta_rec_loc) to add 1/ subtract 1 operation result (Delta-k) add 1 or subtract 1 the operation; By adder constant K 0 is added 1/ and subtracts 1 operation result (Delta-k) and carry out add operation mutually with described, adder is exported the control signal value K of described digital controlled oscillator.

The width of described adder is chosen as 26, described constant K 0 is 33547718, described 1/ initial value that subtracts 1 operation result (Delta-k) that adds selects 6714, and described 1/ minimum value that subtracts 1 operation result (Delta-k) that adds is not less than 2, and maximum is not more than 13428.

Also be included in and subtract 1 operation result (Delta-k) and add 1 or subtract 1 operation back and add 1/ and subtract that 1 operation result (Delta-k) carries out latch operation and before the control signal K value of the described digital controlled oscillator of output, adder exported and carry out latch operation described to adding 1/.

Describedly subtracting 1 operation result (Delta-k) and add 1 or subtract 1 operation adding 1/, is to be 1 o'clock at described comparative result (Delta_rec_loc), current add 1/ to subtract 1 operation result be that adding of last time 1/ subtracted 1 operation result and subtract 1; At described comparative result (Delta_rec_loc) is 15 o'clock, current add 1/ to subtract 1 operation result be that adding of last time 1/ subtracted 1 operation result and add 1; At described comparative result (Delta_rec_loc) is 2 to 14 o'clock, current add 1/ to subtract 1 operation result be last add 1/ and subtract 1 operation result.

Described step C further comprises: by the accumulator of n bit the preceding accumulation result of the n position of current K value and latch output (Sum[n-1:0]) is added up, and send latch with accumulation result; Latch carries out latch operation to accumulation result under reference clock (Fr) effect; Accumulator highest order (the Sum of latch output _N-1) be the local service clock (Fsl) that is produced.

Satisfy relation between described n, reference clock (Fr), current K value and the local service clock (Fsl) that produced: $\mathrm{Fsl}=\frac{K}{2^n}\×\mathrm{Fr}.$

Described reference clock (Fr) is 32.768MHz, and described n is 29.

Among the described step C, the frequency of the local service clock signal that digital controlled oscillator produces raises with the rising of input K value, reduces with the reduction of importing the K value.

Described step D further comprises: by a frequency divider described local service clock is carried out frequency division, produce the residual time mark cycle; By another frequency divider described network clocking is carried out frequency division and produce the derived grid clock; By counter to the derived grid clock count; By latch according to residual time mark cycle and the described local residual time mark of derived grid clock generating.

A described frequency divider is 3008 frequency dividers, and described another frequency divider is 3/64 frequency divider, and described counter is 4 bit counter, and described local residual time mark is 4 bits.

In the described step e, be to occur at described comparative result (Delta_rec_loc) that 1 and 15 number of times equates and when alternately occurring, the local service clock that is produced is exactly the source business clock (Fsl) that recovers.

The technical scheme that realizes the object of the invention still is such: a kind ofly carry out the circuit of resetting source service clock with residual time mark method, it is characterized in that comprising:

Receive the residual time mark buffer of residual time mark (SRTS), the residual time mark (SRTS) that receives and the local residual time mark of generation are carried out numeric ratio residual time mark comparator, comparative result to the residual time mark comparator carries out the digital filter that filtering produces controlling value K, be subjected to K value control and be that reference frequency produces the local service clock and recovers the numerically-controlled oscillator of source business clock (Fsl) and according to the local residual time mark generation module of local service clock and the local residual time mark of network clocking (Fn) generation through the process of progressively approaching with reference clock (Fr).

Described residual time mark comparator is connected and composed by first subtracter, second subtracter and the 3rd subtracter; Described first subtracter subtracts to the residual time mark of current reception and the residual time mark that last time receives, described second subtracter subtracts to the local residual time mark of current generation and the local residual time mark that last time produces, and described the 3rd subtracter subtracts to the output result of first subtracter and second subtracter.

Method and the circuit that carries out resetting source service clock with residual time mark method of the present invention, by analyzing the rule of data flow (as the E1 business) residual time mark of carrying CBR business in the atm network, compare with the numerical value (reflecting frequency difference) of residual time mark comparator the residual time mark of the local residual time mark that recovers and reception, again with of the output of this difference reaction to digital filter, and then control the local service clock by digital controlled oscillator and constantly approach to the source business clock, realize the recovery of source business clock.

Of the present inventionly carry out the method and the circuit of resetting source service clock with residual time mark method, the algorithm that is adopted is simple and the circuit realizability is strong, all can realize with programmable logic device or application-specific integrated circuit (ASIC) (ASIC).Because the recovery process of source business clock is a process of progressively approaching, thereby its process do not have big concussion, also can not produce the over control of clock.

Further specify method of the present invention below in conjunction with embodiment and accompanying drawing.

Fig. 1 indicates schematic diagram synchronous remaining time

Fig. 2 is a functional block diagram of realizing E1 data flow segmentation and reorganization (SAR).

Fig. 3 is the residual time mark production process principle and the circuit block diagram of residual time mark generation module among Fig. 2.

Fig. 4 is the present invention finishes resetting source service clock at the residual time mark receive direction principle and a circuit block diagram.

Fig. 5 is detailed principle and the circuit block diagram that Fig. 4 realizes resetting source service clock.

Fig. 6 is a jitter toleration standard form curve chart.

Fig. 7 is a jitter transfer standard form curve chart.

Addressed before Fig. 1 and Fig. 2 illustrate and repeated no more.

Referring to Fig. 3, be the functional structure block diagram of residual time mark generation module 23 among Fig. 2.

The production method of residual time mark has been described in the I363.1 of ITU-T.Residual time mark generation module 23 comprises business clock frequency division module 31, latch module 32, counting module 33 and network clocking frequency division module 34.Concerning the E1 data flow, business clock frequency division module 31 is one 3008 frequency dividers, and business clock Fs is carried out 3008 frequency divisions, produces residual time mark (SRTS) cycle 39, this business clock fractional frequency signal 39 is sent into latch module 32 as latch signal, is used to latch the dateout of counting module 33; Concerning the E1 data flow, network clocking frequency division module 34 is one 3/64 frequency dividers, network clocking Fn is carried out 3/64 frequency division, the fractional frequency signal 38 that obtains is derived grid clock Fnx (Fnx=Fn/X, X is 3/64), counting module 33 is counters of one 4 bits (4bit), and derived grid clock 38 is counted, the dateout of 32 pairs of counting modules 33 of latch module latchs, and output forms the residual time mark (SRTS) 37 of 4 bits (4bit).

Because the frequency of network clocking Fn adopts 51.84MHz, so the divide ratio of frequency divider 34 (X) adopts 3/64 (Fnx=2.43MHz).Can select suitable divide ratio for use according to concrete network clocking in the practical application.Because between the network clocking Fn of source business clock Fs and ATM is asynchronous clock, in the implementation procedure of physical circuit, also will take suitable Synchronous Processing to guarantee reliably to produce residual time mark (SRTS).

Referring to Fig. 4, finish the principle of resetting source service clock shown in the figure at the receive direction of residual time mark, be principle, the structured flowchart of the present invention, the residual time mark (SRTS) that is extracted by module 27 is recovered the local service clock under the control of network clocking Fn (actual is derived grid clock Fnx), reference clock (Fr) residual time mark clock recovery module 28 functions among realization Fig. 2.Its structure is similar with most phase-locked loop structures, comprises residual time mark buffer 41, residual time mark comparator 42, local residual time mark generation module 44, digital filter 43 and the controlled oscillator 45 of counting the number of words (DCO is called for short digital controlled oscillator).

The residual time mark that receives (SRTS) temporarily is stored in the residual time mark buffer 41, and the residual time mark 410 of the reception of residual time mark buffer 41 outputs send the residual time mark comparator 42 1 ends; The local residual time mark 411 that is produced by local residual time mark generation module 44 send the residual time mark comparator 42 other ends; The residual time mark of 42 pairs of local residual time marks of residual time mark comparator and reception carries out frequency ratio, comparative result 415 is sent into digital filter 43 and is carried out filtering, produce the control signal (K) of signal 414 as digital controlled oscillator 45, reference clock (Fr) 413 is sent in the digital controlled oscillator 45, the clock 412 (Fsl) that is produced under the control of K signal is the local service clock of recovery, again by local service clock 412 (Fsl) the generation local residual time mark 411 of local residual time mark generation module 44 according to this recovery, the frequency of the local service clock signal of recovering (Fsl) 412 raises with the rising of input K value, reduction with input K value reduces, and promptly realizes the frequency adjustment of the local service clock of output.

For the ease of understanding illustrated operation principle, the local service clock (Fsl) 412 of hypothesis recovery earlier equals the source business clock; Local residual time mark generation module 44 is identical with the residual time mark generation module 23 of residual time mark sending direction among Fig. 2; It also is identical that the atm network of being imported is derived clock Fn, consequently the residual time mark of Jie Shouing just should not exist with the difference of residual time mark comparison in residual time mark comparator 42 of this locality, the output of residual time mark comparator 42 can control figure filter 43 output change, the business clock of local recovery also remains unchanged.

Frequency at the business clock (Fsl) 412 of local recovery is not equal under the situation of source business clock frequency, after then passing through the comparison of residual time mark comparator 42, residual time mark comparator 42 will be reflected to this species diversity on the output signal 415 of residual time mark comparator, the adjustment that digital filter 43 can raise or reduce the K value according to the output of residual time mark comparator 42.Rising or reduction along with the K value, the output frequency of controlled oscillator 45 of counting the number of words also raises accordingly or reduces, make 412 pairs of source business clocks of local service clock (Fsl) follow and constantly approach, finally make the local service clock (Fsl) 412 of local recovery equal the source business clock.

Referring to Fig. 5, shown in the figure detailed principle and the circuit structure of realizing resetting source service clock with residual time mark method, it is residual time mark buffer 41 among Fig. 4, residual time mark comparator 42, digital filter 43, the refined structure of digital controlled oscillator 45 and local residual time mark generation module 44 according to the production method of aforesaid residual time mark principle and residual time mark, is further analyzed the rule of the professional residual time mark of E1 (SRTS).

The structure of local residual time mark generation module 44 has just been saved 3/64 frequency divider with residual time mark generation module shown in Figure 3 among the figure, thereby directly introduces derived grid clock Fnx.

Each residual time mark cycle (i.e. 3008 business clock cycles) produces a new residual time mark, for ease of analyzing the initial value can suppose to begin to calculate first new residual time mark hour counter (33) also is zero, and the frequency of the business clock (Fs) of input equals nominal value 2.048MHz.

Adopt following formula to calculate according to the residual time mark production method for the generation of first residual time mark:

$\frac{2.43}{2.048}\×3008=16\·X+Y$

Wherein X is for being less than or equal to

Maximum integer.

That is: $X=[\frac{2.43}{2.048\×16}\×3008$

First residual time mark SRTS1 has following relation of plane:

SRTS ₁＝[Y]

Be that SRTS1 is the maximum integer that is less than or equal to Y.

Formula below adopting for the generation of n residual time mark accordingly calculates: $\frac{2.43}{2.048}\×3008\·n=16\·X_n+Y_n$

X wherein _nCan obtain by following formula: $X_n=[\frac{2.43}{2.048\×16}\×n\×3008$

So n residual time mark SRTS _nCan be expressed as:

SRTS _n＝[Y _n

The initial value of supposing to begin to calculate residual time mark hour counter (33) is 0, can obtain the value of preceding 16 residual time marks so:

1，2，3，4，5，6，7，8，9，10，11，12，13，14，15，1

Scale value deducts a last residual time mark value and always equals 1 or 2 when being not difficult to find out current residual by analyzing us, in fact generally have certain frequency difference between business clock and nominal clock, but having the current residual markers equally deducts a residual time mark and always equals 1 or 2 rule, therefore: the frequency of business clock is high more, and it is just few more that the difference that the current residual markers deducts a residual time mark equals 2 number of times that occur; The frequency of business clock is low more, and it is just many more that the difference that the current residual markers deducts a residual time mark equals 2 number of times that occur.

Residual time mark comparator 42 is made up of 34 bit subtraction devices 52,53,54 among Fig. 5, the residual time mark 410 that residual time mark comparator 42 is used for the local residual time mark that produces 411 of comparison and receives is to be higher or lower than or to equal source business clock frequency with the business clock frequency of judging local recovery.In fact be not directly to compare these two residual time marks, but the difference of these two residual time marks is compared.

The output of residual time mark comparator 42 should be that to deduct the local residual time mark of recovery with the residual time mark difference that receives poor as can see from Figure 5, promptly is expressed as:

Delta_rec_loc＝Delta_srts_rec-Delta_srts_loc；

Wherein the residual time mark difference of Jie Shouing is residual time mark poor of adopting the residual time mark of current reception and previous reception, the local residual time mark difference of recovering is local residual time mark poor of adopting the local residual time mark of current recovery and previous recovery, promptly is expressed as:

Delta_srts_rec＝Srts_rec_curr-Srts_rec_last

Delta_srts_loc＝Srts_loc_curr-Srts_loc_last。

Because the professional current residual markers of E1 is always than previous residual time mark big 1 or 2, the result that subtracts each other of above-mentioned two formula also just always equals 1 or 2.Therefore under the normal condition, the output of residual time mark comparator 42 has three kinds of possibilities: 1 or 15 or 0.

The output of residual time mark comparator 42 reflects the business clock of local recovery and the difference between the business clock of source, and 42 outputs of residual time mark comparator occur 1 often, illustrate that the business clock frequency of local recovery is higher than the source business clock; The output of residual time mark comparator occurs 15 often, illustrates that the business clock frequency of local recovery is lower than the source business clock.

43 is digital filters among Fig. 5.Subtract 1 arithmetic unit 58 by adding 1/, first latch 59, the adder 510 and second latch 511 are formed, the latch clock of first, second latch 59,511 adopts reference clock Fr, the output Delta-k of the 510 pairs of constant K 0 of adder and first latch 59 carries out addition, first latch 59 subtracts 1 arithmetic unit 58 feedback Delta-k signals to adding 1/, subtracts in 1 arithmetic unit 58 Delta-k is added 1 or subtract 1 operation adding 1/ according to the Delta_rec_loc of residual time mark comparator 42 outputs.The operation principle of digital filter 43 is relatively simple, produces the controlling value K of digital controlled oscillator 45 according to the output of residual time mark comparator 42.The K of these digital filter 43 outputs has following relation of plane:

K＝K0+Delta_k

Wherein K0 is a constant, and the size of Delta_k is relevant with the input Delta_rec_loc (415) of the value of previous Delta_k and digital filter 43.Use Delta_k _nThe expression currency, Delta_k _N-1The value that expression is last.Delta_k _nHave following relation of plane:

Delta_rec_loc	?Delta_Kn
		?1	?Delta_Kn-1-1
?15	?Delta_Kn-1+1
		Other	?Delta_Kn-1

The every appearance of the output of residual time mark comparator 42 one time 1, Delta_k subtracts 1; Every appearance one time 15, Delta_k adds 1.Over time, if 1 appearance often, then the relative initial value of Delta_k reduces; If 15 number of times that the occur relative initial value of Delta_k at most increase, the minimizing of Delta_k value or increase are directly reflected into the minimizing or the increase of K value.The output frequency of the minimizing of K value or increase control digital controlled oscillator 45 reduces or raises, and the business clock frequency that makes local generation is to source business clock frequency approaches.It is final when the local service clock frequency equals source business clock frequency, 1 and 15 the equal and alternately appearance of number of times appears in 42 outputs of residual time mark comparator, the K value will be shaken in very little scope, and circuit enters metastable state, and this state is called as lock-out state.

Digital controlled oscillator (DCO, Digitally Controlled Oscillator) 45 is made of accumulator 512 and a latch 513 of a n bit.The latch clock ginseng reference clock Fr of latch 513, n position (i.e. 0 to the n-1 position) Sum[n-1:0 of 512 pairs of K values of accumulator and latch 513 outputs] add up highest order (n-1 position, the i.e. Sum of accumulator 512 outputs _N-1) be the business clock Fsl of local recovery.Fsl has following relation of plane: $\mathrm{Fsl}=\mathrm{Su}{m}_{n-1}=\frac{K}{2^n}\×\mathrm{Fr}$

Wherein Fr is reference clock (frequency), and obviously the size of local service clock frequency directly is subjected to the control of K value, and reduces along with the reduction of K value, raises along with the rising of K value.

44 is local residual time mark generation module among Fig. 5.Comprise 4 bit counter 57 and latch 55 that Fsl is carried out 3008 frequency dividers 56 of frequency division, Fnx is counted.Identical with the operation principle of structure shown in Figure 3, repeat no more.

Reference clock Fr of the present invention adopts 32.768MHz, and the width that constitutes the accumulator 512 of digital controlled oscillator is selected 29, and the width of the adder 510 in the digital filter 43 is selected 26, and constant K 0 gets 33547718.The initial value of Delta_k selects 6714, and the minimum value of Delta_k is not less than 2, and maximum is not more than 13428.

According to the selection of front parameter, the minimum adjustable frequency of this resetting source service clock circuit is: $\frac{1}{2^{29}}\×32.768\mathrm{MHz}=0.06H$

The clock adjusting range is: $\frac{(33547718+2)}{2^{29}}\×32.768\mathrm{MHz}\≤\mathrm{Fsl}\≤\frac{(33547718+13428)}{2^{29}}\×32.768\mathrm{MH}$

That is:

2.047590MHz≤Fsl≤2.048409MHz

This resetting source service clock circuit can realize that the scope of clock recovery reaches ± 200ppm, can satisfy the demand of system fully.

In addition, because the figure place of adder 510 and accumulator 512 all than broad, is to avoid the sequence problem that causes too much owing to figure place during specific implementation, can consider to adopt present popular pipelining.

What the concrete circuit design of the present invention adopted is the standard cell block of 0.35 micron technology, finishes as adder 510 usefulness two-stage flowing water, and accumulator 512 adopts three grades of flowing water to finish.

Adopt method of the present invention to carry out the resetting source service clock test in E1 SAR application-specific integrated circuit (ASIC), through the test to clock recovery circuitry, the index of the source business clock of its recovery meets the requirement of ITU-TG.823 agreement defined fully.Table one and table two illustrate respectively and utilize the recovered clock jitter toleration characteristic (UIpp) that MP1550A SDH tester measures and the test result of jitter transfer function (dB).

Sequence number	Frequency (Hz)	Tolerance limit (UIpp)	Sequence number	Frequency (Hz)	Tolerance limit (UIpp)
						?1	?20	＞20.00	?11	?700	＞20.00
?2	?29	＞20.00	?12	?1,200	＞16.83
						?3	?43	＞20.00	?13	?2,100	＞9.62
?4	?63	＞20.00	?14	?3,700	＞5.46
						?5	?93	＞20.00	?15	?6,400	＞3.16
?6	?130	＞20.00	?16	?11,000	＞2.000
						?7	?180	＞20.00	?17	?19,000	＞2.000
?8	?260	＞20.00	?18	?33,000	?1.402
						?9	?360	＞20.00	?19	?58,000	?0.757
?10	?500	＞20.00	?20	?100,000	?0.456

Table 1

The 2nd, 5 row and the expression respectively of the 3rd, 6 row in the table 1: the measured result of the jitter toleration characteristic under corresponding frequencies obviously is better than by the set quota shown in the curve in Fig. 6 jitter toleration standard form.

Sequence number	Frequency (Hz)	Shift (UIpp)	Shift (dB)	Sequence number	Frequency (Hz)	Shift (UIpp)	Shift (dB)
								?1	?20	?1.5	＜-30.00	?11	?4,700	?0.766	＜-30.00
?2	?36	?1.5	＜-30.00	?12	?6,600	?0.545	＜-30.00
								?3	?66	?1.5	＜-30.00	?13	?9,200	?0.391	＜-30.00
?4	?120	?1.5	＜-30.00	?14	?13,000	?0.277	＜-30.00
								?5	?220	?1.5	＜-30.00	?15	?18,000	?0.2	＜-30.00
?6	?400	?1.5	＜-30.00	?16	?25,000	?0.2	＜-30.00
								?7	?730	?1.5	＜-30.00	?17	?36,000	?0.2	＜-30.00
?8	?1,300	?1.5	＜-30.00	?18	?50,000	?0.2	＜-30.00
								?9	?2,400	?1.5	＜-30.00	?19	?71,000	?0.2	＜-30.00
?10	?3,400	?1.05	＜-30.00	?20	?100,000	?0.2	＜-30.00

Table 2

In the table 2, the 2nd, 3,5,6 row are frequency, jitter conditions that test instrumentation provides, and the 4th, 8 row are jitter transfer function results of actual measurement, obviously are better than by the set quota shown in the curve in Fig. 7 jitter transfer standard form.

The foregoing description of the inventive method solved the implementation method of recovering the source business clock when carrying the E1 data flow in atm network with residual time mark method, but its notion can be applied to other data streaming service equally.

Claims (17)

1. one kind is carried out the method for resetting source service clock with residual time mark method, in residual time mark (SRTS), reference clock (Fr) and the network clocking (Fn) that the utilization of residual time mark receive direction receives, recovers source business clock (Fsl), it is characterized in that comprising:

A. the residual time mark (SRTS) that receives and the local residual time mark of generation are carried out numeric ratio;

B. compared result (Delta_rec_loc) is carried out digital filtering, produces the control signal value K of digital controlled oscillator;

C. with digital controlled oscillator under K value control the generation local service clock of reference clock (Fr) as reference frequency;

D. according to the local residual time mark of this local service clock generating;

E. continuous execution in step A to D, the local service clock that is produced by step C is exactly the source business clock (Fsl) that recovers.

2. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 1, it is characterized in that: described steps A is finished by a residual time mark buffer with by a residual time mark comparator, by the temporary transient residual time mark (SRTS) that stores described reception of residual time mark buffer, and send the residual time mark comparator one end; The local residual time mark that described step D produced send the residual time mark comparator other end.

3. according to claim 2ly a kind ofly carry out the method for resetting source service clock with residual time mark method, it is characterized in that: described residual time mark comparator is finished is that to deduct the local residual time mark of generation with residual time mark (SRTS) difference that receives poor.

4. according to claim 3ly a kind ofly carry out the method for resetting source service clock with residual time mark method, it is characterized in that: the residual time mark of described reception (SRTS) difference is residual time mark poor of the residual time mark of current reception and previous reception; The local residual time mark difference of described generation is local residual time mark poor of the local residual time mark of current generation and previous generation.

5. according to claim 1ly a kind ofly carry out the method for resetting source service clock, it is characterized in that described step B further comprises: subtract 1 arithmetic unit and subtract 1 operation result (Delta-k) and add 1 or subtract 1 operation adding 1/ according to described comparative result (Delta_rec_loc) by adding 1/ with residual time mark method; By adder constant K 0 is added 1/ and subtracts 1 operation result (Delta-k) and carry out add operation mutually with described, adder is exported the control signal value K of described digital controlled oscillator.

6. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 5, it is characterized in that: the width of described adder is chosen as 26, described constant K 0 is 33547718, described 1/ initial value that subtracts 1 operation result (Delta-k) that adds selects 6714, described 1/ minimum value that subtracts 1 operation result (Delta-k) that adds is not less than 2, and maximum is not more than 13428.

7. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 5, it is characterized in that: also be included in and subtract 1 operation result (Delta-k) and add 1 or subtract 1 operation back and add 1/ and subtract that 1 operation result (Delta-k) carries out latch operation and before the control signal K value of the described digital controlled oscillator of output, adder exported and carry out latch operation described to adding 1/.

8. according to claim 5 or 7 described a kind of methods of carrying out resetting source service clock with residual time mark method, it is characterized in that: described to add 1/ subtract 1 operation result (Delta-k) add 1 or subtract 1 the operation, be to be 1 o'clock, current add 1/ to subtract 1 operation result be that adding of last time 1/ subtracted 1 operation result and subtract 1 at described comparative result (Delta_rec_loc); At described comparative result (Delta_rec_loc) is 15 o'clock, current add 1/ to subtract 1 operation result be that adding of last time 1/ subtracted 1 operation result and add 1; At described comparative result (Delta_rec_loc) is 2 to 14 o'clock, current add 1/ to subtract 1 operation result be last add 1/ and subtract 1 operation result.

9. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 1, it is characterized in that described step C further comprises: by the accumulator of n bit the preceding accumulation result of the n position of current K value and latch output (Sum[n-1:0]) is added up, and send latch with accumulation result; Latch carries out latch operation to accumulation result under reference clock (Fr) effect; Accumulator highest order (the Sum of latch output _N-1) be the local service clock (Fsl) that is produced.

10. according to claim 9ly a kind ofly carry out the method for resetting source service clock, it is characterized in that: satisfy relation between described n, reference clock (Fr), current K value and the local service clock (Fsl) that produced with residual time mark method: $\mathrm{Fsl}=\frac{K}{2^n}\×\mathrm{Fr}.$

11. according to claim 10ly a kind ofly carry out the method for resetting source service clock with residual time mark method, it is characterized in that: described reference clock (Fr) is 32.768MHz, and described n is 29.

12. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 1, it is characterized in that: among the described step C, the frequency of the local service clock signal that digital controlled oscillator produces raises with the rising of input K value, reduces with the reduction of importing the K value.

13. according to claim 1ly a kind ofly carry out the method for resetting source service clock, it is characterized in that described step D further comprises: by a frequency divider described local service clock is carried out frequency division, produce the residual time mark cycle with residual time mark method; By another frequency divider described network clocking is carried out frequency division and produce the derived grid clock; By counter to the derived grid clock count; By latch according to residual time mark cycle and the described local residual time mark of derived grid clock generating.

14. a kind of method of carrying out resetting source service clock with residual time mark method according to claim 13, it is characterized in that: a described frequency divider is 3008 frequency dividers, described another frequency divider is 3/64 frequency divider, described counter is 4 bit counter, and described local residual time mark is 4 bits.

15. according to claim 1 or 8 described a kind of methods of carrying out resetting source service clock with residual time mark method, it is characterized in that: in the described step e, be to occur at described comparative result (Delta_rec_loc) that 1 and 15 number of times equates and when alternately occurring, the local service clock that is produced is exactly the source business clock (Fsl) that recovers.

16. one kind is carried out the circuit of resetting source service clock with residual time mark method, it is characterized in that comprising: the residual time mark buffer that receives residual time mark (SRTS), the residual time mark (SRTS) that receives and the local residual time mark of generation are carried out numeric ratio residual time mark comparator, comparative result to the residual time mark comparator carries out the digital filter that filtering produces controlling value K, be subjected to K value control and be that reference frequency produces the local service clock and recovers the numerically-controlled oscillator of source business clock (Fsl) and according to the local residual time mark generation module of local service clock and the local residual time mark of network clocking (Fn) generation through the process of progressively approaching with reference clock (Fr).

17. according to claim 16ly a kind ofly carry out the circuit of resetting source service clock with residual time mark method, it is characterized in that: described residual time mark comparator is connected and composed by first subtracter, second subtracter and the 3rd subtracter; Described first subtracter subtracts to the residual time mark of current reception and the residual time mark that last time receives, described second subtracter subtracts to the local residual time mark of current generation and the local residual time mark that last time produces, and described the 3rd subtracter subtracts to the output result of first subtracter and second subtracter.

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