CN1147076C - Burst time-delay control device in ATM passive optic network system and its implement method - Google Patents

Abstract

The present invention discloses a method for realizing burst time delay control in ATM passive optical network systems. The method at least comprises the following steps: a, a burst time delay value TD is divided into cell (CELL) time delay, byte (BYTE) time delay and bit (BIT) time delay; b, the CELL time delay and the BYTE time delay are put together for realizing time delay through the comparison, the encoding, the shifting, the latching and the delay line time delay of a CELL module and a BYTE module to downstream permission sequences at a parallel clock rate; c, a shifting register and a high speed selector are used for realizing BIT time delay processing at a serial clock rate; d, the burst time delay value TD is dynamically adjusted through a required shifting value and an actual shifting value by a bit mapping method. The present invention also discloses a burst time delay control device used for realizing the method.

Description

Burst time-delay control device and its implementation in the ATM Passive Optical Network system

Technical field

The present invention relates to control and time delay in asynchronous transfer mode (ATM) EPON, refer to a kind of device and its implementation that can control the delay time of uplink burst cell in the ATM Passive Optical Network especially.

Background technology

Because the arrival of network times, the communication network develop rapidly that various functions are become stronger day by day is to satisfy the demand that people grow with each passing day.ATM Passive Optical Network (APON) is exactly one of them, it is that ATM broadband services and EPON (PON) technology based on the cell transmission are combined, with optical fiber as transmission medium, the communication network that can provide high-speed data and broadband services to handle, bandwidth, capacity are big.So-called PON is exactly between optical line terminal (OLT) and optical network unit (ONU), just between local side and remote subscriber, without any the optical access network of active electronic equipment.APON not only can provide broadband multimedia services more neatly, and allows a plurality of users in the Access Network to share whole bandwidth.

The APON system is that the burst time division multiple access inserts the passive optical-fiber network of (TDMA), and a local side OLT can connect a plurality of far-end ONU simultaneously in APON, as 16,32,64 or the like, and not not waiting between each ONU and OLT apart from distance.ONU will be sent to uplink service the OLT side, need be after receiving the permission (GRANT) that OLT sends, business is burst to OLT in the mode of cell (CELL).OLT will correctly receive the bursty data (CELL) of each ONU, just each ONU need be measured to the distance of OLT, promptly adopts the method for range finding to obtain OLT and specify logical reach actual between the ONU, then each ONU is adjusted to identical logical reach.And the actual control procedure that is to ONU burst delay time TD of this adjustment process, if there is not this burst time-delay controlled function, just can not finish the function of the ONU of different distance being adjusted to the identity logic distance, the upstream data that sends of each ONU so, under the situation of up shared bandwidth, just the conflict of data might occur, thereby cause ONU upstream data correctly can not be sent to OLT.

Yet, do not have a kind of effective burst delay control method can finish control at present to ONU burst delay time TD.

Summary of the invention

In view of this, main purpose of the present invention is to provide the implementation method of burst time-delay control in a kind of ATM Passive Optical Network system, makes it can realize control to the burst time-delay, and then guarantees the correct transmission of upstream data.

Further aim of the present invention is to provide the device of burst time-delay control in a kind of ATM Passive Optical Network system, makes its structural design simple, easy to operate, not only can reduce the realization difficulty greatly; And degree of regulation height; In adjusting the time-delay process, can not lose cell or produce cell fragment, thereby improve transmission quality.

For achieving the above object, technical scheme of the present invention is achieved in that

The implementation method of burst time-delay control in a kind of ATM Passive Optical Network system, key is that this method comprises the steps: at least

A1. the delay value TD that will happen suddenly is decomposed into cell (CELL), byte (BYTE), the time-delay of bit (BIT) three parts;

B1. under parallel clock speed, with CELL time-delay and BYTE time-delay lump together by CELL and BYTE module through to comparison, the coding of descending permission sequence, be shifted, latch, delay line time-delay and decoding realize delaying time;

C1. under serial clock speed, realize the BIT delay process by shift register and high speed selector;

D1. adopt and require shift value and actual shift value dynamically to adjust burst delay value TD by the way of bit mapping.

The step of above-mentioned decomposition TD comprises following several steps at least:

A2., it is N that the CELL delay value is set, and the BYTE delay value is W, and the BIT delay value is M;

B2. the value according to TD calculates median D1, D2, L1 and the L2 relevant with N, W and M value; Wherein, D1 equals TD/ (56*8) and rounds, and L1 equals TD and gets remainder divided by (56*8), and D2 equals L1/8 and rounds, and L2 equals L1 and gets remainder divided by 8;

C2. calculate the value of N in the ranging process, W and M according to median: N equals D1, and W equals D2, and M equals L2+124;

Perhaps, calculate the value of N in the course of normal operation, W and M according to median: the TD value that at first is provided with after range finding is finished is TD1, and TD is TD2 in course of normal operation, and then N equals D1, and W equals D2; M equals L2+124+ (TD2-TD1).

The described shift register of step c1 is to connect the 256 bit shift registers that constitute by the register utmost point of 256 1 bits.The described high speed selector of step c1 comprises that at least level Four four selects one multiplexer.The output of every grade of multiplexer of this high speed selector is the input through entering the next stage multiplexer again after the time-delay all.

Burst time-delay control device in a kind of ATM Passive Optical Network system, this device comprise CELL and BYTE time delay module, BIT time delay module at least;

Wherein, CELL and BYTE time delay module mainly by relatively (COMP) module, coding (ENCODE) module, phase place adjustment (PHASE_ADJUST) module, displacement (SHIFT) module, latch (LAT) module, delay line (DLY_LINE) module and decoding (DECODE) module and constitute;

Descending permission sequence is introduced into the COMP module, in the COMP module, permission is analyzed, then comparative result is sent in the ENCODE module and encoded, coding result is delivered to the SHIFT module and is shifted, when the PHASE_ADJUST module produce to allow latch signal, with the data latching in the SHIFT module to the LAT module, after time-delay, by the DECODE module coding result is decoded, deliver to corresponding operational module.

The BIT time delay module mainly is made of shift register and high speed selector; The value of shift register is exported through after the selection of high speed selector.

Described COMP module comprises four parts, is respectively applied for comparing data permission (DATAGRANT), physical layer operations maintenance management (PLOAM GRANT), range finding permission (RANGGRANT) and separates time slot permission (DIVIDED GRANT).

Described delay line (DLY_LINE) module is formed by postponing shift register.

Shift register in the BIT module is to connect the 256 bit shift registers that constitute by the register utmost point of 256 1 bits.High speed selector in the BIT module comprises that at least level Four four selects one multiplexer.The output of every grade of multiplexer of this high speed selector is the input through entering the next stage multiplexer again after the time-delay all, and this time-delay can be 1 bit.

This shows that core of the present invention just is:

At first, delay time TD being divided into CELL, BYTE and BIT three parts realizes.

Secondly, the BIT time delay module is separated with the processing of BYTE time delay module with CELL.CELL and BYTE time-delay part are merged to get up to handle, and BIT time-delay part individual processing.So, for CELL and BYTE time-delay part, because no BIT time-delay part, can adopt the parallel processing mode, then the processing clock frequency is reduced to the parallel clock frequency by the serial clock frequency, with 155.52/155.52Mbps symmetry APON system is example, is about to serial clock frequency 155.52MHz and has dropped to 19.44MHz, and then reduce the realization difficulty of hardware module in the APON system greatly.

And for BIT time-delay part, BIT time-delay part is put into up serial high speed circuit part, though clock frequency is the serial clock frequency, with 155.52/155.52Mbps symmetry APON system is example, clock frequency still is 155.52MHz, but its amount of logic is little, also is easy to realize.

CELL, BYTE, BIT three parts should be put together in fact, they are an integral body to the realization of TD time-delay control, but because CELL, BYTE section processes clock speed become very low, thus these two parts lump together handle more convenient.And BIT section processes clock speed is very high, therefore realizes separately implementing the high speed part more convenient.But from the logical construction integral body of saying so, collaborative work together can realize the time-delay control to TD.

The 3rd, in the BIT time delay module, realize the burst time-delay is controlled the dynamic adjustment of BIT precision by shift register.

The 4th, when upstream data is idle, adopt the dynamic adjustment of mapping method realization to burst delay value TD in the course of normal operation.

As can be seen from the above analysis, burst time-delay control device and its implementation in the ATM Passive Optical Network provided by the present invention system have following characteristics:

1) can realize that OLT to the correct distance measurement function of each different distance ONU, adjusts to a unified position with the logical reach of each ONU, precision is 1bit.Share under the situation of upstream bandwidth at each ONU like this, upstream data does not have data collision, thus correct realization to the transmission of upstream data.

2) because the present invention is divided into CELL, BYTE, BIT three parts with delay value, and CELL and BYTE part handled according to parallel method, and the BIT part is handled by serial mode separately, so, just the logical process frequency with CELL and BYTE part has dropped to 19.44MHz, though the processing frequency of BIT part still is 155.52MHz, because of its amount of logic is little, implements also not difficult.Therefore, structural design of the present invention is not only simple, easy to operate, and greatly reduces the realization difficulty.

3) with the moment of delay time TD in the upstream data free time, carry out among a small circle dynamic adjustment in BIT time-delay part, can avoid causing cell loss concealment and cell fragment because of adjusting delay time TD.

Description of drawings

Fig. 1 for the present invention happen suddenly the time-delay controlled function schematic diagram is described;

Fig. 2 is CELL among the present invention and BYTE time delay module realization block diagram;

Fig. 3 is that the phase place of CELL and BYTE time delay module is adjusted sequential chart;

Fig. 4 is the detailed sequential chart of Latch_En signal;

Fig. 5 is the sequential chart that first group of permission data shift advances shift register;

Fig. 6 is the sequential chart that second group of permission data shift advances shift register;

Fig. 7 is the detailed sequential chart of LAT module in CELL and the BYTE time delay module;

Fig. 8 realizes the BIT precision for the BIT time delay module and adjusts the schematic diagram of function;

Fig. 9 is the flow chart of the inventive method.

Embodiment

Relevant detailed description of the present invention and technology contents, conjunction with figs. is described as follows:

The present invention is divided into CELL, BYTE, BIT three section processes with delay value TD, supposes that now the CELL delay value is that N, BYTE delay value are that W, BIT delay value are M.So, how TD is decomposed specifically is to finish by following decomposition formula:

D1=TD/ (56*8)＜merchant rounds 〉, L1=TD% (56*8)＜delivery 〉;

D2=L1/8＜merchant rounds 〉, L2=L1%8＜delivery 〉;

The value of N, W, M is in ranging process:

N＝D1；W＝D2；M＝L2+124

The value of N, W, M is in course of normal operation: (the TD value of establishing after range finding is finished is TD1, changes into TD2 in course of normal operation)

N＝D1；W＝D2；M＝L2+124+(TD2-TD1)

Give an example, TD is 1429 bits under distance measuring states, then:

D1＝1429/(56*8)＝3；L1＝1429％(56*8)＝85；

D2＝L1/8＝85/8＝10；L2＝L1％8＝85％8＝5；

So, the value of N, W, M is respectively:

N＝D1＝3；W＝D2＝10；M＝L2+124＝129

Suppose that the delay value when the ONU distance measuring states finishes is 1429 bits, when ONU was in normal operating conditions, delay value was changed into 1439 bits, and then the value of N, W, M is respectively in course of normal operation:

N＝3；W＝10；M＝5+124+(1439-1429)＝139

If when ONU was in normal operating conditions, delay value became 1408 bits, then the value of N, W, M is respectively in course of normal operation:

N＝3；W＝10；M＝5+124+(1408-1429)＝108

The value of N, W, M is the corresponding calculating gained of value according to TD, and TD obtains by OLT.

The functional description of burst time-delay control as shown in Figure 1, its major function is: according to the descending GRANT sequence that OLT sends, the uplink burst cell that decision ONU sends.Wherein the GRANT sequence be input as interrupted input, last line output cell sends for burst, output CELL order should with the order strict conformance of GRANT sequence, the delay time TD that should guarantee the uplink burst cell simultaneously is the delay value that OLT requires.

For ONU, GRANT is descending receiving.According to each descending GRANT, up corresponding transmission be to go up row cell (CELL).The GRANT segmentation sends to ONU by the G.983.1 middle regulation of ITU_T.

The GRANT sequence of input is processing time TE by analysis, and then begins to send CELL behind the delay time TD through the OLT appointment.Delay time TD dynamically adjusts in ranging process and course of normal operation, and its adjusting range in course of normal operation is little, and the adjusting range in ranging process is big.

Wherein, TE be the APON system transmission convergence layer (TC) and the range finding agreement G.983.1 in the regulation ONU to the time that descending GRANT carries out analyzing and processing, be generally 7～9CELL.

Because the APON system, descending (OLT is to ONU) adopts the Time Division Multiplexing broadcast technology, and up (ONU is to OLT) then adopts burst time division multiple access (TDMA) technology, is a typical TDM/TDMA (time division multiplexing/time division multiple access) system.The present invention adopts an OLT to connect 64 ONU, and distance can be unequal between these ONU and the OLT.In order to guarantee that all ONU can effectively share upstream bandwidth, the ONU of adjacent time-slots sends data and can not clash, and the circuit transmission quality is improved, and has G.983.1 defined a kind of range finding agreement of standard.The basic principle of ranging technology be exactly that a certain fixing logical time delay is zoomed out in unification by the loop time-delay (ONU is to OLT time-delay and the time-delay sum of OLT to ONU) of TD with all ONU, and TD is realized by time-delay mechanism.

So ONU is according to each descending GRANT, during the up CELL of corresponding transmission, must add TE and TD in front.

Referring to shown in Figure 2, Fig. 2 has provided the realization block diagram of CELL and BYTE time delay module.CELL and BYTE time-delay mould determines mainly by relatively (COMP) module, coding (ENCODE) module, phase place adjustment (PHASE_ADJUST) module, displacement (SHIFT) module, latch (LAT) module, delay line (DLY_LINE) module and decoding (DECODE) module constitutes.Wherein, the COMP module mainly realizes the analytic function of GRANT, and the GRANT that will belong to this ONU analyzes out; The function of ENCODE module is that comparative result is encoded to reduce follow-up realization amount of logic; The major function of SHIFT and LAT is the result behind the coding to be shifted latch, and is convenient to follow-up delay operation; The PHASE_ADJUST module is based on the time-delay reference signal, and producing one-period is the byte efficient clock enable signal of 56CELL, is mainly used in to adjust the BYTE time-delay; The DLY_LINE module is that the GRANT that will latch moves in the delay register by parallel clock Clk and clock enable signal Phase_Adjust_Clk and delays time; The function of DECODE module is that the result after the delay process is decoded, and gives other modules and carries out associative operation.

To just need the reference signal of delaying time accurately to the control of delaying time accurately of up cell, the Delay_Base reference signal of delaying time exactly, the Sof signal is the header signal of downlink frame structure.W is byte (BYTE) number that needs time-delay.Phase_Adjust_Clk produces on the basis of Sof, Delay_Base and W; Its W byte after the Delay_Base signal is effective, producing one-period is the effective clock enable signal of a byte of 56CELL.

The sequential of PHASE_ADJUST module as shown in Figure 3, wherein Clk is a parallel clock, the Latch_En signal latchs for allowing, its detailed sequential chart is shown in figure X, first of this signal is spaced apart 56*27BYTE, and second is spaced apart 56*26BYTE, and just in time the effective GRANT number corresponding to first group of descending GRANT series is 27, effective GRANT number of second group of GRANT series is that 26, two just in time corresponding up frame lengths of the length of adding up are 56*53BYTE.Simultaneously, the effective width of signal is 1BYTE.The Delay_Base signal is that an interval width is 56*53BYTE, and the signal effective width is the periodic signal of 1BYTE, 56 length that are meant up CELL herein.Among the figure, when W1, W2 represented TD decomposed, it was W1, W2 that BYTE delay value W has got two values, and W can get W1 or W2 only illustrates that BYTE delay value W is transformable.As for when getting W1, when should get W2 and depend primarily on the TD value that obtains by OLT and calculate gained according to decomposition formula.

The BYTE time-delay is exactly two enable signals that produce by the PHASE_ADJUST module: clock enable signal Phase_Adjust_Clk and permission latch signal Latch_En control and finish.

The specific implementation process of BYTE time-delay is such:

1) the GRANT sequence is by parallel mode input COMP module, and COMP analyzes after receiving these GRANT, and the GRANT that will belong to this ONU analyzes out, and comparative result is delivered to the ENCODE module.Wherein, four COMP modules are respectively to tackling the comparative analysis of four kinds of different GRANT.

For each ONU, four kinds of GRANT:DATA GRANT are arranged, PLOAMGRANT, range finding permission (RANG GRANT) separates time slot permission (DIVIDED GRANT); And the DATA GRANT of each different ONU, PLOAM GRANT are different, and RANGGRANT is consistent to each ONU, and DIVIDED GRANT can a plurality of ONU be identical, also can be different.

CP0 as a result relatively is 1 identical with the DATA GRANT of this ONU corresponding to descending GRANT, otherwise is 0; CP1 is 1 identical with the PLOAMGRANT of this ONU corresponding to descending GRANT, otherwise is 0; CP2 is 1 identical with the RANGGRANT of this ONU corresponding to descending GRANT, otherwise is 0; CP2 is 1 identical with the DIVIDED GRANT of this ONU corresponding to descending GRANT, otherwise is 0.

2) after the ENCODE module is received comparative result, this result is encoded, its coding rule as shown in Table 1:

CP3	CP2	CP1	CP0	CODE[2]	CODE[1]	CODE[0]
							0	0	0	0	0	0	0
0	0	0	1	1	0	0
							0	0	1	0	1	0	1

0	1	0	0	1	1	0
							1	0	0	0	1	1	1
EVERYTHING ELSE				0	0	0

Table one comparative result and the coded data table of comparisons

In the table one, CP0--CP3 represents the result of comparator output, and when the GRANTS code stream of input equated with the value of the corresponding four kinds of GRANTS of this ONU, corresponding result was 1, and expression OLT requires this ONU sending corresponding data with the corresponding time slot of GRANT.Owing to can only send a kind of data at each time slot, or not send data.When other comparative result occurring, show abnormal conditions to occur.The CODE[2 of output] be 1 to be illustrated in this GRANT time slot corresponding and will to send data, be 0 expression does not send data; CODE[1], CODE[0] then representative will send which kind of data, be 00 to indicate to send ATM CELL, be 01 to indicate to send PLOAM, be 10 to indicate to send RANG PLOAM, be 11 to indicate to send mini-slot (MINISLOT).

Adopt the major advantage of ENCODE to be: can mask wrong situation, avoid wrong to subordinate's transmission, behind the coding, amount of logic required during intermediate treatment has reduced 1/4th simultaneously.

3) the ENCODE module is delivered to coding in the SHIFT module and is shifted, when the LAT module receive allow latch signal Latch_En after, again with data latching in the SHIFT module to LAT.Wherein, the Latch_En signal is by the PHASE_ADJUST module, is used for exactly in the suitable moment data latching of SHIFT module being advanced the LAT module.

Fig. 7 is the detailed sequential chart in the inside of LAT module, as can be seen from Figure 7, GRANT 27 back have a place to insert 0 operation, be owing to stipulate G.983.1 that the CRC to GRANT series is the Parallel CRC of 7 bytes, and GRANT22～6 bytes of 27, therefore, for satisfying the G.983.1 regulation of agreement, must be defined in to insert subsequently by agreement and carry out CRC calculating for one 0.

It also is an operation that CRC among the figure deposits, main is exactly the descending crc value that carries because of a byte behind the 27th GRANT, do not deposit processing if do not do, promptly keep in, after CRC has been calculated in this locality slotting 0, can't compare verification with the crc value that carries, deposit the back and just can compare verification at any time.

G.983.1, TE among the figure stipulates that according to ITU_T it is fixed each system as long as satisfy the scope of 7～9 CELL.When the Latch_En signal was high among the figure, expression allowed to latch.

The CELL time-delay mainly is to realize by the DLY_LINE module, and the DLY_LINE module realizes that by postponing shift register its output is selected to be determined by N.

Fig. 5, Fig. 6 represent that respectively first group and second group of GRANT data shift advance the sequential chart of shift register.Referring to Fig. 5, Fig. 6 as can be known, the concrete operations that CELL time-delay realizes are such: the DLY_LINE module is that the GRANT that will latch moves in the delay register by parallel clock Clk and clock enable signal Phase_Adjust_Clk and delays time, and the output of delay register is selected by delay value N.When the GRANT enable signal when low, preceding 7 bytes are carried out the Parallel CRC verification.

The major function of BIT time delay module is to realize the adjustment of burst time-delay control BIT precision and the dynamic adjustment of the burst delay value TD in the course of normal operation.The adjustment of BIT precision realizes by shift register, and the dynamic adjustment of TD is by the method realization of mapping.

The specific implementation that the BIT precision is regulated is to realize the function of delaying time by the shift register of 256bit, realizes the function of high speed selector simultaneously by multistage multiplexer (MUX).As shown in Figure 8, connect the 256 bit shift registers 70 that constitute by the register utmost point of 256 1 bits and select one selection, can select the value of a certain position in the Output Shift Register through level Four four.Because actual transmission rate is too high, finishes the comparison difficulty, therefore, every grade of time-delay that all adds 1bit after multiplexing, so that hardware can simple realization.M among the figure represents the BIT delay value, and M[7:6], M[5:4], M[3:2], M[1:0] represent respectively just in time to select certain two of M corresponding one by one with the level Four of high speed selector.

Dynamic adjustment about BIT time-delay part it has been seen in that its mapping relations from the computing formula of front N, W, M, such as: add in the value of M that 124 are meant that promptly the value of M is to be fiducial value with 124bit, simultaneously can be in adjustment in the ± 124bit scope.Therefore, the scope of M value can guarantee between 0～256bit.

And the dynamic adjustment of TD mainly is the method by mapping, with the concrete mapping relations of BIT time-delay further as table two for example shown in, table two comprises three examples, each one hurdle, the example left side is to require the BIT value that is shifted, scope is between 8bit, one hurdle, the right is the actual shift value, is benchmark to require the corresponding actual shift value of shift value 0bit 124bit.

Benchmark shift value M actual shift value 0 → 124 1 → 125 2 → 126 3 → 127 4 → 128 5 → 129 6 → 130 7 → 131

Adjust shift value-3bit actual shift value-3 → 121-2 → 122-1 → 123 0 → 124 1 → 125 2 → 126 3 → 127 4 → 128

Adjust shift value+3bit actual shift value 3 → 127 4 → 128 5 → 129 6 → 130 7 → 131 8 → 132 9 → 133 10 → 134

Table two BIT shines upon the table of comparisons

So, not only can realize the time-delay of BIT precision, can support the dynamic adjustment of TD delay value in positive and negative 124bit scope simultaneously.

In sum, cooperate Fig. 9 realization of the present invention as can be seen to comprise following step at least again:

1) the delay value TD that will happen suddenly is decomposed into cell (CELL), byte (BYTE), the time-delay of bit (BIT) three parts;

2) the CELL delay value being set is N, and the BYTE delay value is W, and the BIT delay value is M;

3) value according to TD calculates median D1, D2, L1 and the L2 relevant with N, W and M value; Wherein, D1 equals TD/ (56*8) and rounds, and L1 equals TD% (56*8) delivery, and D2 equals L1/8 and rounds, and L2 equals the L1%8 delivery;

4) calculate the value of N in the ranging process, W and M according to median: N equals D1, and W equals D2, and M equals L2+124;

Perhaps, calculate the value of N in the course of normal operation, W and M according to median: the TD value that at first is provided with after range finding is finished is TD1, and TD is TD2 in course of normal operation, and then N equals D1, and W equals D2; M equals L2+124+ (TD2-TD1).

5) under parallel clock speed, with CELL time-delay and BYTE time-delay lump together by CELL and BYTE module through to comparison, the coding of descending permission sequence, be shifted, latch, delay line time-delay and decoding realize delaying time;

6) under serial clock speed, realize the BIT delay process by shift register and high speed selector;

7) employing requires shift value and actual shift value dynamically to adjust burst delay value TD by the way of bit mapping.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims (12)

1, the implementation method of burst time-delay control in a kind of passive optical network system in asynchronous transfer mode is characterized in that this method comprises the steps: at least

A1. the delay value TD that will happen suddenly is decomposed into cell, byte, the time-delay of bit three parts;

B1. under parallel clock speed, with cell time-delay and byte time-delay lump together by cell and byte module through to comparison, the coding of descending permission sequence, be shifted, latch, delay line time-delay and decoding realize delaying time;

C1. under serial clock speed, realize the bit delay process by shift register and high speed selector;

D1. adopt and require shift value and actual shift value dynamically to adjust burst delay value TD by the way of bit mapping.

2, implementation method according to claim 1 is characterized in that described decomposition burst delay value TD comprises the steps: at least

A2., it is N that the cell delay value is set, and the byte delay value is W, and the bit delay value is M;

B2. the value according to burst delay value TD calculates median D1, D2, L1 and the L2 relevant with N, W and M value; Wherein, D1 equals TD/ (56*8) and rounds, and L1 equals TD and gets remainder divided by (56*8), and D2 equals L1/8 and rounds, and L2 equals L1 and gets remainder divided by 8;

C2. calculate the value of N in the ranging process, W and M according to median: N equals D1, and W equals D2, and M equals L2+124;

Perhaps, calculate the value of N in the course of normal operation, W and M according to median: the TD value that at first is provided with after range finding is finished is TD1, and TD is TD2 in course of normal operation, and then N equals D1, and W equals D2; M equals L2+124+ (TD2-TD1).

3, implementation method according to claim 1 is characterized in that: the described shift register of step c1 is to connect the 256 bit shift registers that constitute by the register utmost point of 256 1 bits.

4, implementation method according to claim 1 is characterized in that: the described high speed selector of step c1 comprises that at least level Four four selects one multiplexer.

5, implementation method according to claim 4 is characterized in that: the output of every grade of multiplexer of described high speed selector is the input through entering the next stage multiplexer again after the time-delay all.

6, burst time-delay control device in a kind of passive optical network system in asynchronous transfer mode is characterized in that comprising at least: cell and byte time delay module, bit time delay module;

Wherein, cell and byte time delay module mainly are made of comparison module, coding module, phase adjusting module, shift module, latch module, delay line module and decoder module;

Descending permission sequence is introduced into comparison module, in comparison module, permission is analyzed, then comparative result is sent in the coding module and encoded, coding result is delivered to shift module and is shifted, when phase adjusting module produce to allow latch signal, with the data latching in the shift module to latch module, after time-delay, by decoder module coding result is decoded, deliver to corresponding operational module;

The bit time delay module mainly is made of shift register and high speed selector; The value of shift register is exported through after the selection of high speed selector.

7, overrun control according to claim 6 is characterized in that: described comparison module comprises four parts, is respectively applied for comparing data permission, physical layer operations maintenance management, range finding permission and separates the time slot permission.

8, overrun control according to claim 6 is characterized in that: described delay line module is formed by postponing shift register.

9, overrun control according to claim 6 is characterized in that: described shift register is to connect the 256 bit shift registers that constitute by the register utmost point of 256 1 bits.

10, overrun control according to claim 6 is characterized in that: described high speed selector comprises that at least level Four four selects one multiplexer.

11, overrun control according to claim 10 is characterized in that: the output of every grade of multiplexer of described high speed selector is the input through entering the next stage multiplexer again after the time-delay all.

12, overrun control according to claim 11 is characterized in that: described time-delay is 1 bit.

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