CN1378258A

CN1378258A - Multiple semiconductor die testing system and method with expandible channels

Info

Publication number: CN1378258A
Application number: CN 01110410
Authority: CN
Inventors: 张国勇
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2001-04-03
Filing date: 2001-04-03
Publication date: 2002-11-06
Anticipated expiration: 2021-04-03
Also published as: CN1260799C

Abstract

The present invention is used to test the pins of one or several semiconductor dies. The test system includes one test processing machine, one test device and one multiplexer. The test processing machine has test channels in the amount less than the number of tested pins and reads the test result from the tested pins; the test device tests the tested dies and generates the test results; and the multiplexer changes over to receive the test results in some order so that the test results can be output in turn to the test channel. The present invention has high test speed.

Description

The multiple semiconductor die testing system of extendible channel and method

The present invention relates to a kind of test macro and method of multiple semiconductor die, particularly a kind of multiple semiconductor die testing system of extendible channel and method, limited testing channel (channel) carries out the test that pin (pin) sum surpasses a plurality of tube cores of channel number in the use test processor.

Fig. 1 has shown the calcspar of a conventional semiconductors multitube die testing system.This system comprises a test handler 1 (Handler/Prober), testing apparatus 2, reaches an interface device 3.

Test handler 1 comprises a receiving system 13, puts into wafer (figure does not show) in receiving system 13, and one of them tube core to be measured (Die) 11 on the wafer is tested.Tube core 11 to be measured has eight pin P1-P8 to be measured.14 of displays from eight testing channel 15a-15h obtain respectively each pin P1-P8 test result and with its demonstration.

Testing apparatus 2 comprises test module 21 and the test machine 22 relative with tube core to be measured 11.When actual figure bit test (testing) as embedding internal memory (embedded memory), test machine 22 control test modules 21 send the to be measured pin P1-P8 of one group of test signal to tube core 11 to be measured via holding wire L1, and test result also passes after tested via holding wire L1 that module 21 transfers to test machine 22 back again.And when carrying out the analogy test, 22 of test machines skip over test module 21 and directly tube core 11 to be measured are tested.

Test machine 22 is delivered to interface device 3 via holding wire L2 with test result, sends the testing channel 15a-15h of test handler 1 behind interface device 3 switching signal joints again back to via holding wire L3.

The testing procedure that utilizes above-mentioned traditional multiple semiconductor die testing system to carry out tube core is as follows:

As shown in Figure 2, at first in step 21 first selected on wafer tube core to be measured is carried out the analogy test, the analogy character of promptly testing pin to be measured is as magnitude of voltage, current value or the like.

Then, again this tube core to be measured is carried out the numerical digit test in step 22, the logical operation function of promptly testing pin to be measured as exporting the numerical digit signal of representing special value, can be to test embedding internal memory (embedded memory) herein.

Moreover, in step 23,, then continue second tube core to be measured repeated above-mentioned

steps

21 and 22 if still have second tube core to test on the wafer; Otherwise finish test.

From the explanation of above-mentioned conventional semiconductors multitube die testing system and method, can learn, when using one group of testing channel that a plurality of tube cores are tested, if the sum of tube core is greater than the test capacity of this group testing channel or the sum of all tube cores pin to be measured during greater than the available test pin sum of this group testing channel, because testing channel deficiency, all tube cores must one then a ground use channel to test in turn, the testing time that is spent will increase with the increase of tube core number to be measured, and is very consuming time.

In addition, because when carrying out die testing, the time that the numerical digit test is spent has accounted for more than 95% of whole testing times,, whole testing times must be reduced effectively if can shorten the required time of numerical digit test.

Therefore, for overcoming above-mentioned the deficiencies in the prior art, spy of the present invention provides a kind of multiple semiconductor die testing system and method for extendible channel, when carrying out the numerical digit test, can make a plurality of test modules test simultaneously and, make and when pin sum to be measured is counted greater than testing channel, can also test fast with test result input test channel in regular turn.

One object of the present invention is to provide a kind of multiple semiconductor die testing system of extendible channel, in order to test the pin plural to be measured of at least one tube core to be measured.

Its technical scheme is: this system comprises: a test handler, a testing apparatus and a multiplexer.Wherein, test handler has the plural testing channel that sum is less than those pins to be measured, and reads the test result of pin to be measured via testing channel.The test module is tested tube core to be measured and is produced the test result of pin to be measured.Multiplexer then switches the acceptance test result in regular turn, makes test result export testing channel in turn to.

Another object of the present invention is to provide a kind of multiple semiconductor die testing system of extendible channel, in order to test a plurality of tube cores to be measured.

Its technical scheme is: this system comprises: a test handler, a testing apparatus and a multiplexer.Wherein, test handler has one group of testing channel, reads one group of test result of each tube core to be measured one by one via testing channel.Testing apparatus is tested each tube core to be measured and is produced one group of test result of each tube core to be measured.Multiplexer then receives each group test result in regular turn in turn, and exports each group test result to testing channel in turn.

Another purpose more of the present invention is to provide a kind of multiple semiconductor die method of testing, uses a test handler with one group of testing channel to cooperate a plurality of test modules that a plurality of tube cores to be measured are tested.

Its technical scheme is: wherein each test module is tested each tube core to be measured and is produced one group of test result respectively, and test handler then reads one group of test result of each tube core to be measured via testing channel.This method may further comprise the steps: at first, make those test modules simultaneously those tube cores to be measured be tested, make each group test result in producing with the time.Then, make this test handler use this group testing channel to read each group test result one by one in turn.

By above description to the object of the invention and technical scheme as can be known, the multiple semiconductor die testing system of extendible channel of the present invention and method both can be tested a plurality of tube cores to be measured again simultaneously in order to test the pin plural to be measured of at least one tube core to be measured.Above-mentioned multiple semiconductor die method of testing, because during the actual figure bit test is to allow a plurality of tube cores read its test result simultaneously more in regular turn, can not allow the testing time increase because of the increase of tube core, and the factor bit test time accounts for more than 95% of whole testing times again, so also effectively reduced whole required testing times, made the present invention reach the effect that improves test speed.

Below be accompanying drawing of the present invention:

Fig. 1 is the calcspar of a conventional semiconductors multitube die testing system;

Fig. 2 is the flow chart of a conventional semiconductors multitube core method of testing:

Fig. 3 shows the calcspar of the multiple semiconductor die testing system of extendible channel in one embodiment of the invention;

Fig. 4 shows the flow chart of multiple semiconductor die method of testing in one embodiment of the invention.

Component symbol explanation among the figure:

1 test handler 11,11a-11c tube core to be measured

13 receiving systems, 14 displays

15a-15h testing channel L1-L3 holding wire

21,21a-21c test module 22 test machines

3 interface devices, 4 multiplexers

P1-p8 pin to be measured

Below in conjunction with accompanying drawing the present invention is further described:

Fig. 3 has shown the calcspar of multiple semiconductor die testing system of the present invention, and components identical is used identical or similar symbol among Fig. 3 and Fig. 1.This system comprises test handler 1, testing apparatus 2, an interface device 3 and a multiplexer 4.

Test handler 1 comprises a receiving system 13, puts into a wafer (figure does not show) in receiving system 13, and having three tube core 11a to be measured, 11b, 11c on this wafer need test.Tube core 11a to be measured, 11b, 11c respectively have eight pin p1-p8 to be measured.14 of displays from eight testing channel 15a-15h obtain respectively each pin p1-p8 test result and with its demonstration.

Testing apparatus 2 comprises and tube core 11a to be measured, test module 21a, 21b, 21c and test machine 22 that 11b, 11c are relative.Among Fig. 3 among multiple semiconductor die testing system of the present invention and Fig. 1 traditional the different of multiple semiconductor die testing system maximum promptly be: between test module and test machine, increase by a multiplexer 4 and make native system can use one group of testing channel 15a-15h (its test capacity only is a tube core), cooperates three to test module 21a, 21b, 21c and carry out the test of three tube core 11a to be measured, 11b, 11c.The effect of multiplexer 4 is that the test result that test module 21a, 21b, 21c can be produced is switched in regular turn and exports test machine 22 to, makes test machine 22 only accept one group of test result with the time.Therefore, when actual figure bit test (as the embedding MEMTEST), because the existence of multiplexer 4, make test machine 22 can make test module 21a, 21b, 21c respectively send one group of test signal via holding wire L1a, L1b, L1c simultaneously and fetch test result simultaneously, relend by the switching of multiplexer 4 and in regular turn it is exported to test machine 22 to the pin p1-p8 to be measured of tube core 11a to be measured, 11b, 11c.When carrying out the analogy test, 22 of test machines skip over test module 21a, 21b, 21c and multiplexer 4 and directly tube core 11a to be measured, 11b, 11c are tested in the mode of taking turns.

The testing procedure that the multiple semiconductor die testing system of the invention described above carries out is as follows:

As shown in Figure 4, at first eight pin p1-p8 to be measured to 11a carry out the analogy test in step 41, and the analogy character of promptly testing pin p1-p8 to be measured is as magnitude of voltage, current value or the like.

Then, in step 42, then continue next one tube core to be measured (11b or 11c) repeating step 41 if still there is tube core not finish the analogy test on the wafer.

Eight pin p1-p8 to be measured to three tube core 11a to be measured, 11b, 11c carry out the numerical digit test simultaneously again in step 43, promptly test the logical operation function of pin p1-p8 to be measured, as export the numerical digit signal of representing special value, can be to test to embedding internal memory (embedded memory) herein.

Though the present invention discloses as above with a preferred embodiment, so it is not in order to qualification the present invention, the those of ordinary skill of any specialty, and change of being done and retouching without departing from the spirit and scope of the present invention all should be in protection scope of the present invention.

Claims

1, in order to the multiple semiconductor die testing system of a kind of extendible channel of the plural pin to be measured of testing at least one tube core to be measured, it is characterized in that: this system comprises:

Has the test handler that sum is less than the plural testing channel of those pins to be measured and is read the test result of those pins to be measured by those testing channels;

This tube core to be measured is tested and produced a testing apparatus of the test result of those pins to be measured;

Switch in regular turn and receive those test knots and make those test results export a multiplexer of those testing channels in turn to.

2. the multiple semiconductor die testing system of extendible channel as claimed in claim 1 is characterized in that: wherein this testing apparatus comprises at least one group of test module of a test signal being sent into those pins to be measured and reading the test result of those pin feedbacks to be measured.

3. the multiple semiconductor die testing system of extendible channel as claimed in claim 2 is characterized in that: wherein this testing apparatus comprises a test machine in order to the action of controlling this test module.

4. the multiple semiconductor die testing system of extendible channel as claimed in claim 3 is characterized in that: wherein this multiplexer is connected between those test modules and this test machine.

5. in order to the multiple semiconductor die testing system of a kind of extendible channel of testing plural tube core to be measured, it is characterized in that: this system comprises:

Have one group of testing channel and read a test handler of one group of test result of each tube core to be measured via this group testing channel one by one;

Each tube core to be measured is tested and produced a testing apparatus of one group of test result of each tube core to be measured;

Receive each group test result in regular turn in turn and each is organized the multiplexer that test result exports this group testing channel in turn to.

6. the multiple semiconductor die testing system of extendible channel as claimed in claim 5 is characterized in that: wherein this testing apparatus comprises that each test module sends a test signal into each tube core to be measured and read the plural number test module of the test result of each tube core feedback to be measured.

7. the multiple semiconductor die testing system of extendible channel as claimed in claim 6 is characterized in that: wherein this testing apparatus comprises in order to control a test machine of those test modules actions.

8. the multiple semiconductor die testing system of extendible channel as claimed in claim 7 is characterized in that: wherein this test machine makes those test modules simultaneously this test signal be sent into each tube core to be measured and read the test result of each tube core feedback to be measured simultaneously.

9. the multiple semiconductor die testing system of extendible channel as claimed in claim 7 is characterized in that: wherein this multiplexer is connected between those test modules and this test machine.

10. multiple semiconductor die method of testing, it is characterized in that: it uses a test handler with one group of testing channel to cooperate plural number test module that plural number tube core to be measured is tested, wherein each test module is tested each tube core to be measured and is produced one group of test result respectively, this test handler reads one group of test result of each tube core to be measured via this group testing channel, and this method may further comprise the steps:

Make those test modules simultaneously those tube cores to be measured be tested, make each group test result in producing with the time;

Make this test handler use this group testing channel to read each group test result one by one in turn.

11. the multiple semiconductor die method of testing of extendible channel as claimed in claim 10, wherein this test handler carries out the numerical digit test to those tube cores to be measured.

12. the multiple semiconductor die method of testing of extendible channel as claimed in claim 11 wherein also comprises:

A category that one by one those tube cores to be measured is carried out analogy test and produce each tube core to be measured compares test result;

This test handler when producing than test result, is read via this group testing channel each category.