CN1378216A - Flash memory multistage coding method - Google Patents
Flash memory multistage coding method Download PDFInfo
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- CN1378216A CN1378216A CN 01109531 CN01109531A CN1378216A CN 1378216 A CN1378216 A CN 1378216A CN 01109531 CN01109531 CN 01109531 CN 01109531 A CN01109531 A CN 01109531A CN 1378216 A CN1378216 A CN 1378216A
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Abstract
The flash memory multistage coding method is to apply stepped voltage waveform to both the control grid and the drain simultaneously. When one memory unit in flash memory array is coded, its drain is applied with one first stepped voltage of different voltage values while the control grid is applied with one second stepped voltage of different voltage values. Thus, the flash memory is multistage coded.
Description
The present invention relates to a kind of non-volatile (non-volatile) semiconductor memory, the detection technology of particularly a kind of flash memory (flash memory).
In traditional semiconductor memory technology, data will be written to one can erase and codified ROM (read-only memory) (erasable programmable ROM, abbreviation EPROM) in the time of in, electric charge system passes to floating boom (floating gate) via channel insulation film (tunnel insulating film), therefore suppose that this internal memory is in first state, for example store data " 0 ", and its limit voltage (threshold voltage, V
TH) be set as a high levle voltage; On the contrary, if electric charge is moved apart floating boom, its limit voltage then is a low level voltage, represents the data " 1 " of second state.In the time will reading the stored data of internal memory, the just limit voltage V by this internal memory of sensing
THSystem is in first or second state, and reads " 0 " or " 1 ".By applying a limit voltage that is higher than the limit voltage of above-mentioned high levle or is lower than low level to the control gate of internal memory, known EPROM just can reach the data of depositing two states, promptly selects first state or second state.Yet the mode of this kind coding internal memory once can only be deposited one data, so the too little shortcoming of memory capacity is arranged.
In order the coding of flash memory to be become multistage (multilevel) state, general known technology to do the control-grid voltage (word line voltages) that the genealogy of law will put on flash memory fixing, and to drain voltage (position voltage)) adjust, promptly apply a ladder voltage (step voltage) waveform, make flash memory can have different vt distributions, that is reach the purpose of multistage coding.Or, drain voltage is fixed, and adjusted the voltage that puts on the control grid.Yet the drain voltage of general flash memory has certain upper limit, can normally and inerrably be operated in order to ensure flash memory, and its voltage that puts on drain electrode just must be limited within the safe scope (safety window).That is to say that the maximum voltage that puts on drain electrode cannot surpass its disruptive voltage (breakdownvoltage) to avoid taking place perforation effect (punch through effect).Therefore, for fear of flash memory generation perforation effect, the scope of the drain voltage of internal memory is just narrowed, this also limited to flash memory can reach the memory scope of multistage coding.
From the above mentioned as can be known, limit the maximal value of drain voltage for fear of the generation of collapse phenomenon, the multistage encoding operation of known flash memory just limits to some extent, that is has limited the multistage coding range of flash memory.
Therefore purpose of the present invention is to provide a kind of flash memory multistage coding method exactly, and it can reach the purpose of flash memory being carried out multistage coding within the maximal value of the drain voltage of avoiding the flash memory collapse.
Another object of the present invention is to provide a kind of flash memory multistage coding method exactly, and it can not be subjected to the restriction of drain voltage to the coding exponent number of flash memory.
For reaching above-mentioned purpose with other, the present invention proposes a kind of flash memory multistage coding method, and it is summarized as follows:
The present invention discloses a kind of coded system of multistage flash memory.The control gate that the method ties up to a flash memory applies stepped voltage waveform simultaneously with drain electrode.
When the storage unit wherein in the flash memory array is encoded, apply the first stepped voltage in the drain electrode (bit line) of flash memory cell, wherein the first stepped voltage has a plurality of different fixed value voltages.Simultaneously between the action period of each different fixed value voltage of the first stepped voltage, apply one second stepped voltage in the control grid (character line) of flash memory, wherein the second stepped voltage has a plurality of different fixed value voltages.
Utilization applies the stepped voltage flash memory of encoding simultaneously in control grid and drain electrode, reaches the purpose of multistage coding.And the difference of each different fixed value voltage of each the different fixed value voltage of the aforesaid first stepped voltage and the second stepped voltage is being good greater than 6V, make flash memory be utilized the mode of Fu Le-Nuo Dehaimu tunneling effect (Fowler-Nordheim tunneling effect, the F-N effect) flash memory of encoding.Moreover the maximal value of those different fixed value voltages of the first stepped voltage is good with 4V, so that drain voltage can operate under normal operating voltage, causes internal memory generation perforation effect and collapses and be unlikely.In addition, more can under normal operating voltage range, operate.Therefore, method of the present invention can be avoided known method because be subjected to the influence of operating voltage range that drains, and makes the exponent number of flash memory rank coding be restricted.
Therefore, the drain electrode that feature of the present invention ties up to flash memory applies stair-stepping voltage simultaneously with the control grid, to reach the purpose of internal memory being made multistage coding.
Another feature of the present invention ties up within the normal working voltage scope of drain electrode just can reach the purpose of multistage coding, and the influence of the operating voltage range that do not drained.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, especially exemplified by preferred embodiment, and conjunction with figs., be described in detail below:
Fig. 1 is the synoptic diagram of a flash memory cell array;
Fig. 2 is the circuit block diagram that the flash memory cell array of control chart 1 reads and writes;
When Fig. 3 is wherein the storage unit of flash memory cell array of code pattern 1, the voltage oscillogram that control grid and drain electrode are applied;
Fig. 4 be the control grid with drain between pressure reduction and the graph of a relation between corresponding limit voltage; And
Fig. 5 is the distribution plan of the stored data of limit voltage and storage unit.
Wherein, parts and Reference numeral are respectively:
10 sequential circuits
12 drain electrode variable voltage oscillating circuits
14 bit line selector switchs
The variable voltage oscillating circuit of 16 control gates
18 code translators
20 memory cell arrays
M1～M16 flash memory cell
WL1～WL4 character line
BL1～BL4 bit line
S1～S4 source electrode line
Embodiment
The present invention proposes a kind of multistage coding (multilevel programming orwriting) method of flash memory.We's genealogy of law is utilized the mode of Fu Le-Nuo Dehaimu tunneling effect (Fowler-Nordheimtunneling effect, the F-N effect) flash memory of encoding.Because utilize the F-N tunneling effect flash memory of encoding, so the control grid just must be at least greater than 6V with the minimum differntial pressure between draining.
The following description will be an example with the data of eight of cell stores quadravalences (four level), but non-in order to the restriction method that the present invention carried.The data of supposing an appointment will be written to one of them storage unit in as shown in Figure 1 the memory cell arrays.The array that memory cell arrays system shown in Figure 1 is made of 16 flash memory cell M1～M16 is comprising four bit lines (bit line) BL1～BL4 and four character lines (word line) WL1～WL4.Now the appointment data is write the flash memory cell M1 that made by BL1 and WL1 as an example.
In the time will carrying out write operation to flash memory cell M1, the control grid (character line WL1) that generally ties up to storage unit applies voltage with drain electrode (bit line BL1).Operating characteristics of the present invention ties up to character line WL1 and bit line BL1 all applies stair-stepping potential pulse.
Please refer to Fig. 2, when preparation is carried out data write operation to storage unit M1, this moment, sequential circuit 10 just produced a trigger pip A to drain electrode variable voltage oscillating circuit 12, and in order to produce one first stepped potential pulse, this first stepped potential pulse is good with the equal time spacing.At this moment, just the bit line wherein in the bit line selector switch 14 select storage unit arrays 20, as bit line BL1, and the first stepped potential pulse just puts on the bit line BL1.Simultaneously, sequential circuit 10 more produces a trigger pip B and gives control grid variable voltage oscillating circuit 16, between action period in order to each different fixed value voltage in the first stepped potential pulse, produce one second stepped potential pulse, this second stepped potential pulse is good with the equal time spacing also; And just the wherein character line in the X code translator 14 select storage unit arrays 20, as character line WL1, and the second stepped potential pulse just puts on the character line WL1.Therefore, the first stepped potential pulse put on bit line BL1 during, within the action time of each different voltage definite value, the suffered voltage of character line WL1 also is stepped voltage, i.e. the second stepped voltage.
Please refer to Fig. 3, it expresses the waveform example of above-mentioned first and second stepped potential pulse (promptly being respectively bit-line voltage and word line voltages) respectively.Describe the method for operating of flash memory multistage coding of the present invention in detail by Fig. 3.Magnitude of voltage shown in graphic and action time is the usefulness of example all as an illustration, and be not in order to restriction the present invention.
In order to avoid collapsing phenomenon and higher operating speed being arranged with the F-N tunneling effect flash memory of encoding, so the minimum control grid operating voltage in this example is set 10V for, the highest drain voltage is set at 4V simultaneously.So just can reach the required voltage of minimum F-N tunneling effect and avoid the flash memory collapse.The first stepped voltage bit line BL1 voltage as shown in Figure 3 that aforesaid drain electrode variable voltage oscillating circuit 17 is produced, it is to produce certain value voltage every 2ms, is respectively 0V, 2V, 3V and 4V.During applying, total drain voltage is 8ms.At drain voltage, promptly between the action period of each fixed value voltage of the first stepped voltage, the control grid at flash memory M1 applies one second stepped voltage character line WL1 voltage as shown in Figure 3 simultaneously.This voltage is respectively 0V, 10V, 11V and 12V for to produce a magnitude of voltage every 0.5ms.For instance, for example between the action period of drain voltage 2V, the second stepped voltage that the control grid is applied simultaneously is distributed as 0V, 10V, 11V and 12V.Therefore, just between the control grid of flash memory M1 and drain electrode, produce the pressure reduction of 8V, 9V and 10V, and these pressure reduction satisfy the minimum voltage 6V of generation F-N tunneling effect.So, with this voltage distribute put on flash memory M1 can make really internal memory with the F-N tunneling effect with among the data write storage unit.
In like manner as can be known, at drain voltage, promptly the 2ms of each fixed value voltage (0V, 2V, 3V and 4V) in the first stepped voltage all applies one second stepped voltage on the control grid between action period simultaneously.By above-mentioned explanation, when first and second stepped voltage puts on the drain electrode of flash memory simultaneously respectively and controls grid, just can produce the voltage difference combination between 0V, 6V, 7V, 8V, 9V, 10V, 11V and eight different drain electrodes of 12V and the control grid.These eight different voltage differences just correspond to eight different limit voltages, and this corresponding relation as shown in Figure 4.By as can be seen shown in Figure 4, when the stepped voltage that distributes with two groups of different voltages simultaneously puts on the control gate of flash memory cell simultaneously respectively and drains, flash memory can be encoded into the capacity that can store eight different data in this example.The distribution of the voltage difference between limit voltage and drain electrode simultaneously,, the control grid presents a good linear relationship.Fig. 5 is the distribution plan of the stored data of expression limit voltage and storage unit, and figure puts on respectively on drain electrode and the control gate with first and second stepped voltage as can be seen thus, and the vt distributions that is produced parses eight different data really.
Moreover, the voltage that bit line BL1 is applied, the i.e. first stepped voltage, its maximal value only has 4V can't surpass the highest drain voltage that makes the flash memory collapse, be about 9V, thus can within the voltage range of safety, reach the purpose of multistage coding, and can not make flash memory generation perforation effect and collapse.
Utilize suitable voltage to distribute, for example by the control of voltage oscillating circuit 12 and 16, just the Control of Voltage that drain electrode can be applied is within the safe voltage scope, to produce the purpose of multistage coding.
In sum, though the present invention with preferred embodiment openly as above, it is not in order to limit the present invention; any personnel that have the knack of this technology; without departing from the spirit and scope of the present invention, when can be used for various modifications and upgrade, so the present invention's protection domain is when being as the criterion with restricted portion.
Claims (8)
1. flash memory multistage coding method in order to the flash memory cell of encoding, is characterized in that: comprising:
Drain electrode at this flash memory cell applies one first stepped voltage, and this first stepped voltage has the different fixed value voltage in plural rank;
In between the action period of each those different fixed value voltage of this first stepped voltage, apply one second stepped voltage in the control grid of this flash memory, this second stepped voltage has the different fixed value voltage in plural rank.
2. flash memory multistage coding method according to claim 1 is characterized in that: the maximal value of those different fixed value voltages of this first stepped voltage is 4V.
3. flash memory multistage coding method according to claim 1 is characterized in that: the difference of each those different fixed value voltage of this first stepped voltage and each those different fixed value voltage of this second stepped voltage is greater than 6V.
4. flash memory multistage coding method in order to the flash memory cell of encoding, is characterized in that: comprising:
Apply one first stepped voltage in the drain electrode of this flash memory cell;
In between the action period of this first stepped voltage, apply the control grid of one second stepped voltage in this flash memory.
5. flash memory multistage coding method according to claim 4 is characterized in that: the maximal value of this first stepped voltage is 4V.
6. flash memory multistage coding method according to claim 4 is characterized in that: the difference of the magnitude of voltage of the magnitude of voltage of this first stepped voltage and this second stepped voltage is greater than 6V.
7. flash memory multistage coding method according to claim 4 is characterized in that: this first stepped voltage is that the time is equidistant.
8. flash memory multistage coding method according to claim 4 is characterized in that: this second stepped voltage is that the time is equidistant.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109531 CN1249728C (en) | 2001-03-30 | 2001-03-30 | Flash memory multistage coding method |
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| CN 01109531 CN1249728C (en) | 2001-03-30 | 2001-03-30 | Flash memory multistage coding method |
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| CN1378216A true CN1378216A (en) | 2002-11-06 |
| CN1249728C CN1249728C (en) | 2006-04-05 |
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| CN 01109531 Expired - Lifetime CN1249728C (en) | 2001-03-30 | 2001-03-30 | Flash memory multistage coding method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576851B (en) * | 2008-05-06 | 2012-04-25 | 宇瞻科技股份有限公司 | Storage unit configuring method and storage medium suitable for same |
| CN103942115A (en) * | 2014-04-22 | 2014-07-23 | 湖南大学 | Data storage fault-tolerant coding method of NAND flash memory system |
| CN104425025A (en) * | 2013-08-27 | 2015-03-18 | 晶豪科技股份有限公司 | Nonvolatile semiconductor memory element |
-
2001
- 2001-03-30 CN CN 01109531 patent/CN1249728C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101576851B (en) * | 2008-05-06 | 2012-04-25 | 宇瞻科技股份有限公司 | Storage unit configuring method and storage medium suitable for same |
| CN104425025A (en) * | 2013-08-27 | 2015-03-18 | 晶豪科技股份有限公司 | Nonvolatile semiconductor memory element |
| CN104425025B (en) * | 2013-08-27 | 2017-10-24 | 晶豪科技股份有限公司 | Nonvolatile semiconductor memory element |
| CN103942115A (en) * | 2014-04-22 | 2014-07-23 | 湖南大学 | Data storage fault-tolerant coding method of NAND flash memory system |
| CN103942115B (en) * | 2014-04-22 | 2016-09-14 | 湖南大学 | A kind of data storage fault-tolerant coding method of NAND flash memory system |
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| Publication number | Publication date |
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| CN1249728C (en) | 2006-04-05 |
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Granted publication date: 20060405 |