CN1371052A - Autoamtic safe reset method of BIOS storage in computer system - Google Patents
Autoamtic safe reset method of BIOS storage in computer system Download PDFInfo
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- CN1371052A CN1371052A CN 01104726 CN01104726A CN1371052A CN 1371052 A CN1371052 A CN 1371052A CN 01104726 CN01104726 CN 01104726 CN 01104726 A CN01104726 A CN 01104726A CN 1371052 A CN1371052 A CN 1371052A
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Abstract
The persent invention discloses an automatic safe reset method of BIOS stored in computer system. The system has separate main BIOS memory for storing the first BIOS program and the second BIOS program for initiating computer system and safety BIOS resetting memory and one of them also includes a fast BIOS program. When the computer system in turned on, the safe BIOS resetting memory is first powered and the first BIOS program is checked by the error testing circuit. In case of existing some error, the content in the safe BIOS resetting memory is used to program the main BIOS memory by means of the fast BIOS program. The chip powering circuit turns off the former and turns on the latter to continue the initiation of the computer.
Description
The present invention is relevant to comprise that one replying the BIOS memory storage with a safety in the computer system of double basic input/output systems (BIOS) memory storage automatically replies a main BIOS memory storage, and the startup running when avoiding the start of computer system makes a mistake and causes the method for computer booting failure.
In the framework of computing machine now, (basic input-output system BIOS) is most basic software in the computer elementary operation to Basic Input or Output System (BIOS).BIOS mainly is made up of the instruction set of computing machine low order, the characteristic of the most basic hardware testing, definition computing machine and handle basic work when computer operating is provided.Such as: when the computer booting, the start selftest of object computer is annotated the signal that keyboard sent, and the transmission or the like of information between the connectivity port.Therefore, initial running during computing machine one start all is to carry out running according to the content of BIOS.If BIOS goes wrong, computing machine can't be carried out the test as internal memory (RAM), hard disk (HD), central processing unit (CPU) etc. once starting shooting, just then computing machine can't successfully be started shooting.
Also because BIOS has possessed consequence like this in computer system, general all can with the program instruction set quick storage of BIOS one can permanent power-source free internal memory in, as Flash ROM, PROM, EPROM, EEPROM etc., and will be built in the motherboard of computing machine in this type of BIOS internal memory or put into the chipset of computer system, make its content not influenced by the power supply power supply and can forever preserve its content.
Yet the content of BIOS internal memory is not to be not have mistake fully.When the circuit structure of BIOS internal memory produces degeneration (degradation) or is subjected to the influence of uncertain operation along with the time, its content may run off or produce mistake, produce error when causing computer booting to carry out bios program, thereby cause computing machine can't finish start.
The object of the present invention is to provide a kind of method of the BIOS of automatically replying memory storage, in order to comprise that one main BIOS memory storage and a safety replys in the computer system of two BIOS memory storages of BIOS memory storage, reply the BIOS memory storage with safety and reply defective main BIOS memory storage, start the running of computer system again with main BIOS memory storage.
For achieving the above object, the method of autoamtic safe reset BIOS memory storage of the present invention comprises the following steps: to provide one first Basic Input or Output System (BIOS) memory storage and one second Basic Input or Output System (BIOS) memory storage, described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage store one first computer program and one second computer program respectively, and described first computer program and described second computer program are used to start the running of described computer system; When described computer system power-on, the described second Basic Input or Output System (BIOS) memory storage of switching on; Detect described first computer program and whether comprise mistake; And ought comprise mistake by described first computer program of detection, with the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
According to above-mentioned conception, memory storage that the described first Basic Input or Output System (BIOS) memory storage is a programmable and the described second Basic Input or Output System (BIOS) memory storage are the memory storage of non-programmable; The second stored computer program of first computer program that the described first Basic Input or Output System (BIOS) memory storage is stored and the described second Basic Input or Output System (BIOS) memory storage can be identical or different.
The step of the described second Basic Input or Output System (BIOS) memory storage of above-mentioned energising comprises the chip power-on circuit that chip energising control end is provided, when described computer system power-on, with the described chip energising control end of the described chip power-on circuit device described second Basic Input or Output System (BIOS) memory storage of switching on; Above-mentioned chip energising control end adopts a general purpose input and output pin (GPIO pin).
Detect described first computer program and whether comprise that wrong step comprises and utilize an error detect circuit to check the error detection data value that described first computer program is included, for judging whether described first computer program comprises mistake.
Above-mentioned error detection data value can be inspection summation (checksum) data value, a coordination inspection (parity check) data value or is circulation unnecessary inspection (CRC) data value.
In order to carry out reprogramming to the described first Basic Input or Output System (BIOS) memory storage, described first Basic Input or Output System (BIOS) memory storage or the described second Basic Input or Output System (BIOS) memory storage also comprise a quick program, are used for the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
Conception according to a further aspect of the invention, the invention provides a kind of method of startup one computer system operation, described method comprises the following steps: to provide one first Basic Input or Output System (BIOS) memory storage and one second Basic Input or Output System (BIOS) memory storage, described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage store one first computer program and one second computer program respectively, and wherein said first computer program and described second computer program are used to start the running of described computer system; When described computer system power-on, the described second Basic Input or Output System (BIOS) memory storage of switching on, and detect described first computer program and whether comprise mistake; When described first computer program of detection comprises mistake, with the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming; Then, the switch on described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage that cuts off the power supply; At last, start the running of described computer system with the described first Basic Input or Output System (BIOS) memory storage.
According to above conception, the described first Basic Input or Output System (BIOS) memory storage comprises a programmable memory storage, and the described second Basic Input or Output System (BIOS) memory storage comprises a non-programmable memory storage; Stored described second computer program of described first computer program that the described first Basic Input or Output System (BIOS) memory storage is stored and the described second Basic Input or Output System (BIOS) memory storage can be identical or different.
The step of the described second Basic Input or Output System (BIOS) memory storage of wherein switching on comprises the chip power-on circuit that chip energising control end is provided, when described computer system power-on, with the described chip energising control end of the described chip power-on circuit described second Basic Input or Output System (BIOS) device of switching on; Above-mentioned chip energising control end adopts a general purpose input and output pin (GPIOpin).
Detecting described first computer program and whether comprise wrong step, is to utilize an error detect circuit to check the error detection data value that described first computer program is comprised, for judging whether described first computer program comprises mistake.
Above-mentioned error detection data value system can be inspection summation (checksum) data value, a coordination inspection (parity check) data value or is circulation unnecessary inspection (CRC) data value.
In order to carry out reprogramming to the described first Basic Input or Output System (BIOS) memory storage, described first Basic Input or Output System (BIOS) memory storage or the described second Basic Input or Output System (BIOS) memory storage also comprise a quick program, are used for the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
Purpose of the present invention, characteristics and advantage are by obtaining more deep understanding below in conjunction with accompanying drawing to the detailed description of a preferred embodiment of the present invention.
Fig. 1 is the computer system functions calcspar that comprises two BIOS memory storages according to a preferred embodiment of the present invention; And
Fig. 2 is the BIOS memory storage autoamtic safe reset method process flow diagram in according to a preferred embodiment of the present invention the computer system.
The preferred embodiment explanation
See also Fig. 1, according to a preferred embodiment of the present invention, the computer system 10 of of the present invention pair of BIOS memory storage comprises a central processing unit 11, one internal memory 12, one chip power-on circuit 13, one error detect circuit 15, and two BIOS memory storages are respectively a main BIOS memory storage (main BIOS memory device) 17 and one safety and reply BIOS memory storage (safe recovery BIOS memory device) 16.Wherein main BIOS memory storage 17 is the memory storage of a programmable, such as a quick ROM (read-only memory) (Flash ROM) or electronics can erase programmble read only memory PROM (EEPROM) composition, and safety is replied BIOS memory storage 16 and be can be a non-programmable memory storage, such as a ROM (read-only memory) (ROM) composition.
Main BIOS memory storage 17 and safety are replied BIOS memory storage 16 stored bios programs and be can be identical bios program, also can be different bios programs.And both stored bios programs all are made up of the computer program instruction set of the running that is used to start computer system 10.For can be in that the stored bios program of main BIOS memory storage 17 be detected when comprising mistake, can reply the stored bios program of main BIOS memory storage 17, main BIOS memory storage 17 or safety are replied BIOS memory storage 16 and are also comprised a quick program (flashutility), be used for safety is replied the stored bios program reprogramming master BIOS memory storage 17 of BIOS memory storage 16, so as to replying the content of main BIOS memory storage 17.
Chip power-on circuit 13 shown in Figure 1 has chip energising control end 131, for example adopt a general purpose input and output pin (GPIO pin), be used to send a power on signal to chip energising (CE) pin 171 of main BIOS memory storage 17 and chip energising (CE) pin 161 of safety answer BIOS memory storage 16, switch the BIOS memory storage of desire energising.
And the BIOS memory storage autoamtic safe reset method in the computer system of a preferred embodiment of the present invention, the understanding that can obtain by the process flow diagram of Fig. 2 filling part.See also Fig. 2.The method of autoamtic safe reset BIOS memory storage of the present invention is by step 21 beginning, and behind computer system power-on (step 22), the GPIO pin of chip power-on circuit just can make safety reply BIOS memory storage energising (step 23).At this moment, the error detect circuit of computing machine can go just to check whether the bios program that is stored in the main BIOS memory storage comprises mistake (judgement formula 24).And the technology of error-detecting can utilize inspection summation (checksum) data value or parity check (parity check) data value or unnecessary inspection (CRC) data value that circulates of checking a memory address of being scheduled to that is positioned at main BIOS memory storage whether to judge whether correctly that the content of main BIOS memory storage comprises mistake.If do not detect the mistake of any main BIOS memory storage content, then the GPIO pin of chip power-on circuit just can make safety reply the outage of BIOS memory storage and make main BIOS memory storage energising (step 26), and the running of computer booting is just proceeded (step 27) by main BIOS memory storage.Comprise mistake if detect main BIOS memory storage content, stored quick program then can be performed in then main BIOS memory storage or the safety answer BIOS memory storage, so that safety is replied the stored bios program reprogramming master BIOS memory storage of BIOS memory storage, so as to replying the content (step 25) of main BIOS memory storage.After the step of reprogramming is finished, the GPIO pin of chip power-on circuit just can make safety reply the outage of BIOS memory storage and make main BIOS memory storage energising (step 26), and the running of computer booting is just proceeded (step 27) by main BIOS memory storage.Like this, the boot program of computer system just can successfully be finished, and whether at all can not be subjected to the stored bios program of main BIOS memory storage comprises vicious influence.
In sum, the present invention utilizes a safety that stores a bios program respectively with main BIOS memory storage to reply the BIOS memory storage to come as the safe return mechanism when main BIOS memory storage is detected when comprising mistake, and quick program is stored in main BIOS memory storage or the safety answer BIOS memory storage in the lump, when making the content of the BIOS of winner memory storage be detected mistake, carry out described quick program and reply the content that the stored bios program of BIOS device is replied main BIOS memory storage with safety.Such method makes a mistake in the time of can avoiding bios program to carry out and the result that causes computing machine to start shooting, makes the startup running of computing machine smooth.
Claims (16)
- One kind in a computer system in order to reply the method for a Basic Input or Output System (BIOS) memory storage, it is characterized in that described method comprises the following steps:One first Basic Input or Output System (BIOS) memory storage and one second Basic Input or Output System (BIOS) memory storage are provided, described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage store one first computer program and one second computer program respectively, and described first computer program and described second computer program are used to start the running of described computer system;When described computer system power-on, the described second Basic Input or Output System (BIOS) memory storage of switching on;Detect described first computer program and whether comprise mistake; AndComprise mistake when detecting described first computer program, with the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
- 2. the method for claim 1 is characterized in that, the described first Basic Input or Output System (BIOS) memory storage comprises a programmable memory storage, and the described second Basic Input or Output System (BIOS) memory storage comprises a non-programmable memory storage.
- 3. the method for claim 1 is characterized in that, described first computer program is identical with described second computer program.
- 4. the method for claim 1 is characterized in that, described first computer program and described second computer program are different.
- 5. the method for claim 1 is characterized in that, the step system of the described second Basic Input or Output System (BIOS) memory storage of switching on comprises the following steps:The one chip power-on circuit with chip energising control end is provided; AndWhen described computer system power-on, with the described chip energising control end of the described chip power-on circuit device described second Basic Input or Output System (BIOS) memory storage of switching on.
- 6. method as claimed in claim 5 is characterized in that, described chip energising control end is a general purpose input and output pin (GPIO pin).
- 7. the method for claim 1 is characterized in that, detects described first computer program and whether comprises wrong step and comprise the following steps:One error detect circuit is provided;Check the error detection data value that described first computer program is comprised with described error detect circuit, for judging whether described first computer program comprises mistake.
- 8. method as claimed in claim 7 is characterized in that, described error detection data value comprises that one checks summation (checksum) data value.
- 9. method as claimed in claim 7 is characterized in that, described error detection data value comprises a coordination inspection (parity check) data value.
- 10. method as claimed in claim 7 is characterized in that, described error detection data value comprises circulation unnecessary inspection (CRC) data value.
- 11. the method for claim 1 is characterized in that, the described first Basic Input or Output System (BIOS) memory storage also comprises a quick program, in order to the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
- 12. the method for claim 1 is characterized in that, the described second Basic Input or Output System (BIOS) memory storage also comprises a quick program, is used for the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
- 13. a method that starts a computer system operation is characterized in that, described method is to comprise the following steps:One first Basic Input or Output System (BIOS) memory storage and one second Basic Input or Output System (BIOS) memory storage are provided, described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage store one first computer program and one second computer program respectively, and described first computer program and described second computer program are in order to start the running of described computer system;When described computer system power-on, the described second Basic Input or Output System (BIOS) memory storage of switching on;Detect described first computer program and whether comprise mistake;Comprise mistake when detecting described first computer program, with the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming;The switch on described first Basic Input or Output System (BIOS) memory storage and the described second Basic Input or Output System (BIOS) memory storage that cuts off the power supply; AndStart the running of described computer system with the described first Basic Input or Output System (BIOS) memory storage.
- 14. method as claimed in claim 13 is characterized in that, the step of the described second Basic Input or Output System (BIOS) memory storage of switching on also comprises the following steps:The one chip power-on circuit with chip energising control end is provided; AndWhen described computer system power-on, with the described chip energising control end of the described chip power-on circuit device described second Basic Input or Output System (BIOS) memory circuit of switching on.
- 15. method as claimed in claim 13 is characterized in that, detects described first computer program and whether comprises wrong step and more comprise the following steps:One error detect circuit is provided;Check the error detection data value that described first computer program is comprised with described error detect circuit, for judging whether described first computer program comprises mistake.
- 16. method as claimed in claim 13, it is characterized in that, the described first Basic Input or Output System (BIOS) memory storage also comprises a quick program, in order to the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming, and the described second Basic Input or Output System (BIOS) memory storage also comprises a quick program, in order to the described first Basic Input or Output System (BIOS) memory storage of the described second computer program reprogramming.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB011047267A CN1180346C (en) | 2001-02-20 | 2001-02-20 | Autoamtic safe reset method of BIOS storage in computer system |
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| CNB011047267A CN1180346C (en) | 2001-02-20 | 2001-02-20 | Autoamtic safe reset method of BIOS storage in computer system |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004104831A1 (en) * | 2003-05-06 | 2004-12-02 | Lenovo (Beijing) Limited | A method for renovating the computer operating system |
| CN1295903C (en) * | 2002-11-18 | 2007-01-17 | 华为技术有限公司 | A safe system starting method |
| CN1304947C (en) * | 2004-10-14 | 2007-03-14 | 威盛电子股份有限公司 | Switching equipment of memory analog device |
| CN1304948C (en) * | 2004-10-14 | 2007-03-14 | 威盛电子股份有限公司 | Memory analog device and method |
| CN1317650C (en) * | 2003-10-27 | 2007-05-23 | 联想(北京)有限公司 | Method for automatically recovering BIOS based on hard disk protective space |
| CN100419678C (en) * | 2004-12-04 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | BIOS updating system and method |
| CN100451987C (en) * | 2006-05-23 | 2009-01-14 | 北京金元龙脉信息科技有限公司 | System and method for carrying out safety risk check to computer BIOS firmware |
| CN101470613A (en) * | 2007-12-28 | 2009-07-01 | 华硕电脑股份有限公司 | Debugging method and starting method for computer system and its basic input/output system |
| CN101131643B (en) * | 2006-08-25 | 2010-08-25 | 佛山市顺德区顺达电脑厂有限公司 | Computer system and restoring method thereof |
| CN101840365A (en) * | 2010-04-30 | 2010-09-22 | 广州广电运通金融电子股份有限公司 | Safe protection method and system for BIOS (Basic Input/Output System) |
| CN101667128B (en) * | 2008-09-05 | 2013-11-06 | 华硕电脑股份有限公司 | Method for updating and repairing basic input and output system |
| CN107632902A (en) * | 2016-07-18 | 2018-01-26 | 衡宇科技股份有限公司 | Method, controller and the storage system of data are replied when failing for sequencing |
| CN114385247A (en) * | 2020-10-21 | 2022-04-22 | 环达电脑(上海)有限公司 | Starting-up method |
-
2001
- 2001-02-20 CN CNB011047267A patent/CN1180346C/en not_active Expired - Lifetime
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1295903C (en) * | 2002-11-18 | 2007-01-17 | 华为技术有限公司 | A safe system starting method |
| US7447888B2 (en) | 2003-05-06 | 2008-11-04 | Lenovo (Beijing) Limited | Method for restoring computer operating system |
| WO2004104831A1 (en) * | 2003-05-06 | 2004-12-02 | Lenovo (Beijing) Limited | A method for renovating the computer operating system |
| CN1317650C (en) * | 2003-10-27 | 2007-05-23 | 联想(北京)有限公司 | Method for automatically recovering BIOS based on hard disk protective space |
| CN1304948C (en) * | 2004-10-14 | 2007-03-14 | 威盛电子股份有限公司 | Memory analog device and method |
| CN1304947C (en) * | 2004-10-14 | 2007-03-14 | 威盛电子股份有限公司 | Switching equipment of memory analog device |
| CN100419678C (en) * | 2004-12-04 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | BIOS updating system and method |
| CN100451987C (en) * | 2006-05-23 | 2009-01-14 | 北京金元龙脉信息科技有限公司 | System and method for carrying out safety risk check to computer BIOS firmware |
| CN101131643B (en) * | 2006-08-25 | 2010-08-25 | 佛山市顺德区顺达电脑厂有限公司 | Computer system and restoring method thereof |
| CN101470613A (en) * | 2007-12-28 | 2009-07-01 | 华硕电脑股份有限公司 | Debugging method and starting method for computer system and its basic input/output system |
| CN101667128B (en) * | 2008-09-05 | 2013-11-06 | 华硕电脑股份有限公司 | Method for updating and repairing basic input and output system |
| CN101840365A (en) * | 2010-04-30 | 2010-09-22 | 广州广电运通金融电子股份有限公司 | Safe protection method and system for BIOS (Basic Input/Output System) |
| CN101840365B (en) * | 2010-04-30 | 2012-08-29 | 广州广电运通金融电子股份有限公司 | Safe protection method and system for BIOS (Basic Input/Output System) |
| CN107632902A (en) * | 2016-07-18 | 2018-01-26 | 衡宇科技股份有限公司 | Method, controller and the storage system of data are replied when failing for sequencing |
| CN114385247A (en) * | 2020-10-21 | 2022-04-22 | 环达电脑(上海)有限公司 | Starting-up method |
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| CN1180346C (en) | 2004-12-15 |
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