CN1366332A - Process for preparing dual-layer grid of MOS element - Google Patents
Process for preparing dual-layer grid of MOS element Download PDFInfo
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- CN1366332A CN1366332A CN 01101277 CN01101277A CN1366332A CN 1366332 A CN1366332 A CN 1366332A CN 01101277 CN01101277 CN 01101277 CN 01101277 A CN01101277 A CN 01101277A CN 1366332 A CN1366332 A CN 1366332A
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Abstract
The invention relates to a method of two layers for manufacturing component of metal-oxide semiconductor (MOS). Two layers with different etch characteristics: an adulterated polysilicon layer and a sacrificial layer formed on substrate. A dielectric layer is formed on the above-said substrate in order to cover the surface of the grid electrode structure and to expose the surface of the sacrificial layer of the grid electrode structure. Then, a metal layer replaces the sacrificial layer so as to form the grid electrode.
Description
The present invention relates to make the method for grid, and particularly relate to a kind of manufacturing metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, MOS) method of element bilayer (dual-layer) grid.
The general normal grid conductor that utilizes polysilicon to be used as metal oxide semiconductor device.Optionally remove polysilicon layer with photoetching technique, make gate oxide and passage area on patterning grid conductor covering p-type (p-type) or n-type (n-type) the MOS element.When the polysilicon gate conductor was used as conducting element, it can be in the quick and easy skew of channel position.Therefore wish that the polysilicon gate conductor has lower resistivity.And the polysilicon resistance rate for example is refractory metal or metal silicide than other metal interconnecting materials, and is also poor.No matter general polysilicon can cause tangible delay whether still very high through its resistivity of overdoping in single transmission.
Characteristics along with the semiconductor element integrated level continues to increase are applied in grid with polysilicon, must reduce its sheet resistor.A kind of method that reduces the resistance rate is to replace polysilicon with refractory metal.Refractory metal for example is an aluminium, and it is low-down that its resistivity is compared with polysilicon and silicon.Yet refractory metal exposes in manufacturing process, can't be able to stand high-temperature oxydation.Therefore refractory metal uses the back segment at fabrication schedule, for example impurity becomes and high temperature manufacturing process such as annealing in process after.
Utilize the multi-crystal silicification metal structure to reduce the resistivity of grid at present, the multi-crystal silicification metal structure is that the surface forms one deck refractory metal silicide above polysilicon conductor.Yet when the passage length of element continues reduction up to inferior micrometer range, when needing lower sheet resistor, multi-crystal silicification metal can't meet the requirements clearly.Therefore, pure fire resistance metal gates remains preferable substitute.The method that tradition is made grid structure comprises one deck polysilicon layer and the pure fire resistance metal of one deck, is disclosed at United States Patent (USP) the 4th, 908 No. 332 by Wu.
The purpose of this invention is to provide a kind of method of making double-deck grid, wherein on polysilicon layer, form a pure fire resistance metal level so that a low resistance gate to be provided.
To achieve these goals, the invention provides a kind of method of making dual-layer grid of MOS element, this method comprises:
One substrate is provided;
In this substrate, form a gate oxide;
On this gate oxide, form a doped polysilicon layer;
On this doped polysilicon layer, form a sacrifice layer;
Define this doped polysilicon layer and this sacrifice layer, form a grid structure;
This doped polysilicon layer and this sacrifice layer side at this patterning form an insulating gap wall;
In this substrate, form one source/drain region;
Form one first dielectric layer in this substrate, to cover this grid structure, this first dielectric layer is exposed with chemical mechanical milling method processing to this sacrificial layer surface;
Optionally remove this sacrifice layer to form an opening, this opening exposes this doped polysilicon layer;
Fill a metal level and enter this opening, and
Form on one second dielectric layer at this metal level and this first dielectric layer.
The present invention provides a kind of method of making dual-layer grid of MOS element on the other hand, and this method comprises:
In this substrate, form a conductive layer and a sacrifice layer successively;
Define this conductive layer and this sacrifice layer to form a grid structure;
In this substrate, form a dielectric layer covering the surface of this grid structure, and expose the surface of this sacrifice layer of this grid structure; And
Replace this sacrifice layer fully with a metal level.
According to the preferred embodiment of this invention, the doped polysilicon layer and the sacrifice layer that contain different etching characteristics form in substrate in succession, define doped polysilicon layer and sacrifice layer afterwards to form grid structure.Deposit a dielectric layer then, cover grid structure and expose the sacrificial layer surface of grid structure.Further replace sacrifice layer and form grid with metal level.
Therefore on doped polysilicon layer, form a metal level, to reduce the all-in resistance rate of grid.When sacrifice layer and doped polysilicon layer have different etching characteristics, can control well and remove sacrifice layer.So can control the thickness of metal level and doped polysilicon layer well, form the grid that contains a thin polysilicon layer and a thick metal layers.
Fully understand aforesaid prior art narration and following preferred embodiment, so that the explanation of invention patent protection scope further to be provided.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, and further provide the explanation of patent of invention scope, below especially exemplified by a preferred embodiment, and conjunction with figs. elaborates.In the accompanying drawing:
Figure 1A to Fig. 1 D is double-deck grid manufacturing process profile according to the preferred embodiment of the invention.The simple declaration of reference numerals
100 substrates
102 gate oxides
104 doped polysilicon layers
106 sacrifice layers
110 side wall spacer
112 sources/drain region
114 dielectric layers
116 openings
118 metal levels
120 grids
122 dielectric layers
Embodiment
The manufacturing process of double-deck grid illustrates with Figure 1A to Fig. 1 D respectively.
With reference to Figure 1A, it for example is silicon base that a substrate 100 is provided, and forms a gate oxide 102 thereon.Gate oxide 102 for example is to form with thermal oxidation (thermal oxidation) method.Forming a conductive layer on gate oxide 102 for example is doped polysilicon layer 104.Make doped polysilicon layer 104, be earlier with low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition traditionally, LPCVD) form one deck undoped polycrystalline silicon, inject (implanting) alloy afterwards to polysilicon layer and with annealing (annealing) heat treatment, dopant activation makes polysilicon layer conducting or doping.
Then on doped polysilicon layer 104, form a sacrifice layer 106.Sacrifice layer 106 for example is amorphous silicon layer or silicon nitride layer, and the doped polycrystalline silicon 104 of itself and below has different etching characteristics.And the thickness of sacrifice layer 106 is thick than the thickness 104 of doped polysilicon layer, and for example, sacrifice layer 106 thickness are approximately five times of doped polysilicon layer 104.Then limit sacrifice layer 106 and doped polysilicon layer 104 to form grid structure (gate structure).
Afterwards, in substrate, carry out slight injection and form side wall spacer 110 at the side of grid structure, for example be with on the structure of aforementioned generation with chemical vapour deposition (CVD) (Chemically VaporDeposit, CVD) layer of silicon dioxide layer, and with anisotropy etch-back techniques etch silicon dioxide layer to form side wall spacer 110.Further use clearance wall 110 and grid structure work as mask, with the alloy injection substrate 100 of heavy prescription amount with formation source in substrate 100/leakage (source/drain) polar region 112.
With reference to Figure 1B, on the structure of aforementioned generation, form the gate oxide 102 of a dielectric layer 114 to cover sacrifice layer 106, side wall spacer 110 and to be exposed out.Dielectric layer 114 for example is to form a thick oxide layer with chemical vapour deposition (CVD).Afterwards, utilize sacrifice layer 106 to be stop layer, (Chemical Mechanical Polishing, CMP) part of removing dielectric layer 114 is exposed up to the surface of sacrifice layer 106 with chemical mechanical milling method.
Then with reference to Fig. 1 C, sacrifice layer 106 (shown in Figure 1B) is optionally removed, and forms opening 116 and exposes polysilicon layer 104 below it.If sacrifice layer 106 is amorphous silicon or silicon nitride, can utilize helium plasma etching or Wet-type etching to remove sacrifice layer 106 respectively.When sacrifice layer 106 has different etching characteristics with doped polysilicon layer 104, can properly control removing of sacrifice layer 106, and the doped polysilicon layer 104 below keeping is complete.
With reference to Fig. 1 D, form metal level 118 with filling opening 116 (shown in Fig. 1 C).Metal level 118 for example is that tungsten is with optionally deposition formation.Metal level 118 and polysilicon layer 104 form grid 120 together.Therefore, the thickness of metal level 118 is identical with the thickness of sacrifice layer 106.Dielectric layer 122 further is deposited on the structure of aforementioned generation with isolated gate 120.
According to above-mentioned, the invention provides a kind of method of making double-deck grid, it forms a metal level to reduce the all-in resistance rate of grid on doped polysilicon layer.When metal level forms after hot manufacturing process, for example be to finish annealing heat treatment or become into manufacturing process, for example be that disadvantageous result such as high-temperature metal oxidation produces to avoid.Sacrifice layer has the etching characteristic different with polysilicon layer in addition, the removing of control sacrifice layer that can be good.Further, metal level replaces sacrifice layer and forms, rather than replaces the part of polysilicon layer with metal level, so the control metal level that also can be good and the polysilicon layer thickness of below thereof.
Though the present invention discloses as above in conjunction with a preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention should be defined by the scope of accompanying Claim.
Claims (17)
1. method of making dual-layer grid of MOS element, this method comprises:
One substrate is provided;
In this substrate, form a gate oxide;
On this gate oxide, form a doped polysilicon layer;
On this doped polysilicon layer, form a sacrifice layer;
Define this doped polysilicon layer and this sacrifice layer, form a grid structure;
This doped polysilicon layer and this sacrifice layer side at this patterning form an insulating gap wall;
In this substrate, form one source/drain region;
Form one first dielectric layer in this substrate, to cover this grid structure, this first dielectric layer is exposed with chemical mechanical milling method processing to this sacrificial layer surface;
Optionally remove this sacrifice layer to form an opening, this opening exposes this doped polysilicon layer;
Fill a metal level and enter this opening, and
Form on one second dielectric layer at this metal level and this first dielectric layer.
2. the method for manufacturing dual-layer grid of MOS element as claimed in claim 1, wherein this dielectric layer has the etching characteristic different with this doped polysilicon layer.
3. the method for manufacturing dual-layer grid of MOS element as claimed in claim 1, wherein this sacrifice layer comprises amorphous silicon.
4. the method for manufacturing dual-layer grid of MOS element as claimed in claim 3 wherein removes this sacrifice layer method and comprises the helium plasma etching.
5. as the method for the described manufacturing dual-layer grid of MOS element of claim l, wherein this sacrifice layer comprises silicon nitride.
6. the method for manufacturing dual-layer grid of MOS element as claimed in claim 5 wherein removes this sacrifice layer method and comprises Wet-type etching.
7. the method for manufacturing dual-layer grid of MOS element as claimed in claim 1, wherein this metal level comprises optionally deposits tungsten metal level.
8. the method for manufacturing dual-layer grid of MOS element as claimed in claim 1, wherein this metal layer thickness is than this doped polycrystalline silicon bed thickness.
9. method of making dual-layer grid of MOS element, this method comprises:
In this substrate, form a conductive layer and a sacrifice layer successively;
Define this conductive layer and this sacrifice layer to form a grid structure;
In this substrate, form a dielectric layer covering the surface of this grid structure, and expose the surface of this sacrifice layer of this grid structure; And
Replace this sacrifice layer fully with a metal level.
10. the method for manufacturing dual-layer grid of MOS element as claimed in claim 9, wherein the etching characteristic of this sacrifice layer is different with this conductive layer.
11. the method for manufacturing dual-layer grid of MOS element as claimed in claim 9, wherein replace this sacrifice layer fully with this metal level, further comprise optionally removing this sacrifice layer, occupied place optionally deposits this metal level before this sacrifice layer subsequently.
12. the method for manufacturing dual-layer grid of MOS element as claimed in claim 11, wherein this sacrifice layer comprises amorphous silicon.
13. the method for manufacturing dual-layer grid of MOS element as claimed in claim 12 wherein removes this sacrifice layer and comprises the helium plasma etching.
14. the method for manufacturing dual-layer grid of MOS element as claimed in claim 11, wherein this sacrifice layer comprises silicon nitride.
15. the method for manufacturing dual-layer grid of MOS element as claimed in claim 14 wherein removes this sacrifice layer and comprises Wet-type etching.
16. the method for manufacturing dual-layer grid of MOS element as claimed in claim 9, wherein in this substrate, form a dielectric layer to cover the surface of this grid structure, and expose the surface of this sacrifice layer of this grid structure, comprise with the chemical mechanical milling method of this sacrifice layer as stop layer.
17. the method for manufacturing dual-layer grid of MOS element as claimed in claim 9, wherein this metal level comprises tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01101277 CN1366332A (en) | 2001-01-17 | 2001-01-17 | Process for preparing dual-layer grid of MOS element |
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| CN 01101277 CN1366332A (en) | 2001-01-17 | 2001-01-17 | Process for preparing dual-layer grid of MOS element |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740379B (en) * | 2008-11-27 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating surface defect of semiconductor device and semiconductor device |
| WO2012071841A1 (en) * | 2010-11-30 | 2012-06-07 | 中国科学院微电子研究所 | Methods for chemical mechanical planarization and fabricating gate last |
| CN102530831A (en) * | 2010-12-27 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| US8252689B2 (en) | 2010-11-30 | 2012-08-28 | Institute of Microelectronics, Chinese Academy of Sciences | Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process |
| CN103872048A (en) * | 2012-12-17 | 2014-06-18 | 德州仪器公司 | Integrated circuit and forming method thereof |
| CN108878420A (en) * | 2017-05-15 | 2018-11-23 | 通嘉科技股份有限公司 | High-voltage semiconductor element and its production method with pulse avalanche energy |
-
2001
- 2001-01-17 CN CN 01101277 patent/CN1366332A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740379B (en) * | 2008-11-27 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating surface defect of semiconductor device and semiconductor device |
| WO2012071841A1 (en) * | 2010-11-30 | 2012-06-07 | 中国科学院微电子研究所 | Methods for chemical mechanical planarization and fabricating gate last |
| US8252689B2 (en) | 2010-11-30 | 2012-08-28 | Institute of Microelectronics, Chinese Academy of Sciences | Chemical-mechanical planarization method and method for fabricating metal gate in gate-last process |
| CN102530831A (en) * | 2010-12-27 | 2012-07-04 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| CN102530831B (en) * | 2010-12-27 | 2014-05-21 | 上海丽恒光微电子科技有限公司 | Manufacture method for MEMS (Micro-electromechanical Systems) device |
| US8877537B2 (en) | 2010-12-27 | 2014-11-04 | Lexvu Opto Microelectronics Technology (Shanghai) Ltd | Method for manufacturing MEMS device |
| CN103872048A (en) * | 2012-12-17 | 2014-06-18 | 德州仪器公司 | Integrated circuit and forming method thereof |
| CN103872048B (en) * | 2012-12-17 | 2018-05-22 | 德州仪器公司 | Integrated circuit and forming method thereof |
| CN108878420A (en) * | 2017-05-15 | 2018-11-23 | 通嘉科技股份有限公司 | High-voltage semiconductor element and its production method with pulse avalanche energy |
| CN108878420B (en) * | 2017-05-15 | 2020-08-14 | 通嘉科技股份有限公司 | High voltage semiconductor device with single pulse avalanche energy and method for fabricating the same |
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