CN108878420B - High voltage semiconductor device with single pulse avalanche energy and method for fabricating the same - Google Patents

High voltage semiconductor device with single pulse avalanche energy and method for fabricating the same Download PDF

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CN108878420B
CN108878420B CN201710339696.4A CN201710339696A CN108878420B CN 108878420 B CN108878420 B CN 108878420B CN 201710339696 A CN201710339696 A CN 201710339696A CN 108878420 B CN108878420 B CN 108878420B
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high voltage
gate
semiconductor device
width
contact hole
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CN108878420A (en
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曾婉雯
叶人豪
凃宜融
熊志文
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Leadtrend Technology Corp
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Leadtrend Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology

Abstract

The invention discloses a high-voltage semiconductor element and a manufacturing method thereof. The high voltage semiconductor device includes a main high voltage switch device and a current detection device. The main high-voltage switch element includes a plurality of switch units arranged in a first matrix. Each switch unit has a switch unit width. The current detection element comprises a plurality of detection units which are arranged in a second matrix. Each detection unit has a detection unit width larger than the switch unit width.

Description

High voltage semiconductor device with single pulse avalanche energy and method for fabricating the same
Technical Field
The present invention relates to a high voltage Metal-Oxide-semiconductor Transistor (MOSFET), and more particularly, to a high voltage MOSFET integrated with a current sensing device.
Background
A high voltage MOSFET is a semiconductor device, and generally refers to a MOSFET capable of withstanding a drain-to-source voltage (i.e., a voltage) exceeding 5V or more. In application, the switching circuit can be used for switching loads, or switching between different voltage potentials in power management, or used as a power element in a high-power amplifier.
High voltage MOSFETs often need to operate at high currents. Fig. 1A shows a conventional current detection architecture. The source terminal S of the high voltage MOSFET 10 is directly connected to a sense resistor RCS1 across which voltage V is appliedCSCan faithfully reflect the circulating current IDAnd providing the control signal to other circuits for corresponding control. However, in such a detection structure, the current I flowsDAll must flow through sense resistor RCS 1. For a considerable circulating current IDIn particular, the sense resistor RCS1 produces considerable energy loss.
Fig. 1B shows another conventional current detection architecture. The high voltage MOSFET12 incorporates a current sense high voltage MOSFET NCS and a main high voltage MOSFET NM. The detection terminal CS of the current detection high voltage MOSFET NCS is connected in series with the detection resistor RCS2, while the source terminal S of the main high voltage MOSFET NM is directly grounded. The current flowing through the current sensing high voltage MOSFET NCS is made approximately proportional to the current of the main high voltage MOSFET NM by using the principle of current mirror. Thus, the voltage across V of the resistor RCS2 is detectedCSApproximately reflecting the circulating current IDAnd most of the flowing current IDAnd does not flow through the sense resistor RCS2, the sense resistor RCS2 does not consume much power.
Fig. 1A and 1B also imply that both high voltage MOSFETs 10 and 12 may have to breakdown to release energy during normal operation. Taking high voltage MOSFET12 as an example, when high voltage MOSFET12 is switched from a conducting state (on) to a non-conducting state (off), the current of inductor LP will charge drain D of high voltage MOSFET12 and may generate a high voltage that exceeds the breakdown voltage of high voltage MOSFET 12. The power element has a specification called single-pulse avalanche Energy (EAS), which refers to the maximum energy that the power element can discharge in a single-pulse avalanche operation. Larger EAS generally means that the power element is stronger and more uniform for energy discharge.
Disclosure of Invention
The embodiment of the invention discloses a high-voltage semiconductor element which has good single-pulse avalanche energy. The high voltage semiconductor device includes a main high voltage switch device and a current detection device. The main high-voltage switch element includes a plurality of switch units arranged in a first matrix. Each switch unit has a switch unit width. The current detection element comprises a plurality of detection units which are arranged in a second matrix. Each detection unit has a detection unit width larger than the switch unit width.
The embodiment of the invention discloses a high-voltage semiconductor element which has good single-pulse avalanche energy. The high voltage semiconductor device includes a main high voltage switch device and a current detection device. The main high-voltage switch element includes a plurality of switch units arranged in a first matrix. Each switch unit has a first contact hole ratio. The current detection element comprises a plurality of detection units which are arranged in a second matrix. Each of the detecting units has a second contact hole ratio larger than the first contact hole ratio.
The embodiment of the invention discloses a manufacturing method which is suitable for manufacturing a high-voltage semiconductor element on a semiconductor substrate. The manufacturing method comprises the following steps: forming a patterned gate conductive layer on the semiconductor substrate; performing a doping process on the semiconductor substrate to form a body region and a source region on the semiconductor substrate, wherein the body region and the source region are defined by a same mask, and the mask comprises the gate conductive layer; forming an inter-polysilicon dielectric layer on the gate conductive layer; removing part of the inter-polysilicon dielectric layer to form a contact hole; and forming a metal layer in the contact hole; wherein the step of removing a portion of the interpoly dielectric layer also removes a portion of the source region, and thus the metal layer may simultaneously contact the body region and the source region.
The embodiment of the invention discloses a high-voltage semiconductor element which is formed on a semiconductor substrate and comprises a gate conducting layer, an integral area and a source area. The gate conductive layer is used as a gate of the high voltage semiconductor device. The body region and the source region are respectively used as a body electrode and a source electrode of the high-voltage semiconductor element. The semiconductor substrate is used as a drain of the high-voltage semiconductor element, and the body region and the source region are defined by the same mask and formed through a doping manufacturing process.
Drawings
FIGS. 1A and 1B are schematic diagrams illustrating two conventional current detection architectures;
FIG. 2 shows a top view of the high voltage MOSFET12 of FIG. 1B;
FIG. 3 illustrates a top view of region 20 of FIG. 2;
FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2;
FIG. 5 illustrates another possible top view of the area 20 of FIG. 2;
FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5;
FIG. 7 shows an equivalent circuit diagram of the parasitic element of FIG. 6 when subjected to EAS testing;
FIG. 8 illustrates another possible top view of the area 20 of FIG. 2;
FIG. 9 illustrates another possible top view of the area 20 of FIG. 2;
FIG. 10 illustrates another possible top view of the area 20 of FIG. 2;
FIG. 11 illustrates another possible top view of the area 20 of FIG. 2;
FIG. 12 illustrates another possible top view of the area 20 of FIG. 2;
fig. 13 shows a schematic diagram of a method 60 of fabricating the high voltage MOSFET12 of fig. 1B;
fig. 14-1-14-6 are schematic diagrams of a high voltage MOSFET12, cross-sectional views at various stages of a manufacturing process 60;
fig. 15 shows a schematic diagram of a method 90 of fabricating the high voltage MOSFET12 of fig. 1B, in accordance with the present invention;
fig. 16-1 through 16-4 are cross-sectional views of the high voltage MOSFET12 at various stages of the manufacturing process 90.
Description of the symbols
10 high voltage MOSFET
12 high voltage MOSFET
14 source electrode
16 detection pole
18 grid
20 area
22 field oxide layer
24 current sense element region
26 high voltage switching element region
32 back side metal layer
34N type substrate
36N type epitaxial layer
38P type body region
40. 40' N + source region
42 gate oxide layer
44 grid conductive layer
45 interpoly dielectric layer
46 metal layer
48. 481, 48' contact hole
50 vertical grid line
52 horizontal grid line
60. 90 manufacturing method
62. 64, 66, 68, 70, 72, 74, 76, 78, 80, 92, 94 steps
BJCS、BJMAINBipolar junction transistor
CCS1、CCS2、CCS11、CCS12、CCS21、CCS22、CCS31、CCS32Detection unit
CM1、CM2、CM11、CM12、CM21、CM22、CM31、CM32Switch unit
CONWD-CS1、CONWD-MAINWidth of contact hole
CS detection terminal
D drain terminal
G-gate terminal
GWTHMAIN、GWTHCSWidth of grid line
IDCirculating current
LP inductor
NCS current detection high-voltage MOSFET
NM main high voltage MOSFET
PTCHCS、PTCHCS1、PTCHCS2、PTCHCS3Width of detection unit
PTCHMAINWidth of switch unit
RCS1 detection resistor
RCS2 detection resistor
RCS、RMAINParasitic resistance
S source end
VCSOver pressure
IV-IV, VI-VI line
Detailed Description
In the present specification, the same reference signs are used to indicate the same or similar components having the same or similar structures, functions, and principles, and are inferred by those skilled in the art based on the teachings of the present specification. For the sake of brevity of the description, elements having the same reference numerals will not be repeated.
Fig. 2 shows a top view of the high voltage MOSFET12 of fig. 1B, which is formed on a semiconductor chip. On one front side of the semiconductor chip, there are a gate 18, a source 14 and a sense electrode 16, which can be used as the gate terminal G, the source terminal S and the sense terminal CS of the high voltage MOSFET12, respectively. A back side (not shown) of the semiconductor die has a drain that serves as the drain terminal D of the high voltage MOSFET 12.
Fig. 3 illustrates a top view of region 20 of fig. 2. Fig. 4 is a sectional view taken along line IV-IV in fig. 2.
Fig. 3 shows primarily the pattern of the gate conductive layer 44 and the field oxide layer 22. In fig. 3, a current detection element region 24 is surrounded by a field oxide layer 22 for forming a current detection high voltage MOSFET NCS; outside the current sensing device region 24 and the field oxide layer 22 is a high voltage switching device region 26 for forming a main high voltage MOSFET NM. The current sensing high voltage MOSFETs NCS can be regarded as a structure formed by a plurality of identical sensing units arranged in a matrix, like the sensing unit CCS1And CCS2As exemplified. Similarly, the main high voltage MOSFET NM can be considered as being formed by several identical switch units arranged in another matrix, like the switch unit CM1And CM2As exemplified. Each detection unit has a switching unit width PTCHMAINEach detection unit has a detection unit width PTCHCS. In fig. 3, each detection cell is the same as each switching cell, so the switching cell width PTCHMAINEqual to the detection cell width PTCHCS. The gate width (gate width) of the gate conductive layer 44 is the same in either the high-voltage switching element region 26 or the current detection element region 24. In short, the high-voltage switching element region 26 and the current detection element region 24 share the same unit.
In fig. 4, a back metal layer 32, an N-type substrate 34, an N-type epitaxial layer 36, a P-type body region 38, an N + source region 40, a gate oxide layer 42, a gate conductive layer 44, an interpoly dielectric layer 45, a metal layer 46, and a field oxide layer 22 are shown. A gate oxide layer 42 and a gate conductive layer 44 are stacked to form a gate structure. Also shown in fig. 4 are contact holes 48 formed by removing portions of the interpoly dielectric layer 45. In the high voltage switching element region 26, a metal layer 46 contacts the N + source region 40 and the P-type body region 38 through contact holes 48 as the source terminal S of the high voltage MOSFET 12. In the current sensing element region 24, the metal layer 46 contacts the N + source region 40 and the P-body region 38 through the contact hole 48 as the sensing terminal CS of the high voltage MOSFET 12. The back side metal layer 32 may serve as the drain terminal D of the high voltage MOSFET 12. All of the gate conductive layers 44 are shorted together and may serve as the gate terminal G of the high voltage MOSFET 12.
It is experimentally known that when the high voltage MOSFET12 is implemented with the structure shown in fig. 3 and 4, and the area of the current detection device region 24 and the device structure are not changed, the EAS of the high voltage MOSFET12 does not increase with the increase of the area of the current detection device region 24. It is surmised that the current sensing element region 24 should be relatively weak, causing most of the EAS to flow through the current sensing element region 24 and burn it out, so the EAS of the high voltage MOSFET12 cannot be made robust and profitable from the increased area of the current sensing element region 24.
In an embodiment of the invention, the width of the switching unit of each switching unit is smaller than the width of the detection unit of each detection unit. Each switch unit has a first contact hole ratio, which is the ratio of the contact hole area of a single switch unit to the area of the single switch unit. Each of the detecting units has a second contact hole ratio, which is the ratio of the contact hole area of a single detecting unit to the area of the single detecting unit. In another embodiment, the second contact hole ratio is greater than the first contact hole ratio.
In the embodiment of the invention, the detection unit is not easy to break down due to the difference of the width of the unit or the difference of the proportion of the contact holes. Therefore, the EAS may be deactivated by the switching unit. As the number of switching units increases, EAS may correspondingly increase because energy may be discharged through a larger area. In other words, embodiments of the present invention may have good EAS.
Fig. 5 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. Fig. 6 is a cross-sectional view taken along line VI-VI in fig. 5.
Fig. 5 shows primarily the pattern of the gate conductive layer 44 and the field oxide layer 22. In fig. 5, the current detection element region 24 is used to form the current detection high voltage MOSFET NCS in fig. 1B; high pressure switchThe off-device region 26 is used to form the main high voltage MOSFET NM in fig. 1B. The current sense high voltage MOSFET NCS can be viewed as being formed by a plurality of identical sense cells arranged in a matrix, like the sense cell CCS11And CCS12As exemplified. Similarly, the main high voltage MOSFET NM can be considered as being formed by several identical switch units arranged in another matrix, like the switch unit CM11And CM12As exemplified. Each detection unit has a switching unit width PTCHMAINEach detection unit has a detection unit width PTCHCS1. In fig. 5, a single detection unit is not identical to a single switching unit. In contrast to fig. 3, the current detecting element region 24 in fig. 5 is substantially the same as the current detecting element region 24 in fig. 3, but one is removed for every two gate lines. Thus, as shown in FIG. 5, the detection cell width PTCHCS1About the width PTCH of the switch unitMAINTwice as much. In other embodiments of the present invention, the width of the detection unit is larger than that of the switch unit, which may be an integer multiple or a non-integer multiple.
In FIG. 6, a plurality of contact holes 48 and 481 are also shown, which are formed by removing portions of the interpoly dielectric layer 45. In the high voltage switching element region 26, a metal layer 46 contacts the N + source region 40 and the P-type body region 38 through contact holes 48 as the source terminal S of the high voltage MOSFET 12. In the current detecting element region 24, the metal layer 46 contacts the N + source region 40 and the P-type body region 38 through the contact hole 481 as the detecting terminal CS of the high voltage MOSFET 12. Contact hole width CON of contact hole 481WD-CS1Contact hole width CON greater than contact hole 48WD-MAIN. The back side metal layer 32 may serve as the drain terminal D of the high voltage MOSFET 12. In FIG. 6, the detection cell width PTCHCS1Is the switching cell width PTCHMAINTwice as much. The gate width (gate width) of the gate conductive layer 44 is the same in either the high-voltage switching element region 26 or the current detection element region 24. The thickness of the interpoly dielectric layer 45 left on the sidewalls of the gate conductive layer 44 is also more or less the same. The contact hole ratio of the high voltage switch element region 26, defined as the ratio of the contact hole area of a single switch unit to the area of the single switch unit, is approximately equal to the contact hole width CONWD-MAINDivided by the switching cell width PTCHMAIN. The contact hole ratio of the current sensing element region 24, which is the ratio of the contact hole area of a single sensing cell to the single sensing cell area, is approximately equal to the contact hole width CONWD-CS1Divided by the detection cell width PTCHCS1. Therefore, in fig. 6, the contact hole ratio of the high-voltage switching element region 26 is smaller than that of the current detection element region 24.
Some parasitic elements are also shown in fig. 6. NPN Bipolar Junction Transistor (BJT) BJMAINIn the high voltage switching element region 26, N + source region 40, P-type body region 38 and N-type epitaxial layer 36 constitute. Similarly, NPN BJT BJCSIs composed of N + source region 40, P-type body region 38 and N-type epitaxial layer 36 in current sensing element region 24. Parasitic resistance RMAINAnd RCSRespectively represent BJT BJMAINAnd BJCSTo the base electrode of the metal layer 46.
Fig. 7 shows an equivalent circuit diagram of the parasitic element of fig. 6 when subjected to EAS testing. The current IEAS of EAS enters from the drain D or the back metal layer 32. Then flows through BJT BJMAINAnd BJCSOne of which is turned on and released to the ground line. Parasitic resistance RMAINAnd RCSThe larger, the more likely to cause BJT BJMAINAnd BJCSIs raised and turned on.
The high voltage switching element region 26 of FIGS. 6 and 4 has the same contact hole width CONWD-MAIN. However, in contrast, the contact hole width CON of the current detecting element region 24 of FIG. 6WD-CS1Larger than the contact hole width (not labeled) of the current sensing element region 24 of fig. 4. Therefore, the parasitic resistance R in fig. 6 can be knownCSWill be less than the corresponding parasitic resistance of fig. 4. In other words, the current detection device region 24 of fig. 6 will be relatively non-conductive under the EAS test, and the current IEAS is likely to pass through the BJT of the large-area high-voltage switching device region 26BJMAINAnd (4) releasing.
It has also been experimentally proven that changing the top view of the high voltage MOSFET12 from fig. 3 to fig. 5 can positively increase the EAS of the high voltage MOSFET 12.
Fig. 8 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. Fig. 8 is similar to fig. 5 and 3 and primarily shows the pattern of the gate conductive layer 44 and the field oxide layer 22. In FIG. 8, the current detecting element region 24 has a plurality of identical detecting units arranged in a matrix as the detecting unit CCS21And CCS22As exemplified. Similarly, the high voltage switch element region 26 has a plurality of identical switch units arranged in another matrix as the switch unit CM21And CM22As exemplified. Each detection unit has a switching unit width PTCHMAINEach detection unit has a detection unit width PTCHCS2. In comparison with fig. 3, the current detecting element region 24 in fig. 8 is the same as the current detecting element region 24 in fig. 3, but only one is left for every three gate lines, and the other two are deleted. Thus, as shown in FIG. 8, the detection cell width PTCHCS2About the width PTCH of the switch unitMAINThree times that of the original.
In fig. 8, the gate width of the gate conductive layer 44 is the same in either the high-voltage switching element region 26 or the current detection element region 24. The contact hole ratio of the high voltage switching element region 26 is approximately equal to the gate gap (distance between two gate lines) of the switching cell versus the switching cell width PTCHMAINThe ratio of (a) to (b). Similarly, the contact hole ratio of the current sensing element region 24 is approximately equal to the gate gap of the sensing cell to the sensing cell width PTCHCS2The ratio of (a) to (b). It is apparent that the contact hole ratio of the high voltage switching element region 26 in fig. 8 is smaller than that of the current detecting element region 24.
In fig. 5 and 8, the switching unit in the high voltage switching element region 26 has a similar or identical unit structure to the detecting unit in the current detecting element region 24. For example, the switch units and the detection units in fig. 5 and 8 are rectangular in shape, and the gate lines formed by the gate conductive layers 44 in the switch units and the detection units only extend along the upper and lower directions. However, the present invention is not limited thereto, and in other embodiments, the switch unit and the detection unit do not need to have the same or similar unit structures.
Fig. 9 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. In FIG. 9, the current detecting element region 24 has a plurality of identical detecting units arranged in a matrix like the detecting unit CCS31And CCS32As exemplified. Similarly, the high voltage switch element region 26 has a plurality of identical switch units arranged in another matrix as the switch unit CM31And CM32As exemplified. Detecting cell width PTCHCS3About the width PTCH of the switch unitMAINTwice as much. In fig. 9, the contact hole ratio of the switch unit is approximately equal to the area ratio of the entire single switch unit except the gate conductive layer 44 in the single switch unit; the contact hole ratio of the sensing unit is approximately equal to the area ratio of the whole single sensing unit except the gate conductive layer 44 in the single sensing unit. As can be understood from fig. 9, the contact hole ratio of the switching unit is smaller than that of the sensing unit.
In fig. 9, the switch unit and the detection unit are rectangular in shape. The grid lines of the switch units only extend along the upper and lower parts, but the grid lines of the detection units not only extend along the upper and lower parts, but also extend along the left and right parts. In fig. 9, the gate pattern (constituted by the gate conductive layer 44) of the high-voltage switching element region 26 (serving as the main high-voltage MOSFET NM) is clearly different from the gate pattern of the current detection element region 24 (serving as the current detection high-voltage MOSFET NCS). In fig. 9, the gate pattern of the current detection element region 24 is electrically connected to the gate pattern of the high-voltage switching element region 26 not only through the vertical gate lines 50 but also through the horizontal gate lines 52. The gate pattern of the current sensing element region 24 is connected to the gate pattern of the voltage switching element region 26 through two directions, one is a horizontal direction and the other is a vertical direction.
Fig. 10 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. The difference between fig. 10 and fig. 9 lies in the number and arrangement of the detection cells in the current detection element region 24. In fig. 9, 6 detection cells are arranged in a matrix of 2 × 3. In fig. 10, 5 detection cells are arranged in an H-shaped matrix.
Fig. 11 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. In fig. 11, the switching cells in the high-voltage switching element region 26 are rectangular in shape, and the detection cells in the current detection element region 24 are regular hexagonal (Hexagon) in shape. In fig. 11, the contact hole ratio of the switching cell is smaller than that of the sensing cell.
Fig. 12 illustrates another possible top view of region 20 of fig. 2, according to an embodiment of the present invention. In fig. 12, the switching cells in the high-voltage switching element region 26, and the sensing cells in the current sensing element region 24 are all regular hexagonal in shape. The switching cells in fig. 12 have the same gate line width as the sensing cells, but the switching cells have smaller side lengths. Therefore, in fig. 12, the contact hole ratio of the switching cell is smaller than that of the sensing cell.
Fig. 13 illustrates a method 60 for fabricating the high voltage MOSFET12 of fig. 1B on a semiconductor substrate, resulting in the cross-sectional view of fig. 4 or fig. 6. Fig. 14-1-14-6 are cross-sectional views of the high voltage MOSFET12 at various stages of the manufacturing process 60.
The fabrication method 60 begins with step 62 by providing an N-type substrate 34.
Step 64 continues with step 62 by epitaxially forming an N-type epitaxial layer 36 on the N-type substrate 34, as shown in fig. 14-1.
Step 66 forms a patterned field oxide layer 22 on the N-type epitaxial layer 36 as shown in fig. 14-2. Step 66 utilizes a photolithography process to define isolation regions where the field oxide layer 22 is located and active regions for later formation of active devices such as transistors with a photomask (referred to as a FOX photomask). Step 66 also generally defines the high voltage switching element region 26 and the current sensing element region 24 because of the formation of the field oxide layer 22.
Step 68 sequentially forms gate oxide 42 and gate conductive layer 44 stacked on N-epi layer 36 and field oxide 22. The gate conductive layer 44 may comprise a polysilicon layer.
Step 70 patterns the gate oxide layer 42 and the gate conductive layer 44, as well asAs shown in fig. 14-3. Step 70 utilizes a photolithography process to define the regions of the GATE conductive layer 44 to be preserved with a photomask (referred to as GATE photomask in the specification), and an etching process is used to remove the GATE conductive layer 44 and the GATE oxide layer 42 in the regions not to be preserved. The remaining gate conductive layer 44 can be used as a gate electrode or a gate line. In one embodiment, the gate line width GWTH in the high voltage switching device region 26 and the current sensing device region 24MAINAnd GWTHCSAs such.
Step 72 is performed by performing a doping process using the gate conductive layer 44 and the field oxide layer 22 as a mask to form P-type body regions 38 in the N-type epitaxial layer 36. Step 72 does not use a photomask. For example, an ion implantation process may be performed followed by a diffusion process to diffuse the P-type body regions 38 under a portion of the conductive layer 44.
Following step 72, step 74 forms N + source regions 40 on N-type epitaxial layer 36 using a photo mask (referred to herein as an N + photo mask) through a photolithography and doping process, as shown in fig. 14-4. N + source regions 40 are formed substantially on N-type epitaxial layer 36 on both sides of conductive layer 44 by an ion implantation process. In fig. 14-4, two N + source regions 40 are formed between each pair of GATE conductive layers 44, spaced apart from each other by a GATE photomask, with a portion of the P-type body region 38 being exposed between the two N + source regions 40.
In step 76, an interpoly dielectric layer 45, which may be silicon dioxide, is formed on the gate conductive layer 44 and the N-type epitaxial layer 36 by a deposition process.
Step 78 uses a photomask (referred to as a CON photomask in this specification) to remove portions of the interpoly dielectric layer 45 by photolithography and etching processes to form contact holes 48, as shown in fig. 14-5. The bottom of contact hole 48 is formed by N + source region 40 and P-type body region 38, and the sidewall of contact hole 48 is formed by interpoly dielectric layer 45.
Step 80 forms a metal layer 46 in the interpoly dielectric layer 45 and the contact hole 48 by a deposition process. Metal layer 46 forms an ohmic contact with N + source region 40 and P-type body region 38.
Step 82 uses a photomask (referred to in the specification as an MTL photomask) to remove portions of metal layer 46 by a photolithography and etch process, as shown in fig. 14-6.
Following step 82, a backside metal layer 32 may be formed on the backside of the N-type substrate 34 to obtain the cross-sectional view of fig. 4 or fig. 6.
In the method 60 of FIG. 13, at least 5 photomasks are required, including FOX, GATE, N +, CON, and MTL photomasks.
Fig. 15 illustrates a method 90 for fabricating the high voltage MOSFET12 of fig. 1B on a semiconductor substrate, resulting in the cross-sectional views of fig. 16-4, in accordance with the present invention. Fig. 16-1-16-3 are cross-sectional views of the high voltage MOSFET12 at various stages of the manufacturing process 90. The method 90 of fig. 15 requires a smaller number of photomasks than the method 60 of fig. 13.
Steps 62, 64, 66, 68, 70, 72 of fig. 15 may be learned with reference to fig. 13 and the description thereof, and will not be described again.
In fig. 15, following step 72, step 92, a doping process is performed using the gate conductive layer 44 and the field oxide layer 22 as a mask to form N + source regions 40' in the N-type epitaxial layer 36, as shown in fig. 16-1. Step 92 does not use a photomask, which is the same mask used in step 72. Therefore, the location of the N + source regions 40' is approximately the same as the location of the P-type body regions 38. In a diffusion process, the P-type body region 38 diffuses farther than the N + source region 40 ', so that the P-type body region 38 surrounds the N + source region 40' substantially completely on the bottom and sides, as shown in fig. 16-1. And in fig. 16-1, there is only one N + source region 40' between every two gate conductive layers 44.
In fig. 15, step 76 continues with step 92. Step 76 can be understood with reference to fig. 13 and the related description, and will not be described in detail.
Step 94 continues with step 76 in which a CON photomask is used to remove portions of the interpoly dielectric layer 45 and the N + source region 40 'by a photolithography and etch process to form contact holes 48', as shown in fig. 16-2. The bottom of contact hole 48 ' is formed only by P-type body region 38, while the sidewalls of contact hole 48 ' are formed by N + source region 40 ' and interpoly dielectric layer 45.
Step 80 is performed by a deposition process to form a metal layer 46 in the interpoly dielectric layer 45 and the contact hole 48'. Metal layer 46 forms an ohmic contact with N + source region 40' and P-type body region 38.
Step 82 removes portions of the metal layer 46 by a photolithography and etch process using an MTL photomask, as shown in fig. 16-3.
Following step 82, a backside metal layer 32 may be formed on the backside of the N-type substrate 34 to obtain the cross-sectional view of FIGS. 16-4.
The method 90 of FIG. 15 requires at least 4 photomasks, including FOX, GATE, CON, and MTL photomasks, but does not require the N + photomask used in step 74 of the method 90 of FIG. 13. In contrast, the manufacturing method 90 of fig. 15 requires fewer photomasks, and thus the manufacturing process cost may be lower.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (18)

1. A high voltage semiconductor device with good single-pulse avalanche energy, comprising:
the main high-voltage switch element comprises:
a plurality of switch cells (switch cells) arranged in a first matrix, wherein each switch cell has a switch cell width; and
the current detection element includes:
several detecting units (sense cells) are arranged in a second matrix, wherein each detecting unit has a detecting unit width (sense cell width) larger than the switch unit width.
2. The high voltage semiconductor device as claimed in claim 1, wherein the width of the detecting unit is an integer multiple of the width of the switching unit.
3. The high voltage semiconductor device as claimed in claim 1, wherein each of the switching units has a first gate width, and each of the sensing units has a second gate width equal to the first gate width.
4. The high voltage semiconductor device as claimed in claim 1, wherein the high voltage semiconductor device comprises a semiconductor substrate (substrate); the main high-voltage switch element and the current detection element share a drain electrode and are formed on the back surface of the semiconductor substrate; the main high-voltage switch element and the current detection element share a grid electrode and are formed on a front surface of the semiconductor substrate, and the main high-voltage switch element and the current detection element are respectively provided with a source electrode and a detection electrode which are formed on the front surface.
5. The high voltage semiconductor device as claimed in claim 1, wherein each of the switch units comprises a first contact hole width, and each of the sensing units comprises a second contact hole width greater than the first contact hole width.
6. A high voltage semiconductor device with good single-pulse avalanche energy, comprising:
the main high-voltage switch element comprises:
a plurality of switch units arranged in a first matrix, wherein each switch unit has a first contact ratio (contact ratio); and
the current detection element includes:
the detecting units are arranged into a second matrix, wherein each detecting unit is provided with a second contact hole proportion which is larger than the first contact hole proportion.
7. The high-voltage semiconductor device as claimed in claim 6, wherein each of the switching units and each of the detecting units are identical in shape (shape).
8. The high voltage semiconductor device as claimed in claim 6, wherein each of the switching units and each of the detecting units are different in external form.
9. The high voltage semiconductor device as claimed in claim 6, wherein the main high voltage switching device and the current detecting device have a first gate pattern and a second gate pattern, respectively, the second gate pattern is connected to the first gate pattern through two connecting directions, and the two connecting directions are not parallel to each other.
10. The high voltage semiconductor device as claimed in claim 6, wherein each of the inspection units has an outer shape, which is rectangular or regular hexagonal.
11. A method for manufacturing a high voltage semiconductor device on a semiconductor substrate, comprising:
forming a patterned gate conductive layer on the semiconductor substrate;
performing a doping process on the semiconductor substrate to form a body region and a source region on the semiconductor substrate, wherein the body region and the source region are defined by a same mask, and the mask comprises the gate conductive layer;
forming an inter-polysilicon dielectric layer on the gate conductive layer;
removing part of the inter-polysilicon dielectric layer to form a contact hole; and
forming a metal layer in the contact hole;
wherein the step of removing a portion of the interpoly dielectric layer also removes a portion of the source region, and thus the metal layer may simultaneously contact the body region and the source region.
12. The method of claim 11, comprising:
forming a field oxide layer; and
and performing the doping process by using the field oxide layer and the gate conductive layer as the mask.
13. The method of claim 11, comprising:
extending to form an epitaxial layer on the semiconductor substrate;
forming a patterned field oxide layer on the epitaxial layer; and
the gate conductive layer is formed on the epitaxial layer.
14. The method of claim 11, wherein the step of forming the gate conductive layer comprises:
sequentially forming a gate oxide layer and the gate conductive layer; and
and patterning the gate oxide layer and the gate conductive layer.
15. The method of claim 11, wherein said contact hole has a bottom comprised only of said body region.
16. A high voltage semiconductor device formed on a semiconductor substrate, comprising:
a gate conductive layer as a gate of the high voltage semiconductor device; and
a body region and a source region, which are respectively used as a body electrode and a source electrode of the high-voltage semiconductor element;
the semiconductor substrate is used as a drain electrode of the high-voltage semiconductor element, and the body region and the source region are defined by the same mask and formed by a doping manufacturing process;
an inter-polysilicon dielectric layer; and
contact holes are formed to remove the inter-poly dielectric layer and a portion of the source region.
17. The high voltage semiconductor device as claimed in claim 16, further comprising:
a field oxide layer on the semiconductor substrate;
the doping process for forming the body region and the source region uses the field oxide layer and the gate conductive layer as the mask.
18. The device of claim 16, wherein the contact hole has a bottom portion formed only by the body region.
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Citations (4)

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Publication number Priority date Publication date Assignee Title
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US5753529A (en) * 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
CN1366332A (en) * 2001-01-17 2002-08-28 世界先进积体电路股份有限公司 Process for preparing dual-layer grid of MOS element
US6870201B1 (en) * 1997-11-03 2005-03-22 Infineon Technologies Ag High voltage resistant edge structure for semiconductor components

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US5753529A (en) * 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
US6870201B1 (en) * 1997-11-03 2005-03-22 Infineon Technologies Ag High voltage resistant edge structure for semiconductor components
CN1366332A (en) * 2001-01-17 2002-08-28 世界先进积体电路股份有限公司 Process for preparing dual-layer grid of MOS element

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