CN2692841Y - Multiplex grid structure - Google Patents

Multiplex grid structure Download PDF

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Publication number
CN2692841Y
CN2692841Y CN 200420049601 CN200420049601U CN2692841Y CN 2692841 Y CN2692841 Y CN 2692841Y CN 200420049601 CN200420049601 CN 200420049601 CN 200420049601 U CN200420049601 U CN 200420049601U CN 2692841 Y CN2692841 Y CN 2692841Y
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gate
layer
multi
gate structure
structure according
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CN 200420049601
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Chinese (zh)
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陈豪育
杨育佳
杨富量
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台湾积体电路制造股份有限公司
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Abstract

The utility model relates to a multiplex grid structure, comprising multiple fin semiconductor layers which are arranged in parallel along the first direction and are supported by multiple insulated platforms on an insulation layer. Wherein, the bottom face of the fin semiconductor layer is larger than the contact face through which the fin semiconductor layer contacts with the insulated platform. The utility model also comprises a grid conductive coating which extends along the second direction and is covered on parts of the surface of the fin semiconductor layers. A grid dielectric layer is provided between the grid conductive coating and the fin semiconductor layers covered by the grid conductive coating. Wherein, the grid dielectric layer is covered on the bottom face of the fin semiconductor layer within the surface parts covered by the grid conductive coating.

Description

多重栅极结构 Multi-gate structure

技术领域 FIELD

本实用新型是有关于一种半导体组件,且特别有关于一种高性能的多重栅极结构,特别适合应用在深次微米以下的CMOS组件。 The present invention relates to a semiconductor device, and more particularly relates to a high performance multi-gate structure, particularly suitable for applications in deep sub-micron CMOS components below.

背景技术 Background technique

金属氧化半导体场效应晶体管(Metal-Oxide-Semiconductor FieldEffect Transistors,以下简称MOSFET)是在集成电路技术技术中相当重要的一种基本电子组件,其由三种基本的材料,即金属导体层、氧化层与半导体层等组成位于半导体基底上的栅极晶体管。 A metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor FieldEffect Transistors, hereinafter referred to as MOSFET) is a very important basic electronic components in the integrated circuit art technology, consisting of three basic materials, i.e. metal conductor layer, the oxide layer the semiconductor layer is composed of a gate transistors on a semiconductor substrate. 此外,还包括了两个位于栅极晶体管两旁,且电性与半导体基底相反的半导体区,称为源极与漏极。 Also included are the two semiconductor regions located on both sides of the gate of the transistor, and the semiconductor substrate oppositely charged, it called the source and drain. 目前制作栅极晶体管时,金属导电层多由经掺杂的复晶硅(Polysilicon)与金属共同组成,此结构又称为复晶硅化金属(Polycide)。 At present the production of the gate of the transistor, a multi-layer metal conductive doped polycrystalline silicon (Polysilicon) composed of metal, this configuration is also known as polycrystalline silicide (Polycide). 氧化层多由热氧化法所形成的氧化硅作为闸氧化层。 Multi oxide layer of silicon oxide formed by thermal oxidation layer as the gate oxide. 此外,在栅极的侧壁多以氮化硅作为间隔物(spacer)。 Further, the plurality of sidewalls of the gate silicon nitride as a spacer (spacer).

虽然上述传统的MOSFET长久以来已被广泛的使用,然而随着半导体技术对积集度要求的提高,传统的MOSFET尺寸及其沟道长度(channellength)亦相对地缩减。 Although the above-described conventional MOSFET since long has been widely used, however, with the improvement of the semiconductor technology product set of requirements, the size of the conventional MOSFET and a channel length (channellength) is also relatively reduced. 当MOSFET组件的沟道长度缩减至低于100nm时,于传统位于半导体硅基底上的MOSFET作用时,便容易由于源极与漏极与其间的沟道相互作用,进而影响了栅极对于其沟道的开启/关闭状态的控制能力,而进一步引起的所谓的短沟道效应(short channel effects;SCE)。 When the channel length of the MOSFET device is reduced to less than 100 nm or, when positioned in a conventional MOSFET on a semiconductor silicon substrate acting, it is easy since the source and drain and channel interaction therebetween, thereby affecting the gate trench for which channel on / off control state, further causing a so-called short-channel effects (short channel effects; SCE).

因此,为了使MOSFET于CMOS组件上的应用可以配合MOSFET尺寸缩小化的发展与提高MOSFET积集度的需求,实有必要针对MOSFET于组件缩小化过程中对于其闸沟道开启/关闭状态的控制能力谋求改善之道。 Accordingly, in order to make the application on the CMOS MOSFET components may be blended MOSFET size reduction of the product development and increase demand set degrees MOSFET, it is necessary for the MOSFET to a real reduction assembly process of the channel ON / OFF state of the brake control for which seek to improve the capacity of the road.

发明内容 SUMMARY

有鉴于此,本实用新型的主要目的就是提供一种多重栅极结构,适合应用于闸沟道长度低于100nm的深次微米以下的CMOS组件上。 In view of this, the main object of the present invention is to provide a multi-gate structure, suitable for a channel length below the gate on a CMOS microns deep sub-components of 100nm. 利用本实用新型的多重栅极结构以增加对于闸沟道的控制并抑制短沟道效应的产生。 Multiple use invention of the present configuration to increase the control gate for the gate and the channel short channel effect is suppressed. 除此之外,本实用新型的多重栅极结构可提供足够的驱动电流,有助于MOSFET作用原理于半导体组件上的继续应用,而不受到组件尺寸缩减的影响。 In addition, the present invention multi-gate structure may provide sufficient drive current, to facilitate the continued application of the principles of MOSFET acting on the semiconductor element, without being affected by the reduced component size.

为达上述目的,本实用新型提供了一种多重栅极结构,包括:多个鳍型半导体层,沿一第一方向大体平行地排列,且由多个位于一绝缘层上的绝缘台地所支撑,其中上述鳍型半导体层的底面大于与其与绝缘台地的接触面;以及一栅极导电层,沿一第二方向延伸且覆盖于上述鳍型半导体层的部分表面上,且于栅极导电层与其所覆盖的上述鳍型半导体层之间更设置有一栅极介电层,其中此栅极介电层更包覆于该栅极导电层所覆盖部分表面内的此等鳍型半导体层的底面。 To achieve the above object, the present invention provides a multi-gate structure, comprising: a plurality of fin-type semiconductor layer are arranged along a first direction substantially parallel to, and positioned by a plurality of insulation on a platform supported by the insulating layer wherein the bottom surface of the fin-type semiconductor layer is larger than its contact surface with the insulating platform; and a gate conductive layer, and extends to cover the upper surface of the fin-type semiconductor layer portion along a second direction, and a gate conductive layer more provided between the fin-type semiconductor layer and it covers a gate dielectric layer, wherein the gate dielectric layer is further coated on the gate conductive layer such fin-type semiconductor layer in a bottom portion of the surface covered . 其中上述绝缘层是位于一半导体基底上,且上述的第一方向是大体正交于第二方向,而上述的鳍型半导体层具有圆滑化的上部边角,以避免尖端放电现象。 Wherein said insulating layer is located on a semiconductor substrate, and said first direction is substantially orthogonal to the second direction, and said fin-type semiconductor layer having an upper rounded corners of the, in order to avoid point discharge.

此外,上述多重栅极更包括多个源极/漏极区,位于此多重栅极两侧未为该栅极导电层所覆盖的该等鳍型半导体层内,以构成一具有多重栅极(multiple-gate)的多重栅极晶体管(multiple-gate transistor)。 Further, the multi-gate further includes a plurality of source / drain region, this is located within the multiple sides of the gate such that the fin is not type semiconductor layer covered by the gate conductive layer to form a gate electrode having multiple ( multiple-gate) of the multi-gate transistor (multiple-gate transistor). 而此多重栅极晶体管(multiple-gate transistor)内更包括多个淡掺杂源极/漏极区连接于上述的源极/漏极区,其中此等淡掺杂源极/漏极区是位于源极/漏极区间的鳍型半导体层内。 And within this multiple gate transistors (multiple-gate transistor) further comprises a plurality of lightly doped source / drain region connected to the source / drain regions, wherein these lightly doped source / drain regions source located within the fin-type semiconductor layer, source / drain section.

本实用新型的多重栅极结构,是形成于多个位于绝缘台地上的半导体层内,具有可同时开启或关闭的多个平行于第一方向的闸沟道(gatechannel),且借由栅极介电层与栅极导电层沿第二方向延伸且覆盖于此等闸沟道所在的半导体层的两对应面及上表面外,更覆盖于其未接触绝缘台地的底面,对于此等闸沟道的控制可较习知的栅极结构为佳,而上述的第一方向与第二方向间具有一大体正交的连接关系。 The present invention multi-gate structure, the semiconductor layer is formed on the insulating plurality of ground stations, having a plurality of parallel or may be turned off simultaneously in a first direction, the channel gate (gatechannel), and by means of gate the dielectric layer and the gate conductive layer extending in a second direction and covering the two surfaces of the semiconductor layer corresponding to the channel where the gate thereto and the like on the surface, the more insulation overlying the bottom surface does not contact the mesa for such gate trench the control channel may be more preferably conventional gate structure, and between said first and second directions substantially orthogonal having a connection relation.

此外,本实用新型的多重栅极结构可搭配高介电常数介电材料(high-k gate dielectric)的使用以及可应用于绝缘层上有硅(SOI)的半导体基底,有助于降低多重栅极晶体管所消耗的功率及相关有害的电气效应。 Further, the present invention can be used with multi-gate structure using a high k dielectric material (high-k gate dielectric) and silicon (SOI) semiconductor substrate on the insulating layer may be applied to help reduce the multiple-gate electrical power and associated deleterious effect transistor consumed.

本实用新型是利用增加晶体管上闸沟道的数量,并将此等闸沟道并联以形成一共构的多重栅极晶体管,此等多重栅极晶体管可同时开启更多的闸沟道,借此纾解电流的压力,以提供通过晶体管的较大电子流量,并改善驱动电流。 The present invention is the use of the increase in the number of gates of the transistor channel, and these gates to form a multiple channel parallel configuration of a total gate of the transistor, multiple gate transistors such more gates open simultaneously the channel, whereby current to relieve stress, to provide a larger flow of electrons through a transistor, and to improve the driving current. 而借由本实用新型的多重栅极晶体管可解决前述尺寸缩小所衍生的问题,并提升半导体组件的效能。 And by means of the present invention can solve the multiple gate transistors to reduce the problem derived from the size and improve the performance of the semiconductor component.

附图说明 BRIEF DESCRIPTION

图1A至图1I为一系列剖面图,用以说明本实用新型一较佳实施例中所制作多重栅极的结构及其制造方法。 1A to 1I are cross-sectional view for explaining the structure of the present invention and the manufacturing method described in a produced multi-gate preferred embodiment.

图2A至图2F为一系列俯视图,用以说明对应于剖面图1a至图1k中的相对俯视情形。 2A to 2F are a series of top plan view for illustrating the relative cross-sectional top view of the case corresponding to Figures 1a to 1k are.

符号说明:100~半导体基底102~绝缘层102a~绝缘台地 REFERENCE SIGNS: 100 ~ 102 ~ insulating layer of the semiconductor substrate 102a ~ insulating mesa

104、104a、104b~硅层106、106a~氧化层108、108a~罩幕层110~光阻层112~凹处114~介电层116~导电层114a~栅极介电层116a~栅极导电层118~光阻图案120~淡掺杂离子植入122~淡掺杂源极/漏极区124~间隔物126~离子植入128~源极/漏极区130~金属硅化物层HM~硬罩幕G~多重栅极具体实施方式本实用新型将配合剖面图1A至图1I作说明本实用新型的多重栅极结构的制作,并配合俯视图2A至图2F以辅助说明其俯视情形。 104,104a, 104b ~ ~ Si layer 106,106a oxide layers 108,108a ~ mask layer 110 to the photoresist layer 112 through the recesses 114 - 116 to the dielectric layer a conductive layer is a gate dielectric layer 114a ~ ~ gate 116a conductive layer 118 photoresist pattern 120 ~ ~ 122 ~ lightly doped ion implantation lightly doped source / drain regions 124 ~ 126 ~ ion implantation spacer metal silicide layer HM 128 ~ source / drain regions 130 ~ ~ G ~ multiple hard mask gate embodiment of the present invention with a sectional view of the FIG. 1A to 1I described for making the present invention multi-gate structure, and with a plan to FIGS. 2A to 2F plan view of assistance in explaining its case.

首先如图1A所示,其显示本实用新型的起始步骤,在该图中,首先提供一基底,例如为一绝缘层上有半导体层的半导体基底,其来源可为绝缘层上有硅(silicon on insulator;SOI)或绝缘层上有硅锗材料(SiGe)的半导体基底100。 First, as shown in FIG. 1A, which shows the initial step of the present invention, in the figure, a substrate is first provided, for example, an insulating layer on a semiconductor substrate a semiconductor layer, the source may have a silicon on insulator ( silicon on insulator; on SOI) or silicon germanium material insulating layer (SiGe) semiconductor substrate 100. 于此半导体基底100上具有一绝缘层102以及一半导体层104,而此绝缘层的材质例如为二氧化硅,其厚度介于10~10000埃,而半导体层104的材质可为硅或硅锗材料,其厚度介于5~5000埃,在此则以一半导体材料的硅层104表示,以说明本实用新型的实施例。 This semiconductor substrate 100 having an insulating layer on a semiconductor layer 102 and 104, the material of this insulating layer, for example silicon dioxide having a thickness between 10 and 10000, and the material of the semiconductor layer 104 may be silicon or silicon germanium material thickness of between 5 to 5000 angstroms, this places a silicon layer 104 of semiconductor material, said to illustrate embodiments of the present invention.

接着于此硅层104上依序形成一氧化层106以及一罩幕层108,形成此氧化层106的方法例如为热氧化法(thermal oxidation),其材质例如为二氧化硅(SiO2),而形成罩幕层108的方法例如为化学气相沉积法(CVD),其材质例如为氮化硅材料(Si3N4)。 Subsequently thereto are sequentially formed on the silicon oxide layer 104 a layer 106 and a mask layer 108, the method for forming the oxide layer 106, for example, thermal oxidation (thermal oxidation), which is made, for example, silicon dioxide (SiO2), and the method of forming the mask layer 108 is, for example, chemical vapor deposition (CVD), which is made, for example, a silicon nitride material (Si3N4). 接着涂布一光阻材料(PR)于上述罩幕层108上,并经由一微影及显影程序以形成多个图案化的光阻层110于罩幕层108上。 Then coating a photoresist (PR) on said mask layer 108, via photolithography and a developing process to form a plurality of the patterned photoresist layer 110 on the mask layer 108. 此时,图1A中剖面结构是对应于如俯视图2A中A~A'切线内的剖面情形,而此时的俯视情形则如图2A中所示,于绝缘层102上(未显示)为罩幕层108所覆盖且具有多个图案化的光阻层110于罩幕层108上,而此等图案化的光阻层110则沿图2A中平行于y轴的第一方向大体平行地排列。 At this time, in FIG. 1A is a cross-sectional configuration corresponding to the cross-section as in the case of 2A, A ~ A 'tangential plan view and a top view of the situation at this time is shown in FIG. 2A, on the insulating layer 102 (not shown) of the cover screen layer 108 having a cover and a plurality of patterned photoresist layer 110 arranged substantially parallel to the mask layer 108, and such a patterned photoresist layer 110 in FIG. 2A in the direction parallel to a first direction of the y-axis .

接着,请参照图1B,沿着上述图案化的光阻层110,分别蚀刻罩幕层108及氧化层106,以分别形成图案化的罩幕层108a及氧化层106a,以构成多个硬罩幕HM,并于去除光阻层110后,再以此图案化的硬罩幕HM作为蚀刻硬罩幕,接着于硅层104上定义出多个图案化硅层104a,并蚀刻停止于绝缘层102上。 Next, referring to Figure 1B, along the patterned photoresist layer 110, and a screen oxide layer 108 are etched cap layer 106, the patterned mask layer 108a and the oxidized layer 106a to form, respectively, to form a plurality of hard mask HM screen, and after removing the photoresist layer 110, and then as the hard mask HM is patterned as an etching hard mask, is then defined on the silicon layer over 104 patterned silicon layer 104a, the insulating layer and the etch stop 102 on. 此时,图1B中的剖面结构是对应于俯视图2B内A~A'切线中的剖面情形,其俯视结构如图2B中所示,于绝缘层102上显现出多个图案化的罩幕层108a及其间所露出的部分绝缘层102,其中,于此等图案化的罩幕层108a及其下方的氧化层106a与硅层104a亦沿先前光阻层110所定义方向,大体平行地于图2B中y轴的第一方向排列。 At this time, a cross-sectional structure of FIG. 1B is a cross-sectional view corresponding to the case of tangent A ~ A 'in FIG. 2B a top within which the planar structure shown in Figure 2B, showing a plurality of patterned mask layer on the insulating layer 102 portion 108a and the insulating interlayer 102 exposed, wherein like thereto patterned mask layer 108a and 106a and the silicon oxide layer below the layer 104a also photoresist layer 110 along the previously defined direction substantially parallel to the FIG. 2B are arranged in a first direction, the y-axis.

请参照图1C,接着蚀刻去除此等硬罩幕HM(即罩幕层108a与氧化层106a),以留下多个硅层104a。 Referring to Figure 1C, is then removed by etching the hard mask HM such (i.e., the mask layer 108a and the oxidized layer 106a), to leave a plurality of silicon layers 104a. 接着,更进行一圆滑化程序以圆滑化硅层104a的上部边角,上述圆滑化程序例如为(a)于制程温度介于200~1000℃的氢气气氛下单一步骤的高温氢气热退火程序(high temperature H2annealing)或为(b)利用一热氧化程序于此等硅层104a表面形成一薄氧化层后再配合一蚀刻程序去除表面的薄氧化层,以达到圆滑化其上部边角功效的两步骤程序。 Next, a more rounded for programming to upper silicon layer 104a rounded corners, said rounded programming, for example, (a) heat between a high temperature hydrogen annealing process in a single step under a hydrogen atmosphere in 200 ~ 1000 ℃ process temperature ( high temperature H2annealing) or from (b) forming a thin oxide layer is formed by a surface thermal oxidation of the silicon layer 104a like this program with an etching process and then removing the thin oxide layer on the surface, to achieve rounded corners of its upper efficacy of two step procedure. 经由上述圆滑化程序所形成的多个上部边角圆滑化且具有鳍型外观(fin shape)的硅层104b后,接着进行一蚀刻程序以蚀刻绝缘层102,于绝缘层102内蚀刻出多个凹处(recess)112并同时形成多个突悬(overhang)的绝缘台地102a一体成形于绝缘层102上以支撑其上的多个硅层104b,且硅层104b的底面大于与绝缘台地102a接触的接触面而露出部分未接触绝缘台地102a的硅层104b底面。 After the upper corners of the formed plurality of via the programming smooth rounded appearance of a fin and having (fin shape) silicon layer 104b, followed by an etching process to etch the insulating layer 102, etched in the insulating layer 102, a plurality of insulating mesa recess (recess) 112 is formed, and simultaneously a plurality of overhang (overhang) of 102a integrally formed on the insulating layer 102 to support thereon a plurality of silicon layers 104b, 104b and the bottom surface of the silicon layer is larger than the contact 102a and the insulating mesa the exposed portion 104b does not contact the bottom surface of the silicon insulating layer mesa contact surface 102a. 上述的绝缘台地102a距绝缘层102约5~500埃的深度,而此蚀刻程序则例如为一湿蚀刻程序。 It said insulating member insulating layer 102 from the platform 102a about 5 to about 500 angstroms of depth, while this etching process is a wet etching process, for example.

请参照图1D,接着形成一顺应性的介电层114覆盖于绝缘层102、绝缘台地102a及硅层104b表面,其中介电层114并覆盖于硅层104b露出于绝缘台地102a的底面部分,介电层114的形成方法例如为溅镀法、热氧化法或化学气相沉积法(CVD),其中较佳方法为衍生自化学气相沉积法的原子层化学气相沉积法(ALCVD)或热氧化法,其厚度约介于5~50埃。 Referring to 1D, the then forming a compliant dielectric layer 114 covering the insulating mesa 102a and the surface of the insulating layer 102 a silicon layer 104b, and the dielectric layer 114 covering the silicon layer 104b is exposed to the bottom surface portion 102a of the insulating mesa, the method of forming the dielectric layer 114, for example, sputtering, thermal oxidation or chemical vapor deposition (CVD), wherein the method preferably derived from an atomic layer chemical vapor deposition (ALCVD) chemical vapor deposition method or a thermal oxidation method a thickness ranging from about 5 to 50 angstroms. 而介电层114的材质可选自一般常见的介电材料中二氧化硅(silicondioxide)或氮氧化硅(oxynitride)材料,亦可自相对电容率(relativepermittivity)大于5的高介电常数材料(high k dielectric)如氧化锆(ZrO2)、氧化铪(HfO2)、五氧化二钽(Ta2O5)、氧化钛(TiO2)以及氧化铝(Al2O3)等中选用。 The material of dielectric layer 114 may be selected from the general common dielectric material, silicon dioxide (silicondioxide), or silicon nitride oxide (oxynitride,) material, also from the relative permittivity (relativepermittivity) greater than a high dielectric constant material 5 ( high k dielectric) such as zirconia (ZrO2), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), titanium oxide (TiO2) and alumina (Al2O3) or the like selected. 值得注意地,在此若采用热氧化法以形成此介电层114,则此顺应性的介电层将仅形成于硅层104b的周围,而与图1D中的图示略有出入,在此图1D中的介电层114则以采用化学气相沉积法(CVD)所形成的顺应性介电层114表示。 Notably, this use of a thermal oxidation method to form this dielectric layer 114, then the compliant dielectric layer formed only around the silicon layer 104b, and a slight discrepancy in the illustration in FIG. 1D, the compliant dielectric layer in this dielectric layer 114 of FIG. 1D places by chemical vapor deposition (CVD) method 114 represents formed.

接着形成一毯覆性导电层116覆盖于介电层114上及一栅极的光阻图案118于导电层116上,导电层116的材质例如为复晶硅(polysilicon)、复晶硅锗(poly-SiGe)或金属,其形成方法例如为电浆加强型化学气相沉积法(PECVD)或溅镀法,其厚度约高于硅层104b表面500~2000埃。 Then forming a blanket conductive layer 116 covers the dielectric layer 114 and a gate 118 of the photoresist pattern on the conductive layer 116, the conductive material layer 116, for example, polycrystalline silicon (polysilicon), polysilicon germanium ( poly-SiGe) or a metal, for example, a method of forming a plasma enhanced chemical vapor deposition (PECVD) or sputtering, which is higher than the surface silicon layer thickness of about 500 ~ 2000 Å 104b. 此时,于图1D中的剖面结构是对应于俯视图图2C内A~A'切线中的剖面情形,其俯视结构则如图2C中所示,为导电层116所覆盖而仅显现出位于导电层116上的沿一第二方向延伸的一栅极的光阻图案118,此第二方向大体正交于此等硅层104b所排列的第一方向。 In this case, in the cross-sectional structure of FIG. 1D is a cross-sectional view corresponding to the case of tangent A ~ A 'within a top view of FIG. 2C which is a plan view configuration as shown in FIG. 2C, the conductive layer 116 is covered with the conductive only exhibit a gate photoresist pattern in a second direction extending layer 116 118, this second direction substantially orthogonal to this first direction of the silicon layer 104b and the like are arranged.

接着,请参照图1E,沿着此栅极的光阻图案118分别定义其下的导电层116与介电层114以分别形成一栅极导电层116a与一栅极介电层114a,并去除未为光阻图案118所覆盖区域内的导电层116与介电层114材料后,再行去除此光阻图案118,由上述部分覆盖于此等硅层104b上的栅极导电层116a与栅极介电层114a以构成一多重栅极G,此多重栅极G在此以图1E中一横跨于三独立的硅层104b的三栅极结构表示,实际多重栅极G所跨越的硅层的数量则可依照组件需求而作改变,而不在此加以限定其数量。 Next, referring to 1E, the resist pattern along which the gate electrode 118 define a gate conductive layer 116a and a gate dielectric layer 114a and the conductive layer 116 a dielectric layer 114 are formed in, and removed after the non-conductive material layer 114 and the dielectric layer 116 within the area covered by the photoresist pattern 118, again this photoresist pattern 118 is removed, the cover portion thereto by the gate conductive layer 116a and the like on the gate silicon layer 104b electrode dielectric layer 114a to form a multi-gate G, the gate G in this multiple to FIG. 1E across a triple gate structure in three separate silicon layers 104a and 104b, the gate G of the actual multi-spanned and the number of the silicon layer can be changed in accordance with component requirements, without the number being defined herein.

因整体结构关系,在此更采用视角正交于图1E的剖面图1F以作说明。 Because the overall structural relationship, in greater use in orthogonal cross-sectional perspective view of FIG. 1E 1F to be described. 接着进行一斜角度的淡掺杂离子植入120,利用适当的离子源植入于多重栅极G两侧的硅层104b表面,并经由一快速热回火程序以形成淡掺杂源极/漏极区122于硅层104b内及多重栅极G下方部分的硅层104b内,以作为防止短沟道效应(short channel effects;SCE)之用,而上述淡掺杂源极/漏极区122的形成方法亦可采用如电浆浸入式离子植入法(plasma immersion ion implantation)完成。 Followed by a ramp angle 120 of ion implantation lightly doped, with a suitable source of ion implantation on the surface 104b of multiple sides of the gate silicon layer G, via a rapid thermal annealing process to form a lightly doped source / a drain region 122 in the silicon layer and the silicon layer 104b inside the lower portion 104b of the multiple gate G, in order to prevent a short channel effect (short channel effects; SCE) purposes, and said lightly doped source / drain regions the method of forming a plasma 122 may also be employed such as immersion ion implantation (plasma immersion ion implantation) is completed.

此时,于图1E中的剖面结构是对应于俯视图2D内A~A'切线中的剖面情形,其俯视结构如图2D中所示,显现出一多重栅极G沿图2D中x方向的第二方向延伸,而于图1F中的剖面结构是对应于俯视图2D内B~B'切线中的剖面情形,借由先前的淡掺杂离子植入120及一快速热回火程序,于此多重栅极G两侧的多个硅层104b内形成了淡掺杂源极/漏极区122。 In this case, in the cross-sectional structure of FIG 1E is a plan view corresponding to the case where the cross-sectional 2D A ~ A 'of the tangent, a top structure is shown in FIG. 2D, showing an x-direction in FIG. 2D multi-gate G extending a second direction, and the cross-sectional structure in FIG. 1F is a cross-sectional view corresponding to the case B ~ B 'in the top view tangent to Figure 2D, by means of the previously lightly doped ion implantation 120, and a rapid thermal annealing process, in within this multiple silicon layers 104b plurality of sides of the gate G is formed of lightly doped source / drain regions 122.

请参阅图1G,采用视角正交于多重栅极G的剖面图以作说明,接着依照沉积-回蚀刻的方式,在多重栅极G的两侧壁形成一间隔物124,以作为栅极导电层116a的绝缘侧壁,一般为二氧化硅层,此外,间隔物112亦可为氮化硅(Si3N4)层或氮氧化硅层(Oxynitride;SiOxNy)。 Referring to FIG. 1G, using perspective cross-sectional view perpendicular to the gate G of the multiple instructions to be followed in accordance with the deposition - etch back embodiment, a spacers 124 are formed on both side walls of the multiple gate G, as a gate conductive sidewall 116a of the insulating layer, generally a silicon dioxide layer, in addition, the spacer 112 may also be silicon nitride (Si3N4) layer or a silicon oxynitride layer (oxynitride; SiOxNy).

随后,对多重栅极G两侧的硅层104b进行高浓度的离子植入126,即浓掺杂,以更形成多个源极/漏极区128于多重栅极G两侧的硅层104b内,并连接于多重栅极G下方的硅层104b内的多个淡掺杂源极/漏极区122,以构成一多重栅极晶体管,而位于多重栅极G下方介于多个源极/漏极区128间的硅层104b,即为此多重栅极的闸沟道(gate channel)。 Subsequently, the silicon layer 104b on multiple sides of the gate G in a high concentration ion implantation 126, i.e., heavily doped, to form a further plurality of source / drain regions 128 on multiple sides of the gate silicon layer 104b G inside, and connected to the plurality of light within the silicon layer 104b below the gate G of the multi-doped source / drain region 122, to form a multi-gate transistors, and between the gate G is positioned below the plurality of multiple sources source / drain regions 128 of the silicon layer 104b, i.e., the channel gate (gate channel) for this multiple gate. 此时,图1G中的剖面结构是对应于俯视图2E内沿B~B'切线内的剖面情形,而此时的俯视结构则如图2E中所示,仅显现出多重栅极G(栅极导电层116a)与其两侧之间隔物124以及多个位于多重栅极G两侧硅104b层内的源极/漏极区128及绝缘层102。 At this time, a cross-sectional structure of FIG. 1G is corresponding to the case where the cross-sectional plan view taken along a tangent B ~ B 'within 2E, the planar structure in this case is shown in FIG. 2E, only showing multiple gate G (gate conductive layer 116a) thereof spaced from the sides 124 and a plurality of sources located within the multi-layer 104b on both sides of the silicon gate electrode G / drain region 128 and the insulating layer 102. 而于图2E中A~A'切线内的剖面结构则同于图1E内的剖面结构,故不在于此另行图示。 Whereas in FIG. 2E A ~ A 'sectional structure of the same tangent to the cross-sectional structure within 1E, the prior thereto and therefore not illustrated.

请参照俯视图2F,当先前制程所选用的栅极导电层116a材质为多晶硅(polysilicon)时,在此可更进行一自对准金属硅化物制程(self-aligned sicilide)以于栅极导电层116a与源极/漏极区128的表面上形成金属硅化物层(salicide)130,以降低栅极导电层116a与此等源极/漏极区128的阻值(resistance),而上述金属硅化物层材质则例如为硅化钴(CoSi2)、硅化镍(NiSi)等耐火金属的硅化物。 Referring to a plan view 2F, when the previous process is the choice of the gate conductive layer 116a is made of polycrystalline silicon (polysilicon), this may further be a self-aligned silicide process (self-aligned sicilide) to the gate conductive layer 116a is formed on the surface of the source / drain region 128 of metal silicide layer (salicide) 130, 116a and these to reduce the source / drain region resistance (resistance) of the gate conductive layer 128, and the metal silicide layer is made, for example, cobalt silicide (CoSi2), nickel silicide (the NiSi) refractory metal silicide and the like.

而对应于俯视图2F中A~A'及B~B'切线内的剖面结构则分别如图1H及图1I中所示,原先表面上的硅材料部分形成了自对准金属硅化物层130。 To correspond to the cross-sectional structure in the plan view. 2F A ~ A 'and B ~ B' and are shown in the tangential 1H shown in FIG. 1I, part of the original silicon material is formed on the surface of the self-aligned metal silicide layer 130.

本实用新型的多重栅极G内多个为栅极导电层116a与门极介电层104b所覆盖且环绕的多个闸沟道(硅层104b),于依实际的组件设计定义出实际的多个源极及漏极后(各位于多重栅极G的同侧),配合适当的接触结构与此等漏极以及多重栅极G接触后,即可借由MOSFET的操作原理,借由多重栅极G的运作同时开启或关闭此等闸沟道,以提供适当的驱动电流,并利用本实用新型多重栅极G的环绕结构,以达成对于此等闸沟道良好的控制效果。 The present invention is a multi-gate G of a plurality of the gate conductive layer 116a and the gate dielectric layer 104b is covered and surrounded by a plurality of gate channel (silicon layer 104b), according to the actual component in the actual design definition after a plurality of source and drain (ipsilateral you multiple gate G), with appropriate contact with the contact structure of these multiple gate G and the drain, by means of the principle of operation to the MOSFET, by means of multiple operation of the gate G while these shutter opening or closing the channel, to provide an appropriate drive current, and the surrounding structure of the present invention using multiple gate G, for these gates to achieve good control channel effect.

Claims (19)

1.一种多重栅极结构,其特征在于包括:多个鳍型半导体层,沿一第一方向平行地排列,且由多个位于一绝缘层上的绝缘台地所支撑,其中该鳍型半导体层的底面大于与该绝缘台地的接触面;以及一栅极导电层,沿一第二方向延伸且覆盖于该鳍型半导体层的部分表面上,且于该栅极导电层与其所覆盖的该鳍型半导体层之间更设置有一栅极介电层,其中该栅极介电层更包覆于该栅极导电层所覆盖部分表面内的该鳍型半导体层的底面。 A multi-gate structure, comprising: a plurality of fin-type semiconductor layer, arranged in parallel along a first direction, a plurality of insulating and located on a platform supported by the insulating layer, wherein the semiconductor fin the conductive layer and a gate electrode, extending in a second direction and covering the upper surface of the fin-type semiconductor layer portion and the gate conductive layer in which it covers; backsheet is larger than the contact surface and the insulation of the mesa further provided with a gate dielectric layer between the fin-type semiconductor layer, wherein the gate dielectric layer is further coated on the bottom surface of the gate conductive layer fin-type semiconductor layer in a portion of the surface is covered.
2.根据权利要求1所述的多重栅极结构,其特征在于:该绝缘层是位于一半导体基底上。 2. The multi-gate structure according to claim 1, wherein: the insulating layer is positioned on a semiconductor substrate.
3.根据权利要求1所述的多重栅极结构,其特征在于:该第一方向正交于该第二方向。 3. The multi-gate structure according to claim 1, wherein: the first direction is orthogonal to the second direction.
4.根据权利要求1所述的多重栅极结构,其特征在于:该鳍型半导体层具有圆滑化的上部边角。 4. The multi-gate structure according to claim 1, wherein: the fin-type semiconductor layer having an upper rounded corners of.
5.根据权利要求1所述的多重栅极结构,其特征在于:更包括多个源极/漏极区,位于该多重栅极结构两侧未为该栅极导电层所覆盖的该鳍型半导体层内,以构成一具有多重栅极的多重栅极晶体管。 The multi-gate structure according to claim 1, characterized in that: further comprising a plurality of source / drain regions, located on both sides of the multi-gate structure for the fin-type non-conductive layer covered by the gate multiple-gate transistor within the semiconductor layer to form a gate electrode having multiple.
6.根据权利要求5所述的多重栅极结构,其特征在于:更包括多个淡掺杂源极/漏极区连接于该源极/漏极区,其中该淡掺杂源极/漏极区是位于该源极/漏极区间的该鳍型半导体层内。 6. The multi-gate structure according to claim 5, characterized in that: further comprising a plurality of lightly doped source / drain region connected to the source / drain region, wherein the lightly doped source / drain region within the fin-type semiconductor layer is the source / drain section.
7.根据权利要求1所述的多重栅极结构,其特征在于:于该栅极导电层两侧更包括一绝缘侧壁。 7. The multi-gate structure according to claim 1, wherein: on both sides of the gate conductive layer further comprises an insulating sidewall.
8.根据权利要求6所述的多重栅极结构,其特征在于:于该绝缘侧壁材质为氮化硅或二氧化硅。 8. The multi-gate structure according to claim 6, wherein: the side wall of the insulating material is silicon dioxide or silicon nitride.
9.根据权利要求1所述的多重栅极结构,其特征在于:该鳍型半导体层材质为硅或硅锗材料。 9. The multi-gate structure according to claim 1, wherein: the fin-type semiconductor layer is made of silicon or silicon germanium material.
10.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层材质为二氧化硅或氮氧化硅材质。 10. The multi-gate structure according to claim 1, wherein: the gate dielectric layer is made of silicon dioxide or silicon oxynitride materials.
11.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层的厚度介于5~50埃。 11. The multi-gate structure according to claim 1, wherein: a thickness of the gate dielectric layer ranges from 5 to 50 angstroms.
12.根据权利要求1所述的多重栅极结构,其特征在于:该栅极介电层材质为相对电容率大于5的材质。 12. The multi-gate structure according to claim 1, wherein: the gate dielectric layer is made of the relative permittivity of the material is greater than 5.
13.根据权利要求12所述的多重栅极结构,其特征在于:该相对电容率大于5的材质为五氧化二钽、氧化铪、氧化锆、氧化钛或氧化铝。 13. The multi-gate structure according to claim 12, wherein: the relative permittivity of the material is greater than 5 is tantalum pentoxide, hafnium oxide, zirconium oxide, titanium oxide or aluminum oxide.
14.根据权利要求1所述的多重栅极结构,其特征在于:该栅极导电层材质为复晶硅、复晶硅锗或金属。 14. The multi-gate structure according to claim 1, wherein: the gate conductive layer is made of polycrystalline silicon, polycrystalline silicon germanium or metal.
15.根据权利要求1所述的多重栅极结构,其特征在于:该绝缘台地是一体成形于该绝缘层上。 15. The multi-gate structure according to claim 1, wherein: the insulating mesa is integrally formed on the insulating layer.
16.根据权利要求15所述的多重栅极结构,其特征在于:该绝缘台地与该绝缘层的材质为二氧化硅。 16. The multi-gate structure according to claim 15, wherein: the insulating material of the insulating layer and the mesa is silicon dioxide.
17.根据权利要求1所述的多重栅极结构,其特征在于:于该栅极导电层上更包括一金属硅化物层。 17. The multi-gate structure according to claim 1, wherein: on the gate conductive layer further comprises a metal silicide layer.
18.根据权利要求5所述的多重栅极结构,其特征在于:位于该多重栅极结构两侧未为该栅极导电层所覆盖的该鳍型半导体层内的该源极/漏极区表面上更包括一金属硅化物层。 18. The multi-gate structure according to claim 5, wherein: the multi-gate located on both sides of the structure that is not the source of the fin-type semiconductor layer covered by the gate conductive layer source / drain region surface further comprises a metal silicide layer.
19.根据权利要求17或18所述的多重栅极结构,其特征在于:该金属硅化物层材质为硅化钴或硅化镍。 19. The multi-gate structure 17 or claim 18, wherein: said metal silicide layer is made of cobalt silicide or nickel silicide.
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CN101562194B (en) 2008-04-16 2012-07-04 索尼株式会社 Semiconductor device and method for manufacturing same
CN101207155B (en) 2006-12-22 2013-06-12 英特尔公司 Floating body memory cell having gates favoring different conductivity type regions

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101203093B (en) 2006-12-15 2011-06-15 英业达股份有限公司 Circuit board metallic layer amending method
CN101207155B (en) 2006-12-22 2013-06-12 英特尔公司 Floating body memory cell having gates favoring different conductivity type regions
CN101562194B (en) 2008-04-16 2012-07-04 索尼株式会社 Semiconductor device and method for manufacturing same

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