CN1328764C - Method for leveling semiconductor sedimentary deposit - Google Patents
Method for leveling semiconductor sedimentary deposit Download PDFInfo
- Publication number
- CN1328764C CN1328764C CNB031484018A CN03148401A CN1328764C CN 1328764 C CN1328764 C CN 1328764C CN B031484018 A CNB031484018 A CN B031484018A CN 03148401 A CN03148401 A CN 03148401A CN 1328764 C CN1328764 C CN 1328764C
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- mentioned
- layer
- semiconductor deposition
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention relates to a method for flattening the deposited layer of a semiconductor. In the method, firstly, a substrate is provided; then, the deposited layer of a semiconductor is formed on the substrate by a plasma chemical vapor deposition method; sequentially, the surface of the deposited layer of a semiconductor is treated by a sputter etching method; afterwards, the surface of the deposited layer of a semiconductor is flattened by a chemical-mechanical grinding method. The method uses the sputter etching method to treat the surface of the deposited layer of a semiconductor so as to increase the grinding efficiency for a chemical-mechanical grinder to grind the deposited layer of a semiconductor.
Description
Technical field
The present invention relates to a kind of method of flattening semiconductor deposition that makes, relate in particular to a kind of sputter etching (sputter etching) and chemical mechanical milling method (chemical mechanical polishing, CMP) method of processing semiconductor deposition laminar surface used in regular turn.
Background technology
In science and technology is maked rapid progress the modern society that develops, of all kinds being known as, make the modern reach the purpose of convenient life by means of these electronic products for high-tech electronic product one after the other incorporates in modern's the life.So electronic product becomes indispensable part in modern's daily life.Wherein, various electronic products all dispose different corresponding integrated circuit (integrated circuit, IC), and IC is gathered in circuit elements such as transistor, diode, resistor and capacitor on the wafer (Die) by semiconductor fabrication process, form complete logical circuit, realizing functions such as control, calculating or memory, thereby make electronic product bring into play its function and handle modern's various affairs.This brings great convenience for people's life.
Please refer to Figure 1A～1E, these figure make method of flattening semiconductor deposition flow process profile in the traditional semiconductor fabrication process.At first, in Figure 1A, provide a base material 12, base material 12 for example is a wafer (wafer), and forms a silicon oxynitride (SiON) layer 14 on base material 12.Then, on silicon oxynitride layer 14, form a silicon nitride (SiN) layer 16, and on silicon nitride layer 16 to photoresist layer 18 composition, shown in Figure 1B.Then, remove the silicon nitride layer 16 of exposed portions and the part silicon oxynitride layer 14 of below thereof, then remove part base material 12, in base material 12, to form many shallow channel (shallow trench), shown in Fig. 1 C.
After the photoresist layer 18 of composition has been removed, on base material 12, form semiconductor sedimentary deposit 22 with high density plasma chemical vapor deposition method (high density plasma chemical vapor deposition, HDP CVD), shown in Fig. 1 D.Semiconductor deposition 22 covers silicon nitride layer 16, and fills up above-mentioned shallow channel 20, and semiconductor deposition 22 for example is silicon dioxide (SiO
2) layer.In Fig. 1 D, semiconductor deposition 22 is provided with the sharp-pointed triangle of a plurality of projections, and these triangular structures are corresponding with the silicon nitride layer 16 of below.Each triangular structure has a peak A and a minimum point B, has a difference in height (step height) between peak A and the minimum point B.Then, (chemical mechanical polishing CMP) makes the surfacing of semiconductor deposition 22, the surface of promptly using chemical mechanical grinder grinding semiconductor sedimentary deposit 22 with chemical mechanical milling method, make that the surface of semiconductor deposition 22 is more smooth, shown in Fig. 1 E.
It should be noted that because the semiconductor deposition 22 of Fig. 1 D is provided with the sharp-pointed triangle of a plurality of projections, add that the difference in height of peak A and minimum point B is very big usually, cause the very out-of-flatness of surface of semiconductor deposition 22.Therefore, use the speed of chemical mechanical grinder grinding semiconductor sedimentary deposit 22 to reduce, so will prolong with the milling time of chemical mechanical grinder grinding semiconductor sedimentary deposit 22, this influence to semiconductor fabrication process is very big.So the speed and the minimizing milling time that improve with chemical mechanical grinder grinding semiconductor sedimentary deposit are technical tasks very urgent and urgent need solves.
Summary of the invention
In view of the above, the technical problem to be solved in the present invention provides a kind of method of flattening semiconductor deposition that makes, and the efficient that follow-up chemical mechanical grinder grinds this semiconductor deposition can be improved in the surface that this method is handled semiconductor deposition with sputter etching.
In order to address the above problem, making in the method for flattening semiconductor deposition that the present invention proposes, one base material at first is provided, then, on above-mentioned base material, form the semiconductor sedimentary deposit with high density plasma chemical vapor deposition method (high density plasmachemical vapor deposition, HDP CVD).Then, handle above-mentioned semiconductor deposition laminar surface with a sputter etching (sputter etching), wherein, with this semiconductor deposition laminar surface of nitrous oxide plasma sputtering.Then, (chemical mechanical polishing CMP) makes the surfacing of semiconductor deposition with chemical mechanical milling method.
The another kind that proposes in the present invention makes in the method for flattening semiconductor deposition, and a wafer at first is provided; On this wafer, form a silicon oxynitride layer again; Then, on silicon oxynitride layer, form a silicon nitride layer; Then, on silicon nitride layer, form the photoresist layer of composition; Remove the silicon nitride layer and the silicon oxynitride layer of exposed portions again; Then, in wafer, form many shallow channel; Then, remove the photoresist layer of composition; Afterwards, on base material, form the semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method, this semiconductor deposition cover part silicon nitride layer, and fill up above-mentioned shallow channel; Then, handle the semiconductor deposition laminar surface with sputter etching, wherein, with this semiconductor deposition laminar surface of nitrous oxide plasma sputtering.Then, make the semiconductor deposition surfacing with chemical mechanical milling method.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, will lift a preferred implementation below and also elaborate in conjunction with the accompanying drawings:
Figure 1A～1E makes method of flattening semiconductor deposition flow process profile in the traditional semiconductor fabrication process;
Fig. 2 is for making the method for flattening semiconductor deposition flow chart according to preferred implementation of the present invention;
Fig. 3 A～3F is for making method of flattening semiconductor deposition flow process profile according to preferred implementation of the present invention;
Fig. 4 is the relation curve of grinding rate and surface treatment situation.
The drawing reference numeral explanation
12,112: base material
14,114: silicon oxynitride layer
16,116: silicon nitride layer
18,118: the photoresist layer of composition
20,120: shallow channel
22,122: semiconductor deposition
Embodiment
The present invention proposes makes method of flattening semiconductor deposition, adopts sputter etching to handle the step of semiconductor deposition laminar surface, can improve the speed that follow-up chemical mechanical grinder grinds above-mentioned semiconductor deposition.
Please refer to Fig. 2 and Fig. 3 A～3F, wherein, Fig. 2 for according to preferred implementation of the present invention make the method for flattening semiconductor deposition flow chart, and Fig. 3 A～3F is for making method of flattening semiconductor deposition flow process profile according to preferred implementation of the present invention.At first, in step 202, provide a base material 112, base material 112 for example is a wafer (wafer), and forms a silicon oxynitride (SiON) layer 114 on base material 112, as shown in Figure 3A.Then, carry out step 204, on base material 112, form the semiconductor sedimentary deposit with high density plasma chemical vapor deposition method (high density plasma chemical vapor deposition, HDP CVD).
On base material 112, forming in the step of semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method, also can comprise a plurality of substeps: at first, on silicon oxynitride layer 114, form a silicon nitride (SiN) layer 116, and on silicon nitride layer 116, form the photoresist layer 118 of composition, shown in Fig. 3 B.Then, the silicon oxynitride layer 114 of the silicon nitride layer 116 of removal exposed portions and the part of below thereof, and remove part base material 112, in base material 112, to form many shallow channel (shallowtrench) 120, shown in Fig. 3 C.Then, remove the photoresist layer 118 of composition, and form semiconductor sedimentary deposit 122 with the high density plasma chemical vapor deposition method on base material 112, this semiconductor deposition 122 covers silicon nitride layer 116, and fill up above-mentioned shallow channel 120, shown in Fig. 3 D.Wherein, above-mentioned semiconductor deposition 122 for example is silicon dioxide (SiO
2) layer.In Fig. 3 D, semiconductor deposition 122 is provided with the sharp-pointed triangle of a plurality of projections, and these triangular structures are corresponding with the silicon nitride layer 116 of below.Each triangular structure has a peak A and a minimum point B, and has a difference in height (step height) between peak A and the minimum point B.
After semiconductor deposition 122 was formed, just carry out step 206, the surface with sputter etching (sputteretching) is handled semiconductor deposition 122 made that the surface of semiconductor deposition 122 can be more smooth a little, shown in Fig. 3 E.In Fig. 3 E, the triangular structure of institute's projection respectively has a peak C and a minimum point D on the semiconductor deposition 122.Can see significantly that the difference in height between peak C and the minimum point D is less than the difference in height between peak A among Fig. 3 D and the minimum point B.It should be noted that the present invention can also use oxygen (O
2) plasma, argon gas (Ar) plasma, nitrogen (N
2) plasma or nitrous oxide (N
2O) surface of plasma sputtering semiconductor deposition 122 is so that the surface of semiconductor deposition 122 is smooth slightly.In addition, high density plasma chemical vapor deposition and sputter etching (sputter etching) can successively be carried out in the high density plasma chemical vapor deposition machine.
Then, carry out step 208, with chemical mechanical milling method (chemical mechanical polishing, CMP) make above-mentioned semiconductor deposition 122 surfacings, promptly use the surface of chemical mechanical grinder grinding semiconductor sedimentary deposit 122, make that the surface of semiconductor deposition 122 is more smooth, shown in Fig. 3 F.
Because the triangular structure of institute's projection slightly is smooth with sputter etching on the semiconductor deposition 122 of Fig. 3 E, the peak C of Fig. 3 E and the difference in height of minimum point D are little, cause speed to improve many with chemical mechanical grinder grinding semiconductor sedimentary deposit 122, and shortened milling time, thereby can keep the operation fluency of semiconductor fabrication process.Even, also can prolong useful life of chemical mechanical grinder.
When grinding not the semiconductor deposition of being handled by sputter etching with chemical mechanical grinder, its grinding rate be about 750 (dust/minute, /min) is shown in the X point of Fig. 4.That is to say that the chemical mechanical grinder per minute can grind off the semiconductor deposition that thickness is 750 ().When grinding the semiconductor deposition of being handled by sputter etching with chemical mechanical grinder, its grinding rate be about 2000 (dust/minute, /min) is shown in the Y point of Fig. 4.That is to say that the chemical mechanical grinder per minute can grind off the semiconductor deposition that thickness is 2000 ().So the design of handling the surface of semiconductor deposition with sputter etching of the present invention helps improving the grinding efficiency of chemical mechanical grinder.
In disclosed the making in the method for flattening semiconductor deposition of the above-mentioned execution mode of the present invention, handle the semiconductor deposition laminar surface with sputter etching, can increase the grinding rate that follow-up chemical mechanical grinder grinds this semiconductor deposition.
In sum; though the present invention discloses as above with a preferred implementation; yet this is not to be limitation of the invention; any those of ordinary skill in the field; under the prerequisite that does not break away from design of the present invention and scope; can make various changes and retouching, so protection scope of the present invention should be as the criterion with the scope that accompanying claims were defined.
Claims (6)
1. one kind makes method of flattening semiconductor deposition, comprises the steps: at least
One base material is provided;
On above-mentioned base material, form the semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method;
Handle above-mentioned semiconductor deposition laminar surface with sputter etching, wherein, with this semiconductor deposition laminar surface of nitrous oxide plasma sputtering; And
Make the surfacing of semiconductor deposition with chemical mechanical milling method.
2. the method for claim 1, wherein above-mentioned base material comprises a wafer.
3. method as claimed in claim 2, the wherein above-mentioned step that forms the semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method on above-mentioned base material also comprises:
On above-mentioned base material, form a silicon oxynitride layer;
On this silicon oxynitride layer, form a silicon nitride layer;
On this silicon nitride layer, form the photoresist layer of composition;
Remove the above-mentioned silicon nitride layer and the silicon oxynitride layer of exposed portions;
In above-mentioned wafer, form many shallow channel;
Remove the photoresist layer of composition; And
On above-mentioned base material, form the semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method, this above-mentioned silicon nitride layer in semiconductor deposition cover part, and fill up above-mentioned shallow channel.
4. method as claimed in claim 3, wherein above-mentioned semiconductor deposition comprises a silicon dioxide layer.
5. one kind makes method of flattening semiconductor deposition, comprises the steps: at least
One wafer is provided;
On this wafer, form a silicon oxynitride layer;
On this silicon oxynitride layer, form a silicon nitride layer;
On this silicon nitride layer, form the photoresist layer of composition;
Remove the above-mentioned silicon nitride layer and the silicon oxynitride layer of exposed portions;
In above-mentioned wafer, form many shallow channel;
Remove the photoresist layer of above-mentioned composition;
On above-mentioned base material, form the semiconductor sedimentary deposit with the high density plasma chemical vapor deposition method, this above-mentioned silicon nitride layer in semiconductor deposition cover part, and fill up above-mentioned shallow channel;
Handle above-mentioned semiconductor deposition laminar surface with sputter etching, wherein, with this semiconductor deposition laminar surface of nitrous oxide plasma sputtering; And
Make above-mentioned semiconductor deposition surfacing with chemical mechanical milling method.
6. method as claimed in claim 5, wherein above-mentioned semiconductor deposition comprises a silicon dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031484018A CN1328764C (en) | 2003-06-27 | 2003-06-27 | Method for leveling semiconductor sedimentary deposit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031484018A CN1328764C (en) | 2003-06-27 | 2003-06-27 | Method for leveling semiconductor sedimentary deposit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567540A CN1567540A (en) | 2005-01-19 |
| CN1328764C true CN1328764C (en) | 2007-07-25 |
Family
ID=34472277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031484018A Expired - Fee Related CN1328764C (en) | 2003-06-27 | 2003-06-27 | Method for leveling semiconductor sedimentary deposit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1328764C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103144011B (en) * | 2011-12-06 | 2016-05-18 | 有研半导体材料有限公司 | A kind of method and burnishing device of controlling silicon wafer polishing surface microroughness |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6001740A (en) * | 1997-09-30 | 1999-12-14 | Siemens Aktiengesellschaft | Planarization of a non-conformal device layer in semiconductor fabrication |
| US6060394A (en) * | 1997-06-24 | 2000-05-09 | Texas Instruments-Acer Incorporated | Method for forming shallow trench isolation with global planarization |
| US6207538B1 (en) * | 1999-12-28 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | Method for forming n and p wells in a semiconductor substrate using a single masking step |
| US6261957B1 (en) * | 1999-08-20 | 2001-07-17 | Taiwan Semiconductor Manufacturing Company | Self-planarized gap-filling by HDPCVD for shallow trench isolation |
| JP2002246387A (en) * | 2001-02-19 | 2002-08-30 | Sharp Corp | Method of manufacturing semiconductor device |
-
2003
- 2003-06-27 CN CNB031484018A patent/CN1328764C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060394A (en) * | 1997-06-24 | 2000-05-09 | Texas Instruments-Acer Incorporated | Method for forming shallow trench isolation with global planarization |
| US6001740A (en) * | 1997-09-30 | 1999-12-14 | Siemens Aktiengesellschaft | Planarization of a non-conformal device layer in semiconductor fabrication |
| US6261957B1 (en) * | 1999-08-20 | 2001-07-17 | Taiwan Semiconductor Manufacturing Company | Self-planarized gap-filling by HDPCVD for shallow trench isolation |
| US6207538B1 (en) * | 1999-12-28 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | Method for forming n and p wells in a semiconductor substrate using a single masking step |
| JP2002246387A (en) * | 2001-02-19 | 2002-08-30 | Sharp Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1567540A (en) | 2005-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5850105A (en) | Substantially planar semiconductor topography using dielectrics and chemical mechanical polish | |
| US6548399B1 (en) | Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer | |
| TW262565B (en) | A method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used | |
| CN107017161B (en) | Method for reducing dishing recess in STI-CMP process | |
| US20060261041A1 (en) | Method for manufacturing metal line contact plug of semiconductor device | |
| CN101308790A (en) | Method for removing dielectric layer on substrate and chemical mechanical polishing process | |
| WO1999046081A1 (en) | Multi-step chemical mechanical polishing process and device | |
| CN100353521C (en) | Chemical mechanical polishing process for manufacturing interconnection line structure of semiconductor devices | |
| CN1328764C (en) | Method for leveling semiconductor sedimentary deposit | |
| KR20050033180A (en) | Method for planarizing oxide layer and method for manufacturing semiconductor device using the same | |
| CN104078346A (en) | Planarization method for semi-conductor device | |
| CN100414666C (en) | Composite chemically mechanical polishing method | |
| CN102054665A (en) | Method for processing epitaxial substrate | |
| CN102479695B (en) | Method for improving uniformity of chemical mechanical planarization process of metal gate | |
| US7199018B2 (en) | Plasma assisted pre-planarization process | |
| US6551922B1 (en) | Method for making a semiconductor device by variable chemical mechanical polish downforce | |
| CN102800580B (en) | Polishing method and gate forming method | |
| CN109841512A (en) | The manufacturing method of semiconductor device | |
| US7109117B2 (en) | Method for chemical mechanical polishing of a shallow trench isolation structure | |
| KR100734653B1 (en) | Oxide cmp method | |
| CN1379446A (en) | Chemicomechanical grinding method combined with rotary coating | |
| KR100312647B1 (en) | Planarization method of semiconductor device | |
| JP2000357674A (en) | Integrated circuit chip and planarizing method | |
| CN105990130A (en) | Planarization method | |
| JP2001210710A (en) | Forming process of shallow trench isolation utilizing sacrificial layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070725 Termination date: 20190627 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |