CN1320651C - Chip with a plurality of internal functional blocks and method for power supply and noise reduction - Google Patents
Chip with a plurality of internal functional blocks and method for power supply and noise reduction Download PDFInfo
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- CN1320651C CN1320651C CNB2004100887543A CN200410088754A CN1320651C CN 1320651 C CN1320651 C CN 1320651C CN B2004100887543 A CNB2004100887543 A CN B2004100887543A CN 200410088754 A CN200410088754 A CN 200410088754A CN 1320651 C CN1320651 C CN 1320651C
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- functional blocks
- internal functional
- reference source
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 230000005611 electricity Effects 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
The present invention discloses a chip with a plurality of internal function blocks, which is composed of an internal chip section and an external encapsulating section, wherein the internal chip section comprises a reference source and at least two sets of internal functional blocks; a soldering pan is correspondingly arranged on each internal functional block; the external encapsulating section of the chip is provided with a chip base pin; the soldering pans are respectively and conductively connected with the chip base pin by soldering lines; an output end of the reference source is at least conductively connected with one of the soldering pans by an internal connecting line of the chip so as to supply power to each internal functional block. The present invention also simultaneously discloses a method for supplying power and reducing noises of the chip with the internal function blocks. When the chip structure is adopted, a decoupling capacitor connected in series between the chip base pin and the earth is arranged in an external circuit of the chip. Compared with the prior art, the present invention has the characteristics of simple circuit structure, reduced processing and use cost, improved chip and the integration level of the operating environment, etc.
Description
Technical field
The present invention relates to a kind of chip, particularly a kind of in-line power structure with chip of a plurality of internal functional blocks with a plurality of internal functional blocks; The present invention also relates to a kind of method of power supply noise reduction of the chip with a plurality of internal functional blocks simultaneously.
Technical background
At present in the integrated chip design process, when having a plurality of internal functional blocks, for fear of the noise jamming that causes owing to common source between each internal functional blocks, often have to adopt each internal functional blocks to separate independently-powered mode, promptly organize a reference source in the inside chip partial design of integrated chip more, every group of corresponding one group of internal functional blocks of a reference source, and independently-powered to its corresponding internal functional blocks.Because what adopt is the mode of powering separately, therefore many group a reference sources must be set, thereby cause a reference source to occupy too much area, the chip entire area is increased, this is for reducing chip area at present, and the technology trends that increases chip integration is quite disadvantageous beyond doubt.In addition, because the output of every group of a reference source must add decoupling capacitor, just can reach the purpose that reduces noise, therefore prior art must be provided with a plurality of pads in inside chip part correspondence again, outer enclosure part correspondence at chip is provided with a plurality of chip pins, and the output of chip pin, pad, a reference source conducted electricity connection one to one, and many group decoupling capacitors are set in the peripheral circuit of this chip again, each decoupling capacitor is connected on respectively between chip pin and the ground.This mode causes chip periphery circuit structure complexity, and cost increases, and the area coverage of peripheral circuit also has to increase, and is unfavorable for improving the integrated level of circuit equally.
Summary of the invention
The objective of the invention is: at the deficiencies in the prior art, provide a kind of and simplify circuit, reduce cost, reduce area, improve the chip with a plurality of internal functional blocks of chip integration.The present invention also provides a kind of method of power supply noise reduction of the chip with a plurality of internal functional blocks simultaneously.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of chip with a plurality of internal functional blocks, partly constitute by inside chip part and outer enclosure, described inside chip partly comprises at least two group internal functional blocks, described inside chip part also comprises an a reference source, power supply as the described group of net at least internal functional blocks, described inside chip is partly gone up corresponding to each internal functional blocks and is provided with pad, the outer enclosure of described chip partly is provided with a chip pin, described pad is connected with this chip pin conduction by bonding wire respectively, and the output of described a reference source is connected with one of them pad conduction at least by the chip internal connecting line.
The output of described a reference source can be connected with at least one group of internal functional blocks conduction by the chip internal connecting line.
Described a plurality of pad can be arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
Described internal functional blocks can have two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit.
Described pad can have two, and one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line.
The output of described a reference source can be connected with the internal logic circuit conduction.
A kind of power supply noise-reduction method with chip of a plurality of internal functional blocks, has the chip internal of a plurality of internal functional blocks, adopt an a reference source, and corresponding each internal functional blocks is provided with a pad of conduction connection with it, a chip pin is set on the outer enclosure of chip, described each pad all is connected on this chip pin by bonding wire, the output of described a reference source is connected with pad conduction at least, thus make a reference source can the while as the power supply of described a plurality of internal functional blocks; At the outer setting decoupling capacitor of this chip, and described decoupling capacitor is connected in series between described chip pin and the ground.
The output of described a reference source can be connected with at least one group of internal functional blocks conduction by the chip internal connecting line.
Described a plurality of pad can be arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
Described internal functional blocks can have two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit; Described pad has two, and one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line; The output of described a reference source is connected with the internal logic circuit conduction.
In technique scheme, the present invention is owing to adopt the public power power supplier of an a reference source as a plurality of internal functional blocks, thereby relative prior art, can significantly reduce a reference source area occupied, facility on the space that provides for the quantity increase of internal functional blocks has also been saved the cost of chip itself.Simultaneously, owing to adopt a plurality of pads to utilize the bonding wire ways of connecting with a chip pin respectively, thus can between different internal functional blocks, introduce the inductance of bonding wire, reach the purpose that reduces internal functional blocks noise jamming each other.And the chip pin that is used for being connected with decoupling capacitor only needs one, also provides the space for chip increases other function pin.In addition, the decoupling capacitor that is provided with for the decoupling noise reduction in the peripheral circuit also only needs one, thereby has saved the space of peripheral circuit, the cost of manufacture of also having saved the chip periphery circuit.Therefore, relative prior art, the present invention has the characteristics such as integrated level that circuit structure is simple, can reduce processing and use cost, raising chip itself and environment for use.
Description of drawings
Accompanying drawing 1 is a kind of structural representation with chip of a plurality of internal functional blocks of the present invention.
Embodiment
Below in conjunction with Figure of description and specific embodiment the present invention is described in further detail.
For the ease of understanding, a kind of embodiment provided by the invention is applied on the chip with phase-locked loop.
With reference to the accompanying drawings, a kind of chip with a plurality of internal functional blocks of this enforcement is made of inside chip part 2 and outer enclosure part 4, and described inside chip part 2 comprises two groups of internal functional blocks, and wherein one group is phase-locked loop 5, and another group is internal logic circuit 3.Described inside chip part also comprises an a reference source 1, as the power supply of described two groups of internal functional blocks.
In the present embodiment, be provided with pad 7,12 corresponding to each internal functional blocks on the described inside chip part 2.The outer enclosure part 4 of described chip is provided with a chip pin 10.Described pad 7,12 is connected with these chip pin 10 conductions by bonding wire 8,11 respectively, and the output of described a reference source 1 is connected with pad 12 conductions at least by chip internal connecting line 6.
Described pad 12 is connected with the output conduction of described a reference source 1 by internal connection line 6, and another is connected with described phase-locked loop 5 conductions by internal connection line 6.The output of described a reference source 1 is connected with internal logic circuit 3 conductions.
Described pad 12 is arranged adjacent in the edge of inside chip part, thereby described bonding wire 8,11 is distributed in the outer enclosure part 4.
A kind of power supply noise-reduction method that present embodiment provided with chip of a plurality of internal functional blocks, except that chip internal adopts the public power supply of an a reference source 1 as phase-locked loop 5 and internal logic circuit 3, also at the outer setting decoupling capacitor 9 of this chip, and described decoupling capacitor 9 is connected in series between described chip pin 10 and the ground.Thereby between two groups of internal functional blocks, introduce the inductance of bonding wire 8,11 on the one hand, reduce by two groups of noise jamming that internal functional blocks is mutual; And, also utilize decoupling capacitor 9 to reach the purpose of decoupling noise reduction.
It below only is the specific embodiment of a kind of application of the present invention.In fact, when chip internal has two or more functional blocks, and between a plurality of functional block as directly common source have the noise jamming problem time, can adopt structure provided by the present invention and method.Therefore, as those skilled in the art, easily technical scheme of the present invention is applied to present embodiment and has on the chip beyond the chip of phase-locked loop.Therefore, all changes of doing according to technical solution of the present invention when the function that is produced does not exceed the scope of technical solution of the present invention, all belong to protection scope of the present invention.
Claims (10)
1, a kind of chip with a plurality of internal functional blocks, partly constitute by inside chip part and outer enclosure, described inside chip partly comprises at least two group internal functional blocks, it is characterized in that: described inside chip part also comprises an a reference source, power supply as described at least two group internal functional blocks, described inside chip is partly gone up corresponding to each internal functional blocks and is provided with pad, the outer enclosure of described chip partly is provided with a chip pin, described pad is connected with this chip pin conduction by bonding wire respectively, and the output of described a reference source is connected with one of them pad conduction at least by the chip internal connecting line.
2, have the chip of a plurality of internal functional blocks according to claim 1, it is characterized in that: the output of described a reference source is connected with at least one group of internal functional blocks conduction by the chip internal connecting line.
3, have the chip of a plurality of internal functional blocks according to claim 1, it is characterized in that: described a plurality of pads are arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
4, as having the chip of a plurality of internal functional blocks as described in claim 1 or 2 or 3, it is characterized in that: described internal functional blocks has two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit.
5, as having the chip of a plurality of internal functional blocks as described in the claim 4, it is characterized in that: described pad has two, one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line.
6, as having the chip of a plurality of internal functional blocks as described in the claim 5, it is characterized in that: the output of described a reference source is connected with the internal logic circuit conduction.
7, a kind of power supply noise-reduction method with chip of a plurality of internal functional blocks, it is characterized in that: have the chip internal of a plurality of internal functional blocks, adopt an a reference source, and corresponding each internal functional blocks is provided with a pad of conduction connection with it, a chip pin is set on the outer enclosure of chip, described each pad all is connected on this chip pin by bonding wire, the output of described a reference source is connected with pad conduction at least, thus make a reference source can the while as the power supply of described a plurality of internal functional blocks; At the outer setting decoupling capacitor of this chip, and described decoupling capacitor is connected in series between described chip pin and the ground.
8, as having the power supply noise-reduction method of the chip of a plurality of internal functional blocks as described in the claim 7, it is characterized in that: the output of described a reference source conducts electricity with at least one group of internal functional blocks by the chip internal connecting line and is connected.
9, as having the power supply noise-reduction method of the chip of a plurality of internal functional blocks as described in the claim 7, it is characterized in that: described a plurality of pads are arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
10, as having the power supply noise-reduction method of the chip of a plurality of internal functional blocks as described in claim 7 or 8 or 9, it is characterized in that: described internal functional blocks has two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit; Described pad has two, and one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line; The output of described a reference source is connected with the internal logic circuit conduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100887543A CN1320651C (en) | 2004-11-03 | 2004-11-03 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100887543A CN1320651C (en) | 2004-11-03 | 2004-11-03 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1604325A CN1604325A (en) | 2005-04-06 |
| CN1320651C true CN1320651C (en) | 2007-06-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100887543A Expired - Fee Related CN1320651C (en) | 2004-11-03 | 2004-11-03 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
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| Country | Link |
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| CN (1) | CN1320651C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108181491A (en) * | 2018-01-03 | 2018-06-19 | 江苏林洋能源股份有限公司 | A kind of method for improving electric energy meter measuring accuracy and measuring reliability |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1389912A (en) * | 2002-06-13 | 2003-01-08 | 威盛电子股份有限公司 | Chip package structre and its substrate board |
| US6738258B2 (en) * | 2001-12-06 | 2004-05-18 | Abb Research Ltd | Power semiconductor module |
| CN2746531Y (en) * | 2004-11-03 | 2005-12-14 | 北京中星微电子有限公司 | Chip with multiple internal function block |
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2004
- 2004-11-03 CN CNB2004100887543A patent/CN1320651C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6738258B2 (en) * | 2001-12-06 | 2004-05-18 | Abb Research Ltd | Power semiconductor module |
| CN1389912A (en) * | 2002-06-13 | 2003-01-08 | 威盛电子股份有限公司 | Chip package structre and its substrate board |
| CN2746531Y (en) * | 2004-11-03 | 2005-12-14 | 北京中星微电子有限公司 | Chip with multiple internal function block |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1604325A (en) | 2005-04-06 |
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Granted publication date: 20070606 Termination date: 20121103 |