CN2746531Y - Chip with multiple internal function block - Google Patents
Chip with multiple internal function block Download PDFInfo
- Publication number
- CN2746531Y CN2746531Y CN 200420112011 CN200420112011U CN2746531Y CN 2746531 Y CN2746531 Y CN 2746531Y CN 200420112011 CN200420112011 CN 200420112011 CN 200420112011 U CN200420112011 U CN 200420112011U CN 2746531 Y CN2746531 Y CN 2746531Y
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- Prior art keywords
- chip
- internal
- functional blocks
- internal functional
- reference source
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- Expired - Lifetime
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- 230000010354 integration Effects 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 239000003990 capacitor Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Abstract
The utility model discloses a chip with a plurality of internal function blocks, which is composed of an internal chip part and an external packaging part, wherein, the internal chip part comprises a reference source and at least two groups of internal function blocks, and bonding pads corresponding to the internal function blocks are also arranged; the external packaging part of the chip is provided with a chip base pin, and the bonding pads are respectively in conductive connection with the chip base pin through bonding wires. The output terminal of the reference source is in conductive connection with at least one of the bonding pads through a connecting wire in the chip, so that power can be supplied to each of the internal function blocks. Compared with the prior art, the utility model has the characteristics that the circuit structure is simple, the processing and using cost can be lowered, the integration levels of the chip and using environments can be enhanced, etc.
Description
Technical field
The utility model relates to a kind of chip with a plurality of internal functional blocks, particularly a kind of in-line power structure with chip of a plurality of internal functional blocks.
Technical background
At present in the integrated chip design process, when having a plurality of internal functional blocks, for fear of the noise jamming that causes owing to common source between each internal functional blocks, often have to adopt each internal functional blocks to separate independently-powered mode, promptly organize a reference source in the inside chip partial design of integrated chip more, every group of corresponding one group of internal functional blocks of a reference source, and independently-powered to its corresponding internal functional blocks.Because what adopt is the mode of powering separately, therefore many group a reference sources must be set, thereby cause a reference source to occupy too much area, the chip entire area is increased, this is for reducing chip area at present, and the technology trends that increases chip integration is quite disadvantageous beyond doubt.In addition, because the output of every group of a reference source must add decoupling capacitor, just can reach the purpose that reduces noise, therefore prior art must be provided with a plurality of pads in inside chip part correspondence again, outer enclosure part correspondence at chip is provided with a plurality of chip pins, and the output of chip pin, pad, a reference source conducted electricity connection one to one, and many group decoupling capacitors are set in the peripheral circuit of this chip again, each decoupling capacitor is connected on respectively between chip pin and the ground.This mode causes chip periphery circuit structure complexity, and cost increases, and the area coverage of peripheral circuit also has to increase, and is unfavorable for improving the integrated level of circuit equally.
The utility model content
The purpose of this utility model is: at the deficiencies in the prior art, provide a kind of and simplify circuit, reduce cost, reduce area, improve the chip with a plurality of internal functional blocks of chip integration.
In order to solve the problems of the technologies described above, technical solution adopted in the utility model is: a kind of chip with a plurality of internal functional blocks, partly constitute by inside chip part and outer enclosure, described inside chip partly comprises at least two group internal functional blocks, described inside chip part also comprises an a reference source, power supply as described at least two group internal functional blocks, described inside chip is partly gone up corresponding to each internal functional blocks and is provided with pad, the outer enclosure of described chip partly is provided with a chip pin, described pad is connected with this chip pin conduction by bonding wire respectively, and the output of described a reference source is connected with one of them pad conduction at least by the chip internal connecting line.
The output of described a reference source can be connected with at least one group of internal functional blocks conduction by the chip internal connecting line.
Described a plurality of pad can be arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
Described internal functional blocks can have two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit.
Described pad can have two, and one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line.
The output of described a reference source can be connected with the internal logic circuit conduction.
In technique scheme, the utility model is owing to adopt the public power power supplier of an a reference source as a plurality of internal functional blocks, thereby relative prior art, can significantly reduce a reference source area occupied, facility on the space that provides for the quantity increase of internal functional blocks has also been saved the cost of chip itself.Simultaneously, owing to adopt a plurality of pads to utilize the bonding wire ways of connecting with a chip pin respectively, thus can between different internal functional blocks, introduce the inductance of bonding wire, reach the purpose that reduces internal functional blocks noise jamming each other.And the chip pin that is used for being connected with decoupling capacitor only needs one, also provides the space for chip increases other function pin.In addition, the decoupling capacitor that is provided with for the decoupling noise reduction in the peripheral circuit also only needs one, thereby has saved the space of peripheral circuit, the cost of manufacture of also having saved the chip periphery circuit.Therefore, prior art the utlity model has the characteristics such as integrated level that circuit structure is simple, can reduce processing and use cost, raising chip itself and environment for use relatively.
Description of drawings
Accompanying drawing 1 is a kind of structural representation with chip of a plurality of internal functional blocks of the utility model.
Embodiment
Below in conjunction with Figure of description and specific embodiment the utility model is described in further detail.
A kind of embodiment that the utility model provides is applied on the chip with phase-locked loop.
With reference to the accompanying drawings, a kind of chip with a plurality of internal functional blocks of this enforcement is made of inside chip part 2 and outer enclosure part 4, and described inside chip part 2 comprises two groups of internal functional blocks, and wherein one group is phase-locked loop 5, and another group is internal logic circuit 3.Described inside chip part also comprises an a reference source 1, as the power supply of described two groups of internal functional blocks.
In the present embodiment, be provided with pad 7,12 corresponding to each internal functional blocks on the described inside chip part 2.The outer enclosure part 4 of described chip is provided with a chip pin 10.Described pad 7,12 is connected with these chip pin 10 conductions by bonding wire 8,11 respectively, and the output of described a reference source 1 is connected with pad 12 conductions at least by chip internal connecting line 6.
Described pad 12 is connected with the output conduction of described a reference source 1 by internal connection line 6, and another is connected with described phase-locked loop 5 conductions by internal connection line 6.The output of described a reference source 1 is connected with internal logic circuit 3 conductions.
Described pad 12 is arranged adjacent in the edge of inside chip part, thereby described bonding wire 8,11 is distributed in the outer enclosure part 4.
Adopt that present embodiment provided have the chip of a plurality of internal functional blocks the time, can be except that chip internal adopts the public power supply of an a reference source 1 as phase-locked loop 5 and internal logic circuit 3, also at the outer setting decoupling capacitor 9 of this chip, and described decoupling capacitor 9 is connected in series between described chip pin 10 and the ground.Thereby between two groups of internal functional blocks, introduce the inductance of bonding wire 8,11 on the one hand, reduce by two groups of noise jamming that internal functional blocks is mutual; And, also utilize decoupling capacitor 9 to reach the purpose of decoupling noise reduction.
It below only is the specific embodiment of a kind of application of the present utility model.In fact, when chip internal has two or more functional blocks, and between a plurality of functional block as directly common source have the noise jamming problem time, can adopt structure provided by the utility model and method.Therefore, as those skilled in the art, easily the technical solution of the utility model is applied to present embodiment and has on the chip beyond the chip of phase-locked loop.Therefore, all changes of doing according to technical solutions of the utility model when the function that is produced does not exceed the scope of technical solutions of the utility model, all belong to protection range of the present utility model.
Claims (6)
1, a kind of chip with a plurality of internal functional blocks, partly constitute by inside chip part and outer enclosure, described inside chip partly comprises at least two group internal functional blocks, it is characterized in that: described inside chip part also comprises an a reference source, power supply as described at least two group internal functional blocks, described inside chip is partly gone up corresponding to each internal functional blocks and is provided with pad, the outer enclosure of described chip partly is provided with a chip pin, described pad is connected with this chip pin conduction by bonding wire respectively, and the output of described a reference source is connected with one of them pad conduction at least by the chip internal connecting line.
2, have the chip of a plurality of internal functional blocks according to claim 1, it is characterized in that: the output of described a reference source is connected with at least one group of internal functional blocks conduction by the chip internal connecting line.
3, have the chip of a plurality of internal functional blocks according to claim 1, it is characterized in that: described a plurality of pads are arranged adjacent in the edge of inside chip part, and described bonding wire is distributed in the outer enclosure part.
4, as having the chip of a plurality of internal functional blocks as described in claim 1 or 2 or 3, it is characterized in that: described internal functional blocks has two groups, and wherein one group is phase-locked loop, and another group is internal logic circuit.
5, as having the chip of a plurality of internal functional blocks as described in the claim 4, it is characterized in that: described pad has two, one of them is connected with the output conduction of described a reference source by internal connection line, and another is connected with described phase-locked loop conduction by internal connection line.
6, as having the chip of a plurality of internal functional blocks as described in the claim 5, it is characterized in that: the output of described a reference source is connected with the internal logic circuit conduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420112011 CN2746531Y (en) | 2004-11-03 | 2004-11-03 | Chip with multiple internal function block |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420112011 CN2746531Y (en) | 2004-11-03 | 2004-11-03 | Chip with multiple internal function block |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2746531Y true CN2746531Y (en) | 2005-12-14 |
Family
ID=35583108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420112011 Expired - Lifetime CN2746531Y (en) | 2004-11-03 | 2004-11-03 | Chip with multiple internal function block |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2746531Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320651C (en) * | 2004-11-03 | 2007-06-06 | 北京中星微电子有限公司 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
-
2004
- 2004-11-03 CN CN 200420112011 patent/CN2746531Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320651C (en) * | 2004-11-03 | 2007-06-06 | 北京中星微电子有限公司 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20041103 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |