CN1389912A - Chip package structre and its substrate board - Google Patents
Chip package structre and its substrate board Download PDFInfo
- Publication number
- CN1389912A CN1389912A CN 02123232 CN02123232A CN1389912A CN 1389912 A CN1389912 A CN 1389912A CN 02123232 CN02123232 CN 02123232 CN 02123232 A CN02123232 A CN 02123232A CN 1389912 A CN1389912 A CN 1389912A
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- Prior art keywords
- power supply
- supply area
- core power
- crystal grain
- capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Structure Of Printed Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses the structure for encapsulating chip and the substrate plate in the structure. The electric power area of the power pins that controls the core area of the each control unit connected to the crystal grain is divided into two parts. At least one phi type filter is utilized to insulate the different electric power area in order to prevent the mutual interference noise so as to make the chip operation more stable. The pin type filter is put in the corner to complete the wiring layout easily.
Description
Technical field
The present invention relates to a kind of semiconductor package, and particularly relevant for the substrate plate in a kind of chip-packaging structure and the structure.
Background technology
The evolution of semiconductor fabrication techniques now is at a tremendous pace, therefore, integrated circuit (the Integrated Circuit that uses the semiconductor fabrication techniques manufacturing to form, abbreviation IC) evolution of integration is also by Small Scale Integration (Small Scale Integration, abbreviation SSI), large scale integrated circuit (Large Scale Integration, be called for short LSI), so that luxuriant be the great scale integrated circuit (Ultra-Large Scale Integration, abbreviation ULSI) of main flow.No matter the purposes of these circuit why, it normally uses semiconductor fabrication techniques to be made on the wafer (wafer), the applicable integrated circuit sum that each wafer comprises is decided according to the door number (gatecounts) of semiconductor fabrication process and circuit itself, and then wafer is cut into the crystal grain (die) that only comprises a unit integrated circuit, and use encapsulation (packaging) technology and encapsulated to form and can be applicable to common printed circuit board (PCB) (Printed Circuit Board, abbreviation PCB) chip on, that is the IC that generally is commonly called as.
Because the integration of application integrated circuit constantly promotes, so that also shape complexity more and more of the function of integrating on IC, required I/O (Input/Output the is called for short I/O) pin count of its encapsulation is also more and more many.Therefore, encapsulation technology is also constantly deduced and is improved, in early days QFP (the quad flat pack) encapsulation of crystal grain framework on lead frame (Lead Frame) is not inconsistent gradually required, even recent PGA (pin-grid array) encapsulation also can't meet the demand of high I/O pin count.So, a kind of with the crystal grain framework in based on ball lattice array (the Ball Grid Array on the substrate plate (substrate) of a small pieces tellite of printed circuit technique, abbreviation BGA) encapsulation is to arise at the historic moment, and has become the encapsulation main flow of the IC of high I/O pin count.
Please refer to shown in Figure 1ly, it is a kind of substrate plate schematic diagram of existing north bridge chips encapsulating structure.This place illustrates be substrate plate 100 in order to paste the one side of crystal grain, wherein for simplicity of illustration makes it more for the purpose of the easy identification, many weld pads that can be connected with wiring pad on the crystal grain with metal wire and the wiring of drawing crystal grain I/O pin are all omitted.
In general, north bridge chips can connect central processing unit (Central ProcessingUnit is called for short CPU), Accelerated Graphics Port (Accelerated Graphic Port is called for short AGP) device, Installed System Memory and South Bridge chip usually.Therefore, north bridge chips inside just has the central processing unit control unit, Accelerated Graphics Port control unit, memory control unit, and the function square circuit of South Bridge chip control unit several sections such as (not illustrating).And the I/O of north bridge chips for the I/O of the device that is connected between do the transmission of information, therefore, must provide the power supply of these devices on the substrate plate 100 of north bridge chips.
Therefore, its power generation configuration comprises an access area 110 and a plurality of power supply area 120,130,140,150 and 160 as shown in FIG..Wherein access area 110 is used for pasting the grounding leg position of crystal grain and connection crystal grain.Power supply area 120 is the power supply (V in order to the I/O part of Accelerated Graphics Port control unit that crystal grain is provided
Cc1) power supply pin, be generally 1.5V voltage.Power supply area 130 is the power supply (V in order to the I/O part of South Bridge chip control unit that crystal grain is provided
Cc2) power supply pin, generally also be 1.5V voltage.Power supply area 140 is the power supply (V in order to the I/O part of memory control unit that crystal grain is provided
Cc3) power supply pin, be generally 2.5V voltage.Power supply area 150 is the power supply (V in order to the I/O part of central processing unit control unit that crystal grain is provided
Tt) power supply pin, generally also be 1.5V voltage, power supply area 160 then is the power supply (V of the core of each unit of connecting crystal grain
Core) power supply pin, V
CoreVoltage be 2.5V.
Each unit on the north bridge chips for will with the transmission of external device (ED) intercropping information, therefore, just must do the conversion of voltage between the signal of each unit and its I/O.Please refer to shown in Figure 2ly, it is that signal drives schematic diagram.Show input signal S among the figure
InDriving through core driver 210 and I/O driver 220 becomes output signal S
Out, V
CoreThe power supply of core driver 210 is provided, and V
TtThe power supply of I/O driver 220 then is provided.By in the explanation of Fig. 1 and Fig. 2 as can be known, the substrate plate of existing north bridge chips encapsulating structure is not because of with the isolated from power of the core of each control unit, so the power supply area 160 of core can produce voltage disturbance when the signal of high frequency changes, and thereby interfere with the running of other unit of north bridge chips, cause taking place the possibility of unstable situation.
Summary of the invention
In view of this, the invention provides the substrate plate in a kind of chip-packaging structure and the structure, it can isolate the different electrical power district of substrate plate, to avoid the mutual interference of noise phase, makes chip operation more stable.
For realizing above-mentioned and other purpose, the invention provides a kind of chip-packaging structure, comprise crystal grain and substrate plate.Substrate plate is in order to settling crystal grain and the wire structures of crystal grain is provided, and has a pi type filter, to isolate the different core power supply area of substrate plate.Wherein, substrate plate also comprise the first core power supply area in order to first's circuit power that crystal grain is provided, and in order to the second core power supply area of second portion circuit power that crystal grain is provided.
In the preferred embodiment of the present invention, its pi type filter comprises that an end couples the first core power supply area, and first capacitor of other end ground connection, an end couple the second core power supply area, and second capacitor of other end ground connection and two ends couple the first core power supply area and the second core power supply area respectively, to constitute the inductor of pi type filter.Wherein, the value of first capacitor and second capacitor is 0.1 μ F, and the specification of inductor is when frequency 1.6GHz, and impedance is 100 Ω.
Preferably, this pi type filter also comprises one the 3rd capacitor, and its value is 0.001 μ F, and the one end couples the second source district, and the other end is ground connection then.The position of its configuration is the corner that two limits in the substrate plate connect.
Preferably, this substrate plate also comprises another pi type filter, and the position of its configuration is two corners that the limit connects in addition in the substrate plate.
By in the above-mentioned explanation as can be known, substrate plate in a kind of chip-packaging structure provided by the present invention and the structure, it uses one or two pi type filter to isolate the different electrical power district of substrate plate, to avoid the mutual interference of noise phase, so can make chip operation more stable.
For above and other objects of the present invention, feature and advantage can be become apparent, hereinafter special with preferred embodiment, and cooperate appended graphicly, described in detail.
Description of drawings
Fig. 1 is for showing a kind of substrate plate schematic diagram of existing north bridge chips encapsulating structure;
Fig. 2 drives schematic diagram for showing a kind of signal;
Fig. 3 is the substrate plate schematic diagram of a kind of chip-packaging structure of demonstration preferred embodiment according to the present invention; And
Fig. 4 is for showing the pi type filter icon of the preferred embodiment according to the present invention.
The simple declaration of reference numerals:
100,300 substrate plates
110,310,340,345,350,355,360,365 access areas
120,130,140,150,160 power supply areas
210 core drivers
The 220I/O driver
315,320,325,330,335 power supply areas
372,382 inductors
374,376,378,384,386,388 capacitors
390,395 pi type filters
396,397,398,399 substrate edges of boards
Embodiment
Please refer to shown in Figure 3ly, it is the substrate plate schematic diagram according to a kind of chip-packaging structure of a preferred embodiment of the present invention.This place illustrates be substrate plate 300 in order to paste the one side of crystal grain, wherein for simplicity of illustration makes it more for the purpose of the easy identification, many weld pads that can be connected with wiring pad on the crystal grain with metal wire and the wiring of drawing crystal grain I/O pin are all omitted.In addition, present embodiment is to be example with the crystal grain that cooperates the serial north bridge chips that uses of the K8 of AMD, encapsulating structure then is encapsulated as example with the BGA of wiring connection (wire bond), yet those skilled in the art should understand, and it has other encapsulating structure of similar demand applicable to the encapsulation of different crystal grain.
Because the north bridge chips that cooperates the K8 of AMD series to use can connect central processing unit, Accelerated Graphics Port device and South Bridge chip, therefore, north bridge chips inside just has the central processing unit control unit, Accelerated Graphics Port control unit, and the function square circuit of South Bridge chip control unit several sections such as (not illustrating).And the I/O of north bridge chips for the I/O of the device that is connected between do the transmission of information, therefore, must provide the power supply of these devices on the substrate plate 300 of north bridge chips.
Therefore, its power generation configuration comprises an access area 310 and a plurality of power supply area 315,320,325,330 and 335 as shown in FIG..Wherein access area 310 is commonly used to paste the grounding leg position of crystal grain and connection crystal grain.Power supply area 315 is the power supply (V in order to the I/O part of Accelerated Graphics Port control unit that crystal grain is provided
Cc1) power supply pin, be generally 1.5V voltage.Power supply area 320 is the power supply (V in order to the I/O part of South Bridge chip control unit that crystal grain is provided
Cc2) power supply pin, generally also be 1.5V voltage.Power supply area 325 is the power supply (V in order to the I/O part of central processing unit control unit that crystal grain is provided
Tt) power supply pin, generally also be 1.5V voltage.
In addition, present embodiment will connect the power supply area of power supply pin of each core, unit of crystal grain and divide into the first core power supply area 330 and the second core power supply area, 335 two parts, and its voltage is 2.5V.Wherein, the first core power supply area 330 is the power supply (V in order to the core of central processing unit control unit that crystal grain is provided
Core1) power supply pin.And the second core power supply area 335 is the power supply (V in order to the core of Accelerated Graphics Port control unit that crystal grain is provided and South Bridge chip control unit
Core2) power supply pin.And in order to isolate the noise jamming of 335 of the first core power supply area 330 and the second core power supply areas, to improve the stability of chip operation, two limit 396 and 397 corners that connect of present embodiment in substrate plate 300 dispose a pi type filter 390, and two limits 398 in addition and 399 corners that connect in substrate plate 300 dispose another pi type filter 395.Pi type filter 390 comprises capacitor 374,376 and inductor 372 at least, capacitor 374 is connected between the second core power supply area 335 and the access area 340, capacitor 376 is connected between the first core power supply area 330 and the access area 345, and inductor 372 is connected between the first core power supply area 330 and the second core power supply area 335.In like manner, 395 of pi type filters comprise capacitor 384,386 and inductor 382 at least, capacitor 384 is connected between the second core power supply area 335 and the access area 355, capacitor 386 is connected between the first core power supply area 330 and the access area 360, and inductor 382 is connected between the first core power supply area 330 and the second core power supply area 335.Certainly, in present embodiment, pi type filter 390 and 395 comprises also that respectively a capacitor 378 and 388 is connected between the first core power supply area 330 and the access area 350,365.
Please refer to Fig. 4 now, it is the pi type filter icon of the preferred embodiment according to the present invention, and this pi type filter 390 of sentencing Fig. 3 is example, and its wire structures changed plots general circuit figure, is beneficial to understand its circuit structure.Show among the figure, this pi type filter 390 comprises the capacitor 374,376 and 378 that is distributed in inductor 372 both sides respectively, wherein preferably capacitor 374 and 376 value are 0.1 μ F, the value of capacitor 378 is 0.001 μ F, and the specification of inductor 372 is when frequency 1.6GHz, and impedance is 100 Ω, certainly, those skilled in the art should understand, and it is worthwhile looks different application demand and different variations is arranged.By icon as can be known, as the first core power supply area (V
Core1) or the second core power supply area (V
Core1) when producing the voltage disturbance of high frequency, inductor 372 all can effectively prevent the voltage disturbance of another core power supply area.
By in the above-mentioned explanation as can be known, for the more and more complicated semiconductor application circuit of function, will inevitably increase its power consumption, make the noise jamming source that produces also increase thereupon.At this moment, as use substrate plate in a kind of chip-packaging structure of the present invention and the structure, effectively the noise isolation interference source makes chip operation more tend towards stability.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (10)
1. the substrate plate of a chip-packaging structure is applicable to encapsulation one crystal grain, it is characterized in that, comprising:
One first core power supply area is in order to provide first's circuit power of this crystal grain;
One second core power supply area, in order to a second portion circuit power of this crystal grain to be provided, wherein this first core power supply area and this second core power supply area have an identical voltage; And
One pi type filter couples between this first power supply area and this second source district.
2. the substrate plate of chip-packaging structure as claimed in claim 1, it is characterized in that: this pi type filter comprises:
One first capacitor, an end couple this first core power supply area, and other end ground connection;
One second capacitor, an end couple this second core power supply area, and other end ground connection; And
One inductor, two ends couple the first core power supply area and this second core power supply area respectively, to constitute this pi type filter.
3. the substrate plate of chip-packaging structure as claimed in claim 2, it is characterized in that: also comprise one the 3rd capacitor, an end of the 3rd capacitor couples this second core power supply area, and the other end is ground connection then.
4. a chip-packaging structure is characterized in that, comprising:
One crystal grain; And
One substrate plate in order to settling this crystal grain and the wire structures of this crystal grain is provided, and has a pi type filter, to isolate the different core power supply area of this substrate plate.
5. chip-packaging structure as claimed in claim 4 is characterized in that: this substrate plate also comprises:
One first core power supply area is in order to provide first's circuit power of this crystal grain; And
One second core power supply area, in order to a second portion circuit power of this crystal grain to be provided,
Wherein, this first core power supply area and this second core power supply area have an identical voltage.
6. chip-packaging structure as claimed in claim 5 is characterized in that: this pi type filter comprises:
One first capacitor, an end couple this first core power supply area, and other end ground connection;
One second capacitor, an end couple this second core power supply area, and other end ground connection; And
One inductor, two ends couple this first core power supply area and this second core power supply area respectively.
7. chip-packaging structure as claimed in claim 6 is characterized in that: also comprise one the 3rd capacitor, an end of the 3rd capacitor couples this second core power supply area, and the other end is ground connection then.
8. the substrate plate of a chip-packaging structure is applicable to encapsulation one crystal grain, it is characterized in that, comprising:
One first core power supply area is in order to provide first's circuit power of this crystal grain;
One second core power supply area, in order to a second portion circuit power of this crystal grain to be provided, wherein this first core power supply area and this second core power supply area have an identical voltage; And
At least one inductor couples between this first power supply area and this second source district.
9. the substrate plate of chip-packaging structure as claimed in claim 8 is characterized in that, also comprises:
One first capacitor, an end couple this first core power supply area, and other end ground connection; And
One second capacitor, an end couple this second core power supply area, and other end ground connection.
10. the substrate plate of chip-packaging structure as claimed in claim 9, it is characterized in that: also comprise one the 3rd capacitor, an end of the 3rd capacitor couples this second core power supply area, and the other end is ground connection then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021232326A CN1180474C (en) | 2002-06-13 | 2002-06-13 | Chip package structre and its substrate board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021232326A CN1180474C (en) | 2002-06-13 | 2002-06-13 | Chip package structre and its substrate board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1389912A true CN1389912A (en) | 2003-01-08 |
| CN1180474C CN1180474C (en) | 2004-12-15 |
Family
ID=4745115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021232326A Expired - Lifetime CN1180474C (en) | 2002-06-13 | 2002-06-13 | Chip package structre and its substrate board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1180474C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320651C (en) * | 2004-11-03 | 2007-06-06 | 北京中星微电子有限公司 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
| CN101814458B (en) * | 2004-12-03 | 2012-05-30 | 罗姆股份有限公司 | Semiconductor device |
| US10845853B2 (en) | 2018-02-01 | 2020-11-24 | Delta Electronics (Shanghai) Co., Ltd | System of providing power to chip on mainboard |
| US11271396B2 (en) | 2018-02-01 | 2022-03-08 | Delta Electronics (Shanghai) Co., Ltd. | System of providing power to chip on mainboard |
-
2002
- 2002-06-13 CN CNB021232326A patent/CN1180474C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320651C (en) * | 2004-11-03 | 2007-06-06 | 北京中星微电子有限公司 | Chip with a plurality of internal functional blocks and method for power supply and noise reduction |
| CN101814458B (en) * | 2004-12-03 | 2012-05-30 | 罗姆股份有限公司 | Semiconductor device |
| US10845853B2 (en) | 2018-02-01 | 2020-11-24 | Delta Electronics (Shanghai) Co., Ltd | System of providing power to chip on mainboard |
| US11271396B2 (en) | 2018-02-01 | 2022-03-08 | Delta Electronics (Shanghai) Co., Ltd. | System of providing power to chip on mainboard |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1180474C (en) | 2004-12-15 |
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Granted publication date: 20041215 |
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| CX01 | Expiry of patent term |