CN1316693A - Adder and its implementation method - Google Patents

Abstract

A WLX adder is disclosed, which uses the halving principle for grouping. In order to improve the parallelism of sum calculation and carry calculatino, the sum predication for each small adder unit and the in-advance carry technique for the carry of each small adder unit are utilized. A reverse logic method is used for circuit design.

Description

Totalizer and its implementation

The present invention relates to the binary data adder operation circuit in the computer logic circuit design field, more particularly, relate to a kind of totalizer and its implementation.

In computer system, additive operation is the core of all arithmetical operations.Therefore the speed that how to improve additive operation is the target of the common pursuit of insider institute.

Initial computing machine all adopts ripple carry adder (ripple-carryaddition).For this totalizer i position and S _iFor

S _i＝A _iB _iC _i

A wherein _iAnd B _iBe respectively the i position of two operands, C _iIt is carry to the i position.The carry of next stage (i+1) position is

C _i+1＝A _i·B _i+C _i·(A _i+B _i)

Therefore the time-delay of a n-1 carry time-delay of the operand addition maximum demand of two n positions and a summation.This obviously can not satisfy the high-speed demand of computer nowadays computing.To the updating of totalizer, the totalizer after improving at present mainly contains two classes through for many years, and a class is asynchronous totalizer, and another kind of is the synchronous addition device.Totalizer in current most computer system has all adopted the latter.Though the kind of synchronous addition device is a lot, all have and come from different separately design philosophys and formed different circuit structures, but their common feature, it all is the cascaded carry that overcomes ripple carry adder, increase summation and the degree of parallelism of asking carry, the time-delay of wait carry when suing for peace, thereby the execution speed of raising totalizer to reduce as far as possible.But their common drawback is still can not satisfy the requirement that improves constantly that arithmetic speed is proposed.

The totalizer that the purpose of this invention is to provide a kind of high speed is to improve the arithmetic speed of computer system.

Another object of the present invention provides a kind of grouping scheme that realizes the additive operation of long number, makes the circuit scale of totalizer of multidigit reduce greatly, thereby improves the speed of additive operation.

The present invention has disclosed a kind of method of utilizing antilogical to carry out Logic Circuit Design, not only can improve the execution speed of circuit, can also reduce circuit scale.

Another object of the present invention is to have proposed a kind of summation and method of asking the degree of parallelism of carry of improving, and promptly adopts the carry lookahead technology between employing and number forecasting techniques, group in the group.

To achieve these goals, the invention provides a kind of device and its implementation that realizes the multidigit additive operation, wherein:

Adopt the dichotomy back of dividing into groups to form the adder unit of minimum to the totalizer of n position, each adder unit receives two operand and the required carry signals of this adder unit of adder unit same bit-width therewith, and local carry signal and the carry with the counting with this adder unit that produce a same bit-width are transmitted signal;

Receive local carry signal and carry transmission signal that all adder units produce, produce the carry generation device-carry chain of the required carry signal of each adder unit;

Carry out the method for dichotomy grouping at the totalizer of n position;

Utilize the reverse logic method for designing of reverse swing door circuit;

For in the group that is adopted that improves summation and the degree of parallelism of asking carry and the number prediction, organize between the method for carry lookahead.

Technique effect of the present invention is: totalizer of the present invention belongs to a kind of of synchronous addition device, and it has abandoned the packet mode of conventional synchronous addition device, has proposed a kind of group technology that adopts the dichotomy principle.Increase summation aspect the degree of parallelism of asking carry, after grouping, adopting in formed each little adder unit and the number forecasting techniques, adopting the carry lookahead technology during carry between each little adder unit of generation.On method for designing, changed traditional formed positive logic circuit design method of forward logical thinking mode, and adopted the circuit design method of reverse logic.

Fig. 1 is the one-piece construction figure of totalizer of the present invention;

Fig. 2 is the circuit diagram of 4 adder units;

Fig. 3 is the circuit diagram with the carry lookahead chain of 5 adder units.

With reference to the accompanying drawings a most preferred embodiment of the present invention is described in detail.

In order further to improve the speed of totalizer, we have proposed a kind of geometric series hierarchical grouping scheme is dichotomy grouping scheme.With the n position minimum half The position form one group, successively again with The position is formed one group, with Form one group etc.This is the ground floor grouping.Each group more according to this rule be divided into the plurality of sub group, by that analogy, every group or son group are all assigned to till 2.Scheme can be extrapolated total number of circuit and is according to this:

f(n)＝2nlog ₂(2n)+3log ₂n+6。

This is the minimum grouping schemes of our resulting used door numbers.

With regard to Project Realization, reverse gate circuit always lacks than fast, the used pipe of the gate speed of forward.According to this characteristic, we change traditional forward logical thinking mode, adopt reverse logic, realize totalizer with reverse gate circuit.

We are that example describes totalizer of the present invention in detail with 4 one group.

Fig. 1 is one-piece construction figure of the present invention.This device can be finished the additive operation of two n figure places.

A＜0:n-1 among Fig. 1 〉, B＜0:n-1 be the binary number of two n positions.

S＜0:n-1 among Fig. 1〉be A＜0:n-1+B＜0:n-1 and.

ADDER among Fig. 1 ₀, ADDER ₁..., ADDER _mBe 4 adder units that divide into groups by two separating methods.

Each adder unit all is identical.Arbitrary adder unit ADDER _iReceive two bit wides and be operand A＜i of 4, i+3 〉, B＜i, i+3 〉, and the required carry signal C of this adder unit _i, by logical operation produce a bit wide be 4 with number S＜i, i+3 and the local carry signal G of this adder unit _iTransmit signal T with carry _i

ADDER among Fig. 1 ₀It is first adder unit of n position totalizer, therefore its front can not produce carry, owing to use reverse carry signal in our adder unit, so NC0 connects high level, certainly if use the carry signal of forward in the adder unit, C0 will connect low level.And its carry transmission signal need not be input among the CLAL yet and go.

ADDER among Fig. 1 _mBe last adder unit of n position totalizer, so the local carry signal NGm that it produced and carry are transmitted signal and are not all needed to be input among the CLAL to go.

The carry lookahead chain of CLAL among Fig. 1 for dividing into groups by two separating methods.CLAL receives the local carry signal G that all adder units produce _iTransmit signal T with carry _i, produce the required carry signal C of each adder unit by logical operation _i

Fig. 2 is the circuit of adder unit of the present invention 4.

In adder unit,, adopted and the number forecasting techniques in order to improve summation and the degree of parallelism of asking carry.With the principle mainly followed of number forecasting techniquess be: produce when each sue for peace two and value, one (thinking that carry is 1) for add carry, another is (the thinking that carry is 0) of add carry not.Each final value is selected according to the carry of reality.

X among Fig. 2 ₀Be 4 group first of the first operand of additive operation; X ₁Be 4 one group of the first operand of additive operation second; X ₂Be 4 group the 3rd of the first operand of additive operation; X ₃Be 4 group the 4th of the first operand of additive operation.

Y among Fig. 2 ₀Be 4 group first of the second operand of additive operation; Y ₁Be 4 one group of the second operand of additive operation second; Y ₂Be 4 group the 3rd of the second operand of additive operation; Y ₃Be 4 group the 4th of the second operand of additive operation.

NC among Fig. 2 ₀The reverse signal of the carry of adder unit for this reason.

Among Fig. 2

Be NC ₀=0 X ₀+ Y ₀And oppositely:

Be NC ₀=1 X ₀+ Y ₀And oppositely.

Among Fig. 2

Be NC ₀=0 X ₁+ Y ₁And oppositely:

Be NC ₀=1 X ₁+ Y ₁And oppositely.

Among Fig. 2

Be NC ₀=0 X ₂+ Y ₂And oppositely:

Be NC ₀=1 X ₂+ Y ₂And oppositely.

Among Fig. 2

Be NC ₀=0 X ₃+ Y ₃And oppositely: Be NC ₀=1 X ₃+ Y ₃And oppositely.

G ' among Fig. 2 _EBe NC ₀=0 X ₀X ₁With Y ₀Y ₁The carry that addition produced; G ' _NBe NC ₀=1 X ₀X ₁With Y ₀Y ₁The carry that addition produced;

S among Fig. 2 ₀Be X ₀+ Y ₀Real and; S ₁Be X ₁+ Y ₁Real and; S ₂Be X ₂+ Y ₂Real and; S ₃Be X ₀+ Y ₀Real and.

Realize that in order further to be convenient to hardware of the present invention we carry out logical derivation to adder unit circuit of the present invention.

Concerning first, because C ₀The carry that is exactly this can be expressed with following formula, and circuit is simplified more.

S ₀＝X ₀Y ₀C ₀ $=\stackrel{\‾}{\stackrel{\‾}{X_0{\⊕Y}_0{\⊕C}_0}}$ $=\stackrel{\‾}{\stackrel{\‾}{X_0\⊕Y_0}\⊕C_0}$ $=\stackrel{\‾}{X_0\⊕Y_0}\⊕{\stackrel{-}{C}}_0$

S _N1＝X ₁Y ₁C _N1

＝X ₁Y ₁(X ₀·Y ₀) $=\stackrel{\‾}{\stackrel{\‾}{X_1{\⊕Y}_1\⊕\left(X_0{\·Y}_0\right)}}$ $=\stackrel{\‾}{\stackrel{\‾}{X_1\⊕Y_1}\⊕\left(X_0{\·Y}_0\right)}$ $=\stackrel{\‾}{X_1{\⊕Y}_1}\⊕\stackrel{\‾}{X_0{\·Y}_0}$ $\stackrel{\‾}{S_{N1}}=\stackrel{\‾}{\stackrel{\‾}{X_1{\⊕Y}_1}\⊕{\stackrel{\‾}{X_0\·Y}}_0}$

S _E1＝X ₁Y ₁C _E1

＝X ₁Y ₁(X ₀+Y ₀) $=\stackrel{\‾}{\stackrel{\‾}{X_1{\⊕Y}_1\⊕\left(X_0{+Y}_0\right)}}$ $=\stackrel{\‾}{\stackrel{\‾}{X_1{\⊕Y}_1}\⊕\left(X_0{+Y}_0\right)}$ $=\stackrel{\‾}{X_1\⊕Y_1}\⊕\stackrel{\‾}{X_0+Y_0}$ $\stackrel{\‾}{S_{E1}}=\stackrel{\‾}{\stackrel{\‾}{X_1{\⊕Y}_1}\⊕{\stackrel{\‾}{X_0+Y}}_0}$

According to the carry of low group, select last S as a result to this group ₁S ₁Can select 1 gate MUX21_1L to finish with 2 of one one reverse output.The function of MUX21_1L is, when control signal is 1, and the input on the gating left side, and to its reverse output; When control signal is 0, the input on gating the right, and to its reverse output.With the gating of low group to the carry signal control MUX21_1L of this group, this carry signal can be adjusted the MUX21_1L input according to signal forward or reverse that carry chain produces with minimum progression.If being the left side of the then MUX21_1L of forward, the carry signal that produces is input as S _N1, the right be input as S _E1If being the left side of reverse then MUX21_1L, the carry signal that produces is input as S _E1, the right be input as S _N1For S ₂, S ₃It all is same reason.In Fig. 2-3, we are example with reverse carry signal.

Owing to adopt two one roped parties, therefore will produce and hang down two to high two carry signal G ' _NAnd G ' _E

G’ _E＝G ₁+T ₁·G _E0

＝X ₁·Y ₁+(X ₁+Y ₁)·(X ₀+Y ₀) $=\stackrel{\‾}{\stackrel{\‾}{X_1{\·Y}_1+(X_1+Y_1)\·(X_0+Y_0)}}$ $=\stackrel{\‾}{\stackrel{\‾}{X_1{\·Y}_1}\·({\stackrel{\‾}{X_1+Y}}_1+{\stackrel{\‾}{X_0+Y}}_0)}$ $=\stackrel{\‾}{\stackrel{\‾}{X_1{\·Y}_1}\·(\stackrel{\‾}{X_1\⊕Y_1}+\stackrel{\‾}{X_0+Y_0})}$

G’ _N＝G ₁+T ₁·G _N0

＝X ₁·Y ₁+(X ₁+Y ₁)·X ₀·Y ₀ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_1\&CenterDot;Y_1\left(X_1{+Y}_1\right)\&CenterDot;X_0\&CenterDot;Y_0}}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_1\&CenterDot;Y_1}\&CenterDot;({\stackrel{\&OverBar;}{X_1+Y}}_1+{\stackrel{\&OverBar;}{X_0\&CenterDot;Y}}_0)}$ Because with this understanding, $\stackrel{\&OverBar;}{X_1+Y_1}=\stackrel{\&OverBar;}{X_1{\&CirclePlus;Y}_1},$ Therefore can $\stackrel{\&OverBar;}{X_1{\&CirclePlus;Y}_1}$ Substitute $\stackrel{\&OverBar;}{X_1+Y_1}.$ ${G^{,}}_N=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_1\&CenterDot;Y_1}\&CenterDot;(\stackrel{\&OverBar;}{X_1{\&CirclePlus;Y}_1}+\stackrel{\&OverBar;}{X_0\&CenterDot;Y_0})}$ S _N2＝X ₂Y ₂G’ _N $\stackrel{\&OverBar;}{S_{N2}}=\stackrel{\&OverBar;}{X_1\&CirclePlus;Y_2}\&CirclePlus;{G^{,}}_N$ S _E2＝X ₂Y ₂G’ _E $\stackrel{\&OverBar;}{S_{E2}}=\stackrel{\&OverBar;}{X_2\&CirclePlus;Y_2}\&CirclePlus;{G^{,}}_E$ S _N3=X ₃ Y ₃ C _N3=X ₃ Y ₃ (X ₂Y ₂+ T ₂G ' _N)=X ₃ Y ₃ (X ₂Y ₂+ (X ₂+ Y ₂) G ' _N) because with this understanding, X ₂+ Y ₂=X ₂ Y ₂But, so X ₂ Y ₂Substitute X ₂+ Y ₂S _N3=X ₃ Y ₃ (X ₂Y ₂+ (X ₂ Y ₂) G ' _N) $\stackrel{\&OverBar;}{S_{N3}}=X_3\&CirclePlus;Y_3\&CirclePlus;\stackrel{\&OverBar;}{X_2\&CenterDot;Y_2+(X_2\&CirclePlus;Y_2){\&CenterDot;G^{,}}_N}$ S _N3=X ₃ Y ₃ C _E3=X ₃ Y ₃ (X ₂Y ₂+ T ₂G ' _E)=X ₃ Y ₃ (X ₂Y ₂+ (X ₂+ Y ₂) G ' _E) because with this understanding, X ₂+ Y ₂=X ₂ Y ₂But, so X ₂ Y ₂Substitute X ₂+ Y ₂S _E3=X ₃ Y ₃ (X ₂Y ₂+ (X ₂ Y ₂) G ' _E $\stackrel{\&OverBar;}{S_{E3}}=X_3{\&CirclePlus;Y}_3\&CirclePlus;\stackrel{\&OverBar;}{X_2{\&CenterDot;Y}_2+\left(X_2{\&CirclePlus;Y}_2\right){{\&CenterDot;G}^{,}}_E}$ Four one group local carry signal is G.G＝X ₃·Y ₃+(X ₃+Y ₃)·X ₂·Y ₂+(X ₃+Y ₃)·(X ₂+Y ₂)·G’ _N $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3\&CenterDot;Y_3+(X_3+Y_3){\&CenterDot;X}_2\&CenterDot;Y_2+(X_3+Y_3)\&CenterDot;(X_2+Y_2){{\&CenterDot;G}^{,}}_N}}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3\&CenterDot;Y_3}\&CenterDot;(\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2\&CenterDot;Y_2})\&CenterDot;(\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2+Y_2}+\stackrel{\&OverBar;}{{G^{,}}_N})}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3\&CenterDot;Y_3}\&CenterDot;(\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2\&CenterDot;Y_2})}+\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2+Y_2}+\stackrel{\&OverBar;}{{G^{,}}_N}}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3\&CenterDot;Y_3}\&CenterDot;(\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2\&CenterDot;Y_2})}+\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2+Y_2}}\&CenterDot;{G^{,}}_N$ $\stackrel{-}{G}=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3{\&CenterDot;Y}_3}\&CenterDot;(\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2{\&CenterDot;Y}_2})}+\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_3+Y_3}+\stackrel{\&OverBar;}{X_2+Y_2}}\&CenterDot;{G^{,}}_N}$ Same using $\stackrel{\&OverBar;}{X_3\&CirclePlus;Y_3}$ Replace $\stackrel{\&OverBar;}{X_3+Y_3;}$ With $\stackrel{\&OverBar;}{X_2\&CirclePlus;Y_2}$ Replace $\stackrel{\&OverBar;}{X_2+Y_2.}$ $\stackrel{-}{G}=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3{\&CenterDot;\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}\&CenterDot;(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3\&CirclePlus;{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2{\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2})}+\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3\&CirclePlus;{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}}\&CenterDot;{G^{\&prime;}}_N}$ It is T that signal is transmitted in this locality of four one group.T＝(X ₀+Y ₀)·(X ₁+Y ₁)·(X ₂+Y ₂)·(X ₃+Y ₃) $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{(X_0+Y_0)\&CenterDot;(X_1+Y_1)\&CenterDot;({\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2+Y_2)\&CenterDot;({\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3+Y_3)}}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_0+Y_0}+\stackrel{\&OverBar;}{X_1+Y_1}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3+{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}}$ $=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_0+Y_0}+\stackrel{\&OverBar;}{X_1+Y_1}\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3+{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}}$ $\stackrel{-}{T}=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_0+Y_0}+\stackrel{\&OverBar;}{X_1+Y_1}}+\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3+{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}}}$

Same using $\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3{\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}$ Replace $\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3+{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3};$ With $\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2{\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}$ Replace $\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2};$ With $\stackrel{\&OverBar;}{X_1{\&CirclePlus;Y}_1}$ Replace $\stackrel{\&OverBar;}{X_1+Y_1};$ With $\stackrel{\&OverBar;}{X_0{\&CirclePlus;Y}_0}$ Replace $\stackrel{\&OverBar;}{X_0+Y_0}$ $\stackrel{-}{T}=\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{X_0\&CirclePlus;Y_0}+\stackrel{\&OverBar;}{X_1\&CirclePlus;Y_1}}\&CenterDot;\stackrel{\&OverBar;}{\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_2\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A0010495900121.png,A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}+\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="3"\; label="X"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">X</figure-callout>}}_3\&CirclePlus;{\mathrm{<figure-callout\; id="3"\; label="Y"\; filenames="A0010495900131.png"\; state="\{\{state\}\}">Y</figure-callout>}}_3}}}$

Fig. 3 is the carry lookahead chain of 5 groups of totalizers.Among the figure,

NG0 is the reverse local carry signal that ADDER0 produces.

NG1 is the reverse local carry signal that ADDER1 produces.

NT1 is that the reverse carry that ADDER1 produces is transmitted signal.

NG2 is the reverse local carry signal that ADDER2 produces.

NT2 is that the reverse carry that ADDER2 produces is transmitted signal.

NG3 is the reverse local carry signal that ADDER3 produces.

NT3 is that the reverse carry that ADDER3 produces is transmitted signal.

NC1 is the needed reverse carry signal of ADDER1.

NC2 is the needed reverse carry signal of ADDER2.

NC3 is the needed reverse carry signal of ADDER3.

NC4 is the needed reverse carry signal of ADDER4.

Abovely the present invention is described in detail according to a specific embodiment.Yet the skilled person in the present technique field is easy to find out, under the prerequisite that does not deviate from spirit of the present invention, also can make various changes and modifications to the present invention.The applicant thinks that these modification, modification also all fall within the defined scope of following claim.

Claims (6)

1. totalizer comprises:

A plurality of additive operations unit (ADDER0～ADDERm);

Two data lines (A, B);

A CLAL;

It is characterized in that:

Above-mentioned a plurality of additive operations unit is divided into some groups by geometric series hierarchical grouping scheme; Each group is divided into the plurality of sub group by above-mentioned rule again, all assigns to 2 for extremely up to every group or each group.

2. totalizer as claimed in claim 1, its feature also is: in the little adder unit of each that forms after grouping, to predicting with number.

3. totalizer as claimed in claim 1, its feature also is: what adopt when the carry that produces between each little adder unit is carry lookahead.

4. group technology that realizes the additive operation of long number is characterized in that:

N adder unit by the geometric series hierarchical grouping, promptly formed one group with minimum half n/2 position, form one group with n/4 again, form one group with n/8 again, the rest may be inferred;

Each group is divided into the plurality of sub group by above-mentioned rule again, all assigns to 2 for extremely up to every group or each group.

5. a logic circuit design method is characterized in that: adopt reverse gate circuit to constitute totalizer.

6. a method that improves summation and ask the degree of parallelism of carry is characterized in that: adopt in the totalizer grouping and the number prediction, adopt carry lookahead between group.

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