CN108898228B - Quantum adder design method without damaging source operands - Google Patents
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Abstract
The invention provides a quantum adder design method without damaging a source operand, and belongs to the field of quantum circuit design. The invention designs 6 basic quantum gates which are convenient for parallel calculation, then designs a quantum half adder, a quantum full adder and a corresponding reset device on the basis, and a design method of an n-bit non-destructive source operand adder which is formed by the quantum half adder, the quantum full adder and the corresponding reset device. The invention has the advantages that the reset device is designed, so that the source operand participating in operation is not destroyed, and the high efficiency of quantum information processing in signal processing is reflected at the same time: only 12n-3 basic operations are needed to implement n-bit integer addition operations, while the time complexity is only 6n+3.
Description
Technical Field
The invention relates to the field of quantum circuit design, in particular to a quantum adder design method without damaging source operands.
Background
The quantum computer has unique data processing capability, can solve mathematical problems which are difficult to solve by the traditional computer, such as large-number prime factor decomposition and discrete logarithm solution, and therefore, becomes a strategic competitive focus of all countries in the world. Adders are an important component of quantum computers, unlike classical computing, which have unclonable properties, so it is valuable to study adders that do not destroy source operands.
In quantum computing, an information element is represented by a qubit, which has two basic quantum states |0> and |1>, the basic quantum states being abbreviated as ground states. One qubit may be a linear combination of two ground states, often referred to as an overlap state, and may be expressed as |ψ > = a|0> +b|1>, where a and b are two complex numbers.
Tensor product is a method of grouping together small vector spaces to form a larger vector space, symbolicallyAnd (3) representing. For two ground states |u>And |v>Tensor product of them->Common abbreviation |uv>，|u>|v>Or |u, v>Representation, e.g. for ground state |0>And |1>Their tensor product can be expressed as
For n tensor products of matrix UCan be abbreviated as->For quantum state |u>Tensor product of n times (n times)Can also be abbreviated as->
The quantum circuit may be composed of a sequence of quantum bit gates, each line representing a connection of the quantum circuit in the representation of the quantum circuit, the execution order of the quantum circuit being from left to right. The qubit gates may conveniently be represented in a matrix form. The quantum gate of n quantum bits can be 2 n ×2 n Is represented by unitary matrix U, i.eWherein U is + Is the conjugate transpose of U, I is the unit matrix,>is the n tensor product of I. X (NOT gate), V and V + Is a single qubit gate commonly used in three types, and their matrix representation is:
where i is an imaginary unit.
The most important multiple quantum bit gate is the controlled U gate, represented by the control quantum bit and the target quantum bit, represented by black dots when the control bit is 1, and represented by white dots when the control bit is 0. When u=x, V + The controlled U gates are respectively called controlled NOT gates, controlled V gates and controlled V + Gates, their symbology is shown in FIG. 1.
An important performance index of a quantum wire is the complexity of the wire. The complexity of the line is divided into quantum cost complexity and quantum time complexity. Controlled NOT gate, controlled V + Both the quantum cost and the run-time complexity of the gate are 1. The quantum cost of the quantum circuit refers to a controlled NOT gate, a controlled V gate and a controlled V in the circuit + Total number of gates. The time complexity of a quantum wire is the total time of the quantum gates in a parallel running wire.
Disclosure of Invention
The invention provides a quantum adder without damaging source operands, which comprises a design method for designing 6 basic quantum gates which are convenient for parallel calculation, then designing a quantum half adder, a quantum full adder and a corresponding reset device on the basis, and forming an n-bit adder without damaging the source operands by the quantum half adder, the quantum full adder and the corresponding reset device, thereby realizing the high efficiency of quantum information processing in signal processing: only 12n-3 basic operations are needed to implement the n-bit integer addition operation.
The technical scheme of the invention is as follows:
the invention utilizes three basic quantum controlled gates (namely, controlled NOT gate, controlled V gate and controlled quantum full adder V + Gates) to build up an implementation line that does not destroy the source operands.
The specific design scheme and steps of the invention are as follows:
1. the specific process of designing the 6 basic quantum gates is as follows:
realizing 6 basic quantum gate design circuits by 3 controlled gates, respectively using symbol P 1 、P 2 、P 3 、P 4 、P 5 And P 6 The quantum cost and quantum time complexity of the 6 basic quantum gate design circuits are 3, and the structures are respectively as follows: basic door P 1 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 2 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 3-quantum bit connecting line; basic door P 3 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 4 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 5 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 4-qubit connecting line; basic door P 6 The device consists of 2 controlled V gates, a controlled NOT gate and a 4-quantum bit connecting line;
2. quantum half adder and reset design
With controlled V-gate, basic gate P 2 Implementation of the Quantum half-adder design Circuit in FIG. 3, symbolized by A 1 And (3) representing.
Application of quantum half adder to quantum state |0>|b 0 >|a 0 >Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}. From equation (1), it can be seen that the quantum half adder realizes addition (b 0 +a 0 ) In which the first qubit of the output is |a 0 b 0 >Storage addition (b) 0 +a 0 ) Carry information of (2) output second quantum bitStored is the sum of the additions.
In order not to destroy the source operands, a reset of the quantum half adder as in FIG. 4 is designed, consisting of a controlled V gate and a basic gate P 3 Is formed by the symbol R 1 And (3) representing.
Application of a reset of a quantum half adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}. From equation (2), it can be known that the resetter of the quantum half adder willReset to |b 0 >|a 0 >。
And analyzing the quantum circuit to obtain the quantum cost and the time complexity of the quantum half adder and the corresponding resetter which are both 4.
3. Quantum full adder and reset design
By means of basic gates P 1 And P 5 Realizing quantum full adder design circuit by symbol A 2 And (3) representing.
Application of quantum full adder to quantum state |0>|b i >|a i >|c i -1>Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i -1 e {0,1}. From equation (3), it can be seen that the quantum full adder realizes addition (b i +a i +c i -1) wherein the first qubit of the output +.>Storage addition (b) i +a i +c i-1 ) Carry information of (2), second qubit of output +.>Stored is the sum of the additions.
In order not to destroy the source operands, a reset of the quantum full adder as in FIG. 6 is designed, which consists of a basic gate P 3 And P 6 Composition, denoted by the symbol R 2 And (3) representing.
Application of a reset of a quantum full adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i-1 E {0,1}. From equation (4), it can be seen that the resetter of the quantum full adder willReset to |b i >。
And analyzing the quantum circuit to obtain the quantum cost and the time complexity of the quantum full adder and the resetter of 6.
4. n-qubit design without destroying source operand adder
Implementing the quantum adder design circuit of FIG. 7 with n-qubits without destroying source operands using quantum half adder, quantum full adder and corresponding resetter, with symbol A D And (3) representing. The quantum adder with n quantum bits not damaging the source operand is composed of (n-1) quantum full adder and reset device (which can be decomposed into n-1 basic gates P 1 、P 5 、P 6 And P 3 ) The device comprises 1 quantum half adder, a resetter of the 1 quantum half adder and a controlled NOT gate. It implements two n-bit addition operations that do not destroy the source operand.
It is assumed that integers a and b of n bits are stored in the ground states of two n qubits:
wherein a is n-1 a n-2 ...a 0 And b n-1 b n-2 ...b 0 Binary representations of integers a and b, respectively, a h ,b h ∈{0,1},h＝0,...,n-1。
Quantum ground state added with n quantum bitsThe auxiliary bit of the most addition operation and the row order obtain |00b n- 1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >As input. Applying adder to |00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >Obtaining
A D ||00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >＝|s n s n-1 b n-1 a n-1 s n-2 b n-2 a n-2 ...s 0 b 0 a 0 > (6)
Wherein s=a+b, s n s n-1 s n-2 ...s 0 Is a binary representation of the integer s, s h ∈{0,1},h＝0,...,n。
As can be seen from the formula (6), the adder implements the following addition operation:
analyzing the quantum circuit to obtain the adder which can realize n-bit integer and does not damage the source operand, wherein the quantum cost of the adder is 6 (n-1) +6 (n-1) +2×4+1=12n-3, n is more than or equal to 2, (n-1) basic gates P 1 And a basic gate P 2 Running in parallel, (n-1) basic gates P 3 And a basic gate P 4 And the parallel operation is performed, so that the line time complexity is 3 (n-1) +3 (n-1) +2×4+1=6n+3, and n is more than or equal to 2, which fully reflects the high efficiency of the addition line designed by the patent.
The invention has the advantages and effects that:
the invention solves the problem of 'quantum addition operation without destroying source operands', and designs a quantum adder without destroying source operands. The invention has the advantages that the reset device is designed, so that the source operand participating in operation is not destroyed, and the high efficiency of quantum information processing in signal processing is reflected at the same time: only 12n-3 basic operations are needed to implement n-bit integer addition operations, while the time complexity is only 6n+3.
Drawings
FIG. 1 is a name and symbol representation of a qubit gate of the present invention;
FIG. 2 is a circuit diagram and corresponding schematic diagram of 6 basic gates of the present invention;
FIG. 3 is a diagram of a quantum implementation circuit of the quantum half adder of the present invention;
FIG. 4 is a diagram of a quantum implementation circuit of a reset of the quantum half-adder of the present invention;
FIG. 5 is a diagram of a quantum implementation circuit of the quantum full adder of the present invention;
FIG. 6 is a diagram of a quantum implementation circuit of a reset of the quantum full adder of the present invention;
FIG. 7 is a diagram of a quantum implementation circuit of a source operand quantum adder of the present invention;
FIG. 8 is a diagram of a quantum implementation of an example of a source operand quantum addition operation that is not disrupted in accordance with the present invention.
Detailed Description
The invention is further illustrated by the following examples.
As shown in fig. 1-8, the specific process is as follows,
1. the specific process of designing the 6 basic quantum gates is as follows:
realizing 6 basic quantum gate design circuits by 3 controlled gates, respectively using symbol P 1 、P 2 、P 3 、P 4 、P 5 And P 6 The quantum cost and quantum time complexity of the 6 basic quantum gate design circuits are 3, and the structures are respectively as follows: basic door P 1 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 2 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 3-quantum bit connecting line; basic door P 3 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 4 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 5 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 4-qubit connecting line; basic door P 6 The device consists of 2 controlled V gates, a controlled NOT gate and a 4-quantum bit connecting line;
2. quantum half adder and reset design
With controlled V-gate, basic gate P 2 Implementation of the Quantum half-adder design Circuit in FIG. 3, symbolized by A 1 And (3) representing.
Application of quantum half adder to quantum state |0>|b 0 >|a 0 >Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}. From equation (1), it can be seen that the quantum half adder realizes addition (b 0 +a 0 ) In which the first qubit of the output is |a 0 b 0 >Storage addition (b) 0 +a 0 ) Carry information of (2) output second quantum bitStored is the sum of the additions.
In order not to destroy the source operands, a reset of the quantum half adder as in FIG. 4 is designed, consisting of a controlled V gate and a basic gate P 3 Is formed by the symbol R 1 And (3) representing.
Application of a reset of a quantum half adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}. From equation (2), it can be known that the resetter of the quantum half adder willReset to |b 0 >|a 0 >。
Analysis of the quantum circuits of fig. 3 and 4 results in a quantum half adder and corresponding resetter with a quantum cost and time complexity of 4.
3. Quantum full adder and reset design
By means of basic gates P 1 And P 5 Implementing the quantum full adder design circuit of FIG. 5, symbolized by A 2 And (3) representing.
Application of quantum full adder to quantum state |0>|b i >|a i >|c i-1 >Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i-1 E {0,1}. From equation (3), it can be seen that the quantum full adder realizes addition (b i +a i +c i-1 ) Wherein the first qubit of the output +.>Storage addition (b) i +a i +c i-1 ) Carry information of (2), second qubit of output +.>Stored is the sum of the additions.
In order not to destroy the source operands, a reset of the quantum full adder as in FIG. 6 is designed, which consists of a basic gate P 3 And P 6 Composition, denoted by the symbol R 2 And (3) representing.
Application of a reset of a quantum full adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i-1 E {0,1}. From equation (4), it can be seen that the resetter of the quantum full adder willReset to |b i >。
Analysis of the quantum circuits of fig. 5 and 6 yields a quantum cost and time complexity of 6 for the quantum full adder and resetter.
4. n-qubit design without destroying source operand adder
Implementing the quantum adder design circuit of FIG. 7 with n-qubits without destroying source operands using quantum half adder, quantum full adder and corresponding resetter, with symbol A D And (3) representing. The quantum adder with n quantum bits not damaging the source operand is composed of (n-1) quantum full adder and reset device (which can be decomposed into n-1 basic gates P 1 、P 5 、P 6 And P 3 ) The device comprises 1 quantum half adder, a resetter of the 1 quantum half adder and a controlled NOT gate. It implements two n-bit addition operations that do not destroy the source operand.
It is assumed that integers a and b of n bits are stored in the ground states of two n qubits:
wherein a is n-1 a n-2 ...a 0 And b n-1 b n-2 ...b 0 Binary representations of integers a and b, respectively, a h ,b h ∈{0,1},h＝0,...,n-1。
Quantum ground state added with n quantum bitsThe auxiliary bit of the most addition operation and the row order obtain |00b n- 1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >As input. Applying adder to |00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >Obtaining
A D ||00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >＝|s n s n-1 b n-1 a n-1 s n-2 b n-2 a n-2 ...s 0 b 0 a 0 > (6)
Wherein s=a+b, s n s n-1 s n-2 ...s 0 Is a binary representation of the integer s, s h ∈{0,1},h＝0,...,n。
As can be seen from the formula (6), the adder implements the following addition operation:
analyzing the quantum circuit in FIG. 7, the quantum cost of the adder that implements an n-bit integer without destroying the source operand is 6 (n-1) +6 (n-1) +2×4+1=12n-3, n.gtoreq.2, (n-1) basic gates P 1 And a basic gate P 2 Running in parallel, (n-1) basic gates P 3 And a basic gate P 4 And the parallel operation is performed, so that the line time complexity is 3 (n-1) +3 (n-1) +2×4+1=6n+3, and n is more than or equal to 2, which fully reflects the high efficiency of the addition line designed by the patent.
Let n=3, assume that 3-bit integers a and b are stored in the ground states of the following two 3 qubits:
wherein a is 2 a 1 a 0 And b 2 b 1 b 0 Binary representations of integers a and b, respectively, a h ,b h ∈{0,1},h＝0,...,2。
The adder is designed to implement the following addition operations:
the specific implementation process is as follows: quantum ground state added with 4 quantum bitsThe auxiliary bit of the most addition operation and the row order obtain |00b 2 a 2 0b 1 a 1 0b 0 a 0 >As input, apply adder to |00b 2 a 2 0b 1 a 1 0b 0 a 0 >Obtaining
A D |00b 2 a 2 0b 1 a 1 0b 0 a 0 >＝|s 3 s 2 b 2 a 2 s 1 b 1 a 1 s 0 b 0 a 0 > (10)
Wherein s=a+b, s 3 s 2 s 1 s 0 Is a binary representation of the integer s, s h ∈{0,1},h＝0,...,3。
The implementation line is shown in FIG. 8, which is composed of a basic gate P 1 、P 5 、P 6 And P 3 Each 2, P 2 And P 4 Each of 1, 2 controlled V gates and one controlled not gate, the quantum cost of the line is 33, and the time complexity of the line is 21.
While the preferred embodiments of the present invention have been illustrated and described, the present invention is not limited to the embodiments, and various equivalent modifications and substitutions can be made by one skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention.
Claims (2)
1. The method is characterized in that the method utilizes quantum controlled gates to design 6 basic quantum gates which are convenient for parallel calculation, then utilizes the 6 basic quantum gates to design a quantum half adder, a quantum full adder and a corresponding reset device, and finally utilizes the quantum half adder, the quantum full adder and the corresponding reset device to set up the design method for forming the n-bit non-destructive source operand adder;
the specific process of designing the 6 basic quantum gates is as follows:
realizing 6 basic quantum gate design circuits by 3 controlled gates, respectively using symbol P 1 、P 2 、P 3 、P 4 、P 5 And P 6 The quantum cost and quantum time complexity of the 6 basic quantum gate design circuits are 3, and the structures are respectively as follows: basic door P 1 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 2 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 3-quantum bit connecting line; basic door P 3 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 4 The device consists of 2 controlled V gates, a controlled NOT gate and a 3-quantum bit connecting line; basic door P 5 The device consists of 1 controlled V gate, 1 controlled V+ gate, one controlled NOT gate and a 4-qubit connecting line; basic door P 6 The device consists of 2 controlled V gates, a controlled NOT gate and a 4-quantum bit connecting line;
the implementation process for designing the quantum half adder and the corresponding resetter is as follows:
with controlled V-gate, basic gate P 2 Realizing quantum half adder design circuit by symbol A 1 The representation is made of a combination of a first and a second color,
application of quantum half adder to quantum state |0>|b 0 >|a 0 >Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}, the quantum half adder is known to perform addition (b) from equation (1) 0 +a 0 ) In which the first qubit of the output is |a 0 b 0 >Storage addition (b) 0 +a 0 ) Carry information of (2), second qubit of output +.>Stored is the sum of additions;
the reset device of quantum half adder is designed without destroying source operand, and consists of controlled V gate and basic gate P 3 Is formed by the symbol R 1 A representation;
application of a reset of a quantum half adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b 0 ,a 0 E {0,1}, it is known from equation (2) that the resetter of the quantum half-adder will +.>Reset to |b 0 >|a 0 >；
The quantum cost and the time complexity of the quantum half adder and the corresponding resetter are both 4;
the implementation process for designing the quantum full adder and the corresponding resetter is as follows:
by means of basic gates P 1 And P 5 Realizing quantum full adder design circuit by symbol A 2 A representation;
application of quantum full adder to quantum state |0>|b i >|a i >|c i-1 >Obtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i-1 E {0,1}, the addition (b) is realized by a quantum full adder known from the formula (3) i +a i +c i-1 ) Wherein the first qubit of the output +.>Storage addition (b) i +a i +c i-1 ) Carry information of (2), second qubit of output +.>Stored is the sum of additions;
without destroying source operand, a reset device of quantum full adder is designed, which consists of basic gate P 3 And P 6 Composition, denoted by the symbol R 2 A representation;
application of a reset of a quantum full adder to a quantum stateObtaining
Wherein the method comprises the steps ofIs an exclusive or operation, b i ,a i ,c i-1 E {0,1}, from equation (4) it is known that the resetter of the quantum full adder willReset to |b i >；
The quantum cost and time complexity of the quantum full adder and resetter is 6.
2. The method of claim 1, wherein the designing n-bit qubit non-destructive source operand adders is implemented by:
the quantum half adder, the quantum full adder and the corresponding resetter are utilized to realize that n quantum bits do not damage a quantum adder design line of a source operand, and symbol A is used D The quantum adder of the n quantum bit without destroying the source operand is composed of n-1 quantum full adder and reset, 1 quantum half adder, 1 reset of the quantum half adder and one controlled NOT gate, wherein the reset of the quantum full adder can be decomposed into n-1 basic gates P 1 、P 5 、P 6 And P 3 Two n-bit addition operations without destroying the source operand are realized;
it is assumed that integers a and b of n bits are stored in the ground states of two n qubits:
wherein a is n-1 a n-2 ...a 0 And b n-1 b n-2 ...b 0 Binary representations of integers a and b, respectively, a h ,b h ∈{0,1},h＝0,...,n-1；
Quantum ground state added with n quantum bitsTo obtain the auxiliary bit of addition and the row order of the auxiliary bit is |00b n-1 a n- 1 0b n-2 a n-2 ...0b 0 a 0 >As input, apply adder to |00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >Obtaining
A D |00b n-1 a n-1 0b n-2 a n-2 ...0b 0 a 0 >＝|s n s n-1 b n-1 a n-1 s n-2 b n-2 a n-2 ....s 0 b 0 a 0 > (6)
Wherein s=a+b, s n s n-1 s n-2 ...s 0 Is a binary representation of the integer s, s p ∈{0,1},p＝0,...,n；
As can be seen from the formula (6), the adder implements the following addition operation:
the quantum cost of the adder which realizes the n-bit integer and does not damage the source operand is 6 (n-1) +6 (n-1) +2×4+1=12n-3, n is more than or equal to 2, n-1 basic gates P 1 And a basic gate P 2 Running in parallel, n-1 basic gates P 3 And a basic gate P 4 Run in parallel, therefore, the line time complexity is 3 (n-1) +3 (n-1) +2×4+1×6n+3, n.gtoreq.2.
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