CN1360348A - Structure and circuit of logarithmic skip adder - Google Patents
Structure and circuit of logarithmic skip adder Download PDFInfo
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- CN1360348A CN1360348A CN 02100380 CN02100380A CN1360348A CN 1360348 A CN1360348 A CN 1360348A CN 02100380 CN02100380 CN 02100380 CN 02100380 A CN02100380 A CN 02100380A CN 1360348 A CN1360348 A CN 1360348A
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Abstract
The invention relates to a circuit of digital adder in binary. The carry skipping algorithm is used between grups and the ELM tree type adding structure is used inside group in the circuit. Adopting new carry combination structure makes the initial carry embed into the carry chain so as to realize transferring parallel carry within group. The relationship between the delay of key path and number of bits within group is logarithmic. The invented circuit structure has advantages of the adder produced with small area and quick speed, simple connecting wire, easy to be integrated. The invention can implement binary add operation in 32 bits and 16 bits effectively.
Description
Technical field: the present invention relates to the integrated circuit (IC) design field.
Background technology:
Binary addition is complicated operations among the microprocessor ALU (ALU), is the key of decision ALU arithmetic speed.Algorithm and structure commonly used at present have carry lookahead adder (Carry LookaheadAdder), carry skip adder (Carry SkipAdder), tree structure adder (Tree-StructuredAdder), as " IEEE Transactions on Circuits and Systems-II:Analog andDigital Signal Processing; Vol.43; No.10; October 1996, the ELM tree structure adder in " Area-Time-PowerTradeoffs in Parallel Adders ".Carry lookahead adder speed is very fast, but hardware spending is big; Carry jump structure save area, but speed is limited, is unsuitable for the add operation more than 16; Tree-like adder is defectiveness aspect fan-out or line complexity then.Forms such as common circuit realizes static state being arranged, dynamic, asynchronous.And static circuit with its be easy to design, low-power consumption and antimierophonic characteristics become the main circuit implementation of adder.In the application of adder, the initial carry that enters lowest order often needs.Particularly 2 add ,/when subtracting function, initial carry is necessary in subtraction when realize mending with adder.In adder commonly used realizes, the information of initial carry is by use the final effectively carry of one-level logical calculated again after all partial carry produces, or add the one-level logic at lowest order, and produce effective carry that lowest order makes progress with initial carry, again this carry is transmitted step by step.Which kind of scheme all need increase one-level logical delay on critical path.
Summary of the invention:
The objective of the invention is to propose the circuit design of a kind of new adder structure and a kind of carry integrated structure and above structure, realize little, the fireballing binary adder of area, make circuit realize that line is tried one's best less, compound with regular structure is beneficial to Butut simultaneously.
Content of the present invention and technical scheme are as follows:
The present invention proposes that a kind of Static CMOS Circuits realizes the binary digit adder circuit---logarithm skip adder (Logarithmic Skip Adder) comprises following three partial contents:
1. the structural design of logarithm skip adder;
2. carry is in conjunction with (Carry Incoporated) structure Design;
3.S the transistor level of operator and carry binding modules circuit design.(1) the structural design 1. algorithm bases of logarithm skip adder
The following formulate of logical operation that relates to the binary digit adder circuit in this specification:
Ab:a and b
A+b:a or b
A b:a XOR b
A＝a
n-1a
n-2…a
0
If two n positional operands are:
B＝b
n-1b
n-2…b
0
Initial carry: c
-1
Carry produces (Carry-generation) signal: g
i=a
ib
i(1)
Carry is transmitted (Carry-propagation) signal: p
i=a
i b
i(2)
Carry transmission (Carry-transition) signal: t
i=a
i+ b
i(3)
Then from the carry signal of i position to the i+1 position: c
i=g
i+ p
ic
I-1(4)
Or c
i=g
i+ t
ic
I-1(5)
The i position and: S
i=a
i b
i c
I-1=p
i c
I-1(6)
S operator wherein and E operator constitute and transmit tree, E operator calculating section and, the S operator calculates
The result and.P operator and G operator constitute carry tree.Logical expression is as follows:
P operator: P
Ij=P
iP
j(7)
G operator: G
Ij=G
i+ P
iG
j(8)
E operator: Ps
Out=Ps
In G (9)
S operator: S=Ps (PG) (10)
32 this binary digit adder circuits are divided into 5 groups with addition and carry out structure such as Fig. 1.Wherein each module is shown in Fig. 2,3,4,5.Have 5 modules, all adopt the ELM tree structure.U6 among Fig. 1, two U7 and U8
*All contain same U4 module in the module.This binary digit adder circuit carries out addition by certain figure place grouping, carry out additional calculation and generation in the group to the carry of next group, transmits carry between group.
Adopt the alternative Port Multiplier between group, select signal be in this module every carry transmission signal P with the result; When selecting signal to be ' 1 ', show that last module can be directly delivered to the initial carry of next module as next module to the carry signal of this module, promptly skips this module; When selecting signal be ' 0 ', show that a certain position that the initial carry of this module is bound in this module is absorbed, and the carry of a certain position produces signal G and can be delivered to next module as initial carry as carry in the module.The initial carry of this carry signal and this module is irrelevant, therefore can do parallel computation with prior module.The principle that carry that Here it is is jumped.
For example among Fig. 1 alternative Port Multiplier M
a, M
b, M
c, select signal to be respectively GP1, GP2, GP3:
GP1＝p8p9p10p11p12p13p14；
GP2＝p15p16p17p18p19p20p21；
GP3＝p22p23p24p25p26p2；
In the inside modules that traditional carry is jumped, carry signal is a serial transfer, this feature limits the figure place in the module can not be excessive.Because transmitting signal GP at the group carry of this module be ' 0 ', and the group carry of next module to transmit signal be under ' 1 ' the situation, two modules and MUX are passed in the possible serial of carry signal, this is a critical path.Therefore the figure place in the module is long has a very long critical path.If the figure place in the module is little, can cause the increase of number of modules again, the increase of carry number of skips means more logical time delay equally.The present invention adopts the tree-like add structure of ELM in group, utilize the carry jump algorithm between group, and the carry transmission in the feasible group realizes parallel, and the figure place in its critical path logic level and the group is logarithmic relationship.Figure place is 2 in group
nThe time, output and every result and need n+1 level logic from each operative position to this group carry.For example figure place is 8 o'clock in module, the carry output from each operative position to this module and every result and needs 4 grades of logics, i.e. log
2Therefore n+1 is called the logarithm skip adder, and 8 modules of serial then need 9 grades of logics in the traditional group.2. structure realizes
U8 shown in Figure 3
*Module utilization carry integrated structure makes to comprise initial carry c
-1The operation time-delay of counting to the carry output of this module be 4 grades of logics; The low level section has 3 in U7 shown in Figure 4 (being U7a and the U7b among Fig. 1) module, and high-order section has 4, such structure make this module initial carry to carry output and result and time-delay be 3 grades of logics; The low level section of U6 module shown in Figure 5 is 3, and high-order section is 4, and its initial carry is 2 grades of logics to the time-delay of carry output.The time-delay of the critical path of the logarithm skip adder of Fig. 1 structure is 8 grades of logics like this.
Critical path has 8 kinds of situations altogether.Because the possible value of GP3, GP2, GP1 is 000 to 111.Critical path under the three kinds of situations of having drawn among Fig. 1: work as GP
3GP
2GP
1During for (000), critical path be certain from U7a be input to U7b certain position and; When being (101), critical path is from U8
*Certain input of module skip U7a to U7b certain the position and; When being (111), from U8
*Certain input of module skip U7a, U7b, U6 to certain position of U4 and.Other situation can similarly draw.With (101) is example, shown in short dash line, critical path from the ab of U8* unit to C3, this is 4 grades of logic gate delay: because GP1 equals 1, C3 can skip the U7a module and arrive MUX Ma, one-level gate delay through Port Multiplier enters the U7b module, arrives S21 at U7b through 3 grades of gate delay, altogether 8 grades of gates.This situation also has a paths not have picture because this paths do not have last one long, do not include critical path: because GP2 equals 0, the carry that this explanation enters into U7b is bound to be absorbed in a certain position of this module; Therefore U7b is irrelevant with the carry that enters into U7b to the carry of U6 module by Mb; Be that carry in U6, the U4 module can obtain by the carry exported among the U7b, and irrelevant with the carry before the U7b; So when the carry of front was skipped U7a and entered U7b from U8*, the carry signal of certain generation can be passed through M again through the level Four logic of U7b among the U7b
bThe one-level logic is skipped U6 module (because GP3 equals 1), through M
cThe one-level logic enters the U4 module, and this paths is 7 grades of logics altogether.These 8 kinds situation can the rest may be inferred, and the longest critical path is 8 grades of gates.(2) the design 1. algorithm bases of carry integrated structure
Initial carry c
-1Being the carry that enters into the adder lowest order, is necessary in a lot of the application.Traditional carry increases the extra logic of one-level in conjunction with needs.The present invention is directed to the logarithm skip adder, adopt Ling ' s algorithm, proposed a kind of carry integrated structure, be embedded in the carry chain of adder in following initial carry of the situation that does not increase delay.
U8 among structure chart such as Fig. 3
*Shown in the low level section of module.When the lowest order that initial carry is added to tree-like adder, from tree-like original balance, the lowest order (a of losing of structure
0, b
0) longer than other ' branches ' to one ' branch ' of carry output, thereby increased the logical time delay of critical path.In the ELM module, exist carry and produce (G computing), carry transmission (P computing) and transmit (S computing) three trees.Carry tree utilizes formula (1), (2), (4) to calculate, and wherein carry transmission tree produces the effect that carry jump Port Multiplier is selected signal in addition.But U8 in Fig. 1 structure
*Module does not need the selection signal is provided, and utilizes this point the carry tree in this module can be transformed.The carry computation of ELM module can be represented by the formula:
c
0＝g
0+p
0c
-1 (11)
c
1＝g
1+p
1c
0 (12)
c
3=g
32+ p
32c
1(13) 2. structure realizes
In the carry integrated structure that the design proposes, at first use formula (1), (3), (5) to calculate carry tree, like this on critical path just with one or replaced circuit to implement slow XOR gate, reduced time-delay.Secondly in low level section shown in Figure 3, we are c
-1, g
0, t
0, g
1Send into B
aAnd t
1, g
2, t
2, g
3, t
3Send into B
b, rather than send into B as four signals and the initial carry of low 2 of traditional handle
a, four high 2 signals are sent into B
bIn new carry integrated structure, B
aOutput H be not carry signal effectively, be called the pseudo-carry signal.This signal is at next stage and B
bOutput signal in conjunction with after, export effective carry signal c
3The logical expression of these signals is as follows:
H
1＝g
1+g
0+t
0c
-1 (14)
G
32＝g
3+t
3g
2 (15)
T
321＝t
3t
2t
1 (16)
C
3＝G
32+T
321H
1 (17)
The design of this carry integrated structure is embedded in the carry chain of adder in following initial carry of the situation that does not increase delay.Compare with traditional implementation, the carry integrated structure that the design proposes can reduce the critical path delay of one-level logic, though on hardware, will increase some expenses, because also need with H and t with, is the pseudo-carry conversion of signals effective carry signal, could calculate then one's own department or unit the result and, but this part logic is not on critical path.Like this, from c
-1To c
7Critical path be three grades of logics, and from (a
0, b
0) to c
7It is the level Four logic.The carry integrated structure that the design proposes is not limited to the logarithm skip adder, also can be applied to other tree structure adder.
Because what fan-out of back is very big in the ELM adder structure: and when the VLSI circuit was realized, gate delay can increase along with fan-out, in big fan-out, sharply increase of time-delay; Therefore need add buffer in the situation of big fan-out and limit fan-out, but can increase time-delay so again, make the ELM adder realize that logical time delay increases than the architecture logic time-delay.For one four binary tree structure, be from 4 to 2, again from 2 to one.This is a balanced structure, comes to three grades.If 5 inputs are arranged, will increase one-level, just from 5 to 3, from 3 to 2, again from 2 to 1,4 grades altogether.For adder, if initial carry is arranged, in low four, just be equivalent to 5 binary tree, be that unbalanced construction can increase one-level, can adopt the carry integrated structure to solve.Adopt 8 ELM structures in the logarithm skip adder of the present invention design, by with of the combine distribution of addend figure place with initial carry, construct the binary tree of balance, thus the maximum fan rising limit of ELM adder built in 5.As Fig. 4, for three unit (as low three among the U7), then add initial carry, just in time can be made into 4 binary tree, be three grades balanced structure.
In order to satisfy maximum fan-out is 5 restriction, and in the U7 of Fig. 1 structure, the U6 module, carry is in conjunction with being that figure place by reducing operand realizes.7 operands or 6 operands add that initial carry can obtain the tree structure of balance.Can see Fig. 4,5, for one four binary tree structure, be from 4 to 2, again from 2 to one.This is a balanced structure, comes to three grades.If 5 inputs are arranged, will increase one-level, just from 5 to 3, from 3 to 2, again from 2 to 1,4 grades altogether.For adder, if initial carry is arranged, in low four, just be equivalent to 5 binary tree, be that unbalanced construction can increase one-level, so solve with the carry integrated structure.But for three unit, low three as among the U7 adds initial carry, just in time can be made into 4 binary tree, is three grades balanced structure.
In like manner Fig. 6 is that the maximum fan-out of a kind of critical path is 32 logarithm skip adder structures of 4.U7 wherein
*The low level section be 4, adopt the carry integrated structure, high-order section is 3.Wherein the structure of U6` module as shown in Figure 7.The structure of U3 is identical with the high-order section of U6` module.Therefore the maximum fan-out on the whole adder critical path is 4, and critical path depth is the same with structure among Fig. 1.But comparing with the structure of Fig. 1, this structure needs more hardware spending.Fig. 8 is the structure of 16 logarithm skip adder, and the low level section of U5 module is 2, and high-order section is 3.Maximum fan-out is 4, and critical path is 6 grades of logical delays.(3) design of circuit structure
At logarithm skip adder structure, we have carried out the transistor level design to two circuit by emphasis.It is respectively the circuit of realizing S operator and carry integrated structure.
The function that the S operator is realized is and XOR to see formula (10).Circuit structure as shown in Figure 9, the design main purpose is to realize function with trying one's best transistor few.Because in Fig. 1 structure, have 28 S operators, the effective circuit implementation helps save area, and then reduces power consumption.Circuit utilizes the excellent Points And lines or the logic of transmission gate logical validity realization XOR gate to save transistorized characteristics.Node J realize line or, because conducting simultaneously of a road and the NMOS one tunnel that PMOS forms.MP is the PMOS pipe, and Mn is the NMOS pipe.Since PMOS transmit ' 0 ' and NMOS the threshold value loss is arranged when transmitting ' 1 ', can occur weakly ' 0 ', weak ' 1 ' at node J, will cause the part conducting of output inverter transistor, produce steady state short circuit current, thereby increase power consumption.The effect of MP3 and MN3 is a signal level of recovering node J, eliminates quiescent dissipation.
These two transistors will be with minimum size, to reduce the influence to circuit speed of the electric capacity introduced.In the less demanding application of power consumption, also can recover pipe by two level, to obtain faster speed.What the tradition complementary cmos was realized needs the two-stage gate delay with XOR, 16 transistors.And Fig. 9 structure needs the one-level gate delay, adds necessary inverter totally 10 transistors.The logarithm skip adder of whole Fig. 1 structure can be saved 168 transistors altogether.
The circuit design of carry integrated structure is seen Figure 10.The purpose of design is to realize the logic of formula (1), (3), (14), (15), (16), (17) fast, shortens critical path.As previously described formula (14) can with one-level with or door realize that but three transistors polyphones can appear in such circuit, the equivalent electric resistive is big, underspeeds.In the structure of Figure 10, formula (1), (3), (14) are realized with following formula:
H
1＝a
1b
1+a
0b
0+(a
0+b
0)c
in (18)
Structure with Figure 10 can realize above logic, and same formula (1), (3), (11) are compared, and is to use the two-stage door equally, but has avoided the situation of three transistor polyphones, helps raising speed.
The Figure of description explanation:
Fig. 1: the structure of 32 logarithm skip adders;
U4 module among Fig. 2: Fig. 1,3,4,5
Fig. 3: the U8* module among Fig. 1
Fig. 4: the U7 module among Fig. 1
Fig. 5: the U6 module among Fig. 1
Fig. 6: maximum fan-out is 4 LSA structure
Fig. 7: the U6` module among Fig. 6
Fig. 8: the structure of 16 logarithm skip adder,
Fig. 9: S operator circuit structure
Figure 10: carry combined circuit structure
Embodiment: be described further below in conjunction with embodiment.
Fig. 1 is a kind of structure of 32 logarithm skip adders.This structure is divided into 5 groups with 32, utilizes the carry jump algorithm between group, adopts the tree-like add structure of ELM in the group, and the carry transmission in the feasible group realizes parallel, and the figure place in its critical path logic level and the group is logarithmic relationship.Thereby overcome the restriction of the speed that cascaded carry brings in traditional carry skip adder group.The ELM structure of each group such as Fig. 2, Fig. 3, Fig. 4, shown in Figure 5.
The ELM adder is compared with other tree structure, sum logic is embedded in the tree structure, thereby after obtaining the prime carry, only need a logic gate delay just can obtain every and with the carry of next stage.Other tree structure then will obtain one's own department or unit carry earlier, and then with one-level logical calculated one's own department or unit and, therefore many one-levels logic.High-order section in the ELM adder structure (as 3 to 6 of U7 module) and low level section (as 0 to 2 of U7 module) parallel computation; Owing at this moment lack the information of low level, a high position is calculated be partial carry with part and.After the carry of low level passes to high-order section, obtains final carry and result with.The subject matter of this structure is that the fan-out of circuit is very big, is (n/2+1) for the realization of big word length adder, and wherein n is the word length of operand.The maximum fan-out of 32 adders is 17.Big fan-out need add multistage buffer when VLSI realizes, the result increases time-delay.It is 8 ELM adder that adder structure among the present invention adopts maximum word length, has significantly reduced fan-out, kept simultaneously ELM architecture logic level less, the simple advantage of line.
Advantage of the present invention and good effect are:
Compare with the ELM structure with the carry jump, the logarithmic skip structure that the present invention proposes is the knot to the two advantage Close. For 32 adders that initial carry is arranged, the logarithmic skip adder of Fig. 1 structure needs 186 and patrols Collect door, 8 grades of logics, maximum fan-out are 5; And the ELM structure needs 248 gates, 7 grades of logics, maximum Fan-out is 17; 4 one group carry skip structure needs 149 gates, 14 grades of logics, and maximum fan-out is 2. Designed carry integrated structure has been realized the adder that speed is fast, area is little, have line simple, Be easy to integrated advantage. The logarithmic skip adder structure that employing the present invention proposes and corresponding carry are in conjunction with knot Structure and circuit implementation structure can be realized 32 and 16 binary adders effectively.
Claims (10)
1. a binary digit adder circuit carries out the add operation grouping, carries out additional calculation and the generation carry to next group in the group, jump between group and transmit carry, it is characterized in that: adopt the tree-like add structure of ELM in the group, utilize the carry jump algorithm between group, the carry in the parallel transmission group; Figure place in the group in critical path delay and the group is logarithmic relationship.
2. binary digit adder circuit according to claim 1 is characterized in that: the maximum word length of employing is 8 ELM adder in the group; By the binary tree of carry integrated structure structure balance, the maximum fan rising limit of ELM adder built in 5.
3. binary digit adder circuit according to claim 1 and 2 is characterized in that: the tree structure adder adopts the design of carry integrated structure in the group, is embedded in the carry chain of adder in following initial carry of the situation that does not increase critical path delay; I.e. low 4 sections in the structure as shown in Figure 3 are with t
1Signal is sent into module B
bModule B
aOutput signal H
1=a
1b
1+ a
0b
0+ (a
0+ b
0) c
-1The H signal with module B
bOutput signal in conjunction with after, export effective carry signal c
3
4. according to claim 2 or 3 described binary digit adder circuits, it is characterized in that: the transistor level design of carry integrated structure circuit utilizes branch line or structure to realize pseudo-carry logic H as Figure 10
1=a
1b
1+ a
0b
0+ (a
0+ b
0) c
In
5. according to the described binary digit adder circuit of one of arbitrary claim of claim 1-4, it is characterized in that: the design of S operator transistor level as shown in Figure 9 in the binary digit adder circuit; Utilize transmission gate logic realization and XOR, node J realize line or.
6. according to the described binary digit adder circuit of one of arbitrary claim of claim 1-5, it is characterized in that: 32 this binary adder circuit are divided into 5 groups with addition and carry out structure such as Fig. 1.
7. binary digit adder circuit according to claim 6 is characterized in that: the maximum fan-out of 32 adder structure is 5 among Fig. 1, U6, U7 and U8
*All contain same U4 module in the module.
8. binary digit adder circuit according to claim 7 is characterized in that: U8
*Module utilization carry integrated structure as shown in Figure 3, comprises initial carry c
-1The operation time-delay of counting to the carry output of this module be 4 grades of logics; U7 module low level section is 3, and high-order section is 4, this module from initial carry to output carry and the result and time-delay be 3 grades of logics, as shown in Figure 4; The low level section of U6 module is 3, and high-order section is 4, and the time-delay that this module is exported from initial carry to carry is 2 grades of logics, as shown in Figure 5; 32 binary adder circuit critical path time-delays among Fig. 1 are 8 grades of gates thus.
9. according to the described binary digit adder circuit of one of arbitrary claim of claim 1-5, it is characterized in that: 32 this binary adder circuit are divided into 5 groups with addition and carry out structure such as Fig. 6; U6 ' modular structure as shown in Figure 7, low level section and high-order section respectively are 3; Both guaranteed c
InTo c
5Time-delay be 2 grades of logics, guarantee c again
2Fan-out be 4.
10. according to the described binary digit adder circuit of one of arbitrary claim of claim 1-5, it is characterized in that: 16 this binary adder circuit are divided into 3 groups with addition and carry out structure such as Fig. 8; Wherein the low level section of U5 module is 2, and high-order section is 3; Maximum fan-out is 4, and critical path is 6 grades of logical delays.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101014932B (en) * | 2004-08-04 | 2010-06-16 | 英特尔公司 | Carry-skip adder having merged carry-skip cells with sum cells |
| CN102082561A (en) * | 2011-03-03 | 2011-06-01 | 北京大学 | SOI (silicon on insulator) clock double-edge static D type trigger |
| CN109426483A (en) * | 2017-08-30 | 2019-03-05 | Gsi 科技公司 | Concurrent multibit adder |
| CN116149599A (en) * | 2023-03-30 | 2023-05-23 | 杭州雄迈集成电路技术股份有限公司 | Step-by-step carry processing method, system and adder |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101201731B (en) * | 2008-02-15 | 2010-08-18 | 刘杰 | Binary digit subtracter |
| US9471278B2 (en) * | 2014-09-25 | 2016-10-18 | Texas Instruments Incorporated | Low area full adder with shared transistors |
-
2002
- 2002-01-17 CN CNB021003807A patent/CN1164988C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101014932B (en) * | 2004-08-04 | 2010-06-16 | 英特尔公司 | Carry-skip adder having merged carry-skip cells with sum cells |
| CN102082561A (en) * | 2011-03-03 | 2011-06-01 | 北京大学 | SOI (silicon on insulator) clock double-edge static D type trigger |
| CN102082561B (en) * | 2011-03-03 | 2012-10-10 | 北京大学 | SOI (silicon on insulator) clock double-edge static D type trigger |
| CN109426483A (en) * | 2017-08-30 | 2019-03-05 | Gsi 科技公司 | Concurrent multibit adder |
| CN109426483B (en) * | 2017-08-30 | 2021-09-21 | Gsi 科技公司 | Concurrent multi-bit adder |
| CN116149599A (en) * | 2023-03-30 | 2023-05-23 | 杭州雄迈集成电路技术股份有限公司 | Step-by-step carry processing method, system and adder |
| CN116149599B (en) * | 2023-03-30 | 2023-08-08 | 杭州雄迈集成电路技术股份有限公司 | Step-by-step carry processing method, system and adder |
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| Publication number | Publication date |
|---|---|
| CN1164988C (en) | 2004-09-01 |
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