CN1316613C - Sandwich antireflection structural metal layer of semiconductor and making process thereof - Google Patents
Sandwich antireflection structural metal layer of semiconductor and making process thereof Download PDFInfo
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- CN1316613C CN1316613C CNB031373828A CN03137382A CN1316613C CN 1316613 C CN1316613 C CN 1316613C CN B031373828 A CNB031373828 A CN B031373828A CN 03137382 A CN03137382 A CN 03137382A CN 1316613 C CN1316613 C CN 1316613C
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Abstract
The present invention relates to a sandwich antireflection structural metal layer of a semiconductor and a making process thereof. In order to provide a semiconductor part and a manufacturing for improving the excursion of a metal layer to a contact window and the quality and the performance of a semiconductor element in the process of semiconductor element manufacture, the present invention is proposed. The sandwich antireflection structural metal layer of a semiconductor comprise a first Ti film layer, a first TiN film layer, a second Ti film layer and a second TiN film layer, wherein the TiN film layer is arranged on the first Ti film layer; the second Ti film layer is arranged on the first TiN film layer; the second TiN film layer is arranged on the second Ti film layer. The semiconductor has the making process that a dielectric layer is formed; the sandwich antireflection structural metal layer which comprises the first Ti film layer, the first TiN film layer on the first Ti film layer, the second Ti film layer on the first TiN film layer and the second TiN film layer on the second Ti film layer is formed on the dielectric layer; a plurality of isolation regions are formed on the dielectric layer which is formed into the sandwich antireflection structural metal layer; an etched substrate is cleaned; a field oxide layer is formed.
Description
Technical field
The invention belongs to semiconductor device and manufacture method thereof, particularly a kind of semi-conductive sandwich anti-reflection structure metal level and processing procedure thereof.
Background technology
Fast flash memory bank is a kind of non-volatile memory cell, but it comprises the suspension gate and the electric charge access and exit control unit of store charge.Fast flash memory bank can be applicable to the ROM-BIOS (BIOS) in the computer, and the range of application of high density non-volatility memory then comprises the interface card of big capacity memory storage, digital camera and PC in the portable device etc.Non-volatility memory has many advantages, for example fast access time, low-power consumption and durable.In order to cater to the application demand in Maneuver Computing System, the function of low electric power and fast access becomes the deisgn approach of non-volatility memory.In high performance memory body, there is an epochmaking key parameter to be called capacitive coupling rate (capacitive-coupling ratio).Bergemont is at its paper " Low voltage NVGTM:A New High Performance 3 V/5 VFlash Technology for Portable Computing and TelecommunicationsApplication " (in IEEE Trans.Electron Devices Vol.43, p.1510, the another kind of memory cell that is applied to portable computer and telecommunication apparatus is proposed 1996), this memory cell structure is incorporated in anti-or lock formula virtual ground (the NOR Virtual Ground of low-voltage, NVG) fast flash memory bank has fast access time.In the flash array system, the polysilicon layer extends on the field oxide between memory cell so that the gate coupling efficiency (gate coupling ratio) of suitable foot to be provided.Bergemont also proposes portable computer and telecommunications industry has become the main drive of semiconductor integrated circuit designing technique.Access time is the key that low-voltage reads running.The NVG array adopts the mode of selecting element to reach the access time fast, only reduces carry out ahead of schedule the charging interval (the pre-charge time) of single link at every turn, and does not handle whole bit lines.
In traditional technical field, developed and the multi-form non-volatility memory of many kinds (nonvolatile memory).Mitchellx has proposed a method and has had erasing of autoregistration planar array born of the same parents and programmable ROM (EPROM) in order to manufacturing.The method adopts imbeds doped region in order to form MOS electric crystal (floating gate avalanche injection MOS, FAMOS) bit line, referring to A.T.Mitchellx, " A New Self-Aligned Planar Cell for Ultra HighDensity EPROMs " IEDM, Tech.pp.548-553,1987.The information of fast flash memory bank stores to rely on electric charge is resided in the floating gate for a long time, therefore, must have good performance in order to the dielectric layer of isolating the suspension gate.Present low-voltage fast flash memory bank discharges and recharges the basic fundamental that is adopted to the suspension gate usually under the operating voltage of 3-5V, requiring to reduce under the trend of supply voltage, in order to reach high electrons tunnel efficient, the medium thickness between suspension gate and substrate must be reduced.Yet when medium thickness is reduced to 10nm when following, its reliability is also along with reduction.Utilize the Fowler-Nordheim tunneling effect of electronics to wear oxide layer between tunnel gate and drain, electronics is worn tunnel by the suspension gate, and to cause the suspension gate to drain be relative positive charge, this phenomenon with critical voltage (threshold Voltage) toward negative direction skew.If control grid imposes high voltage and drain ground connection, electronics is then worn tunnel to the gate that suspends and is caused critical voltage (threshold Voltage) toward positive direction skew.The then respectively corresponding two kinds of different logic signals of above-mentioned two kinds of different critical voltages skew, for example ' 0 ' and ' 1 '.
In making the semiconductor element process, the aligning of metal pair contact hole (metal to contactalignment) is a kind of important fabrication stage, can observe the skew of this metal pair contact hole by SEM and AEI REG data.
As shown in Figure 1, wafer frontside comprises several and is defined thereon interval.
As shown in Figure 2, metal level 6 is formed on the dielectric layer 2, and dielectric layer 2 comprises contact window formed thereon 4, fills up conducting medium in contact window 4.The appearance profile of metal level 6 will be based on the stress of 2 of metal level 6 and dielectric layers and is changed.Subsequent step is the pattern-making step of photoresistance patterning process, is beneficial to carry out little shadow program.Yet little shadow program will utilize above-mentioned metal level outward appearance as aiming at reference.The above-mentioned metal level appearance profile that is subjected to stress and is offset change will provide wrong information, cause the metal pattern after the etching of photoresistance pattern can not be located on the correct position.
As shown in Figure 1, observe crystal column surface left and right side zone by SEM, the contact window major part will be exposed to outside the metal pattern, and this meaning is very serious between intermembranous stress problem.This phenomenon will reduce the quality and the performance of element, therefore be badly in need of a kind of structure that solves metal pair contact window offset problem at present.
Summary of the invention
The purpose of this invention is to provide a kind of improve metal level in the semiconductor element manufacture process to the contact hole skew, improve the semi-conductive sandwich anti-reflection structure metal level and the processing procedure thereof of semiconductor element quality parameter.
The semi-conductive sandwich anti-reflection structure of the present invention metal level comprises:
The one Ti rete;
The one TiN rete is positioned on the Ti rete;
The 2nd Ti rete is positioned on the TiN rete;
The 2nd TiN rete is positioned on the 2nd Ti rete.
The present invention is semi-conductive to be comprised the steps:
Form dielectric layer; Comprise a Ti rete in forming on the dielectric layer, be positioned at a TiN rete on the Ti rete, be positioned at the 2nd Ti rete on the TiN rete and be positioned at the sandwich anti-reflection structure metal level of the 2nd TiN rete on the 2nd Ti rete; On the dielectric layer that forms sandwich anti-reflection structure metal level, form several isolated areas; Cleaning etching metacoxal plate; Form field oxide.
Wherein:
The one Ti thicknesses of layers is between 100-150 ; The one TiN thicknesses of layers is between 150-200 ; The 2nd Ti thicknesses of layers is between 100-150 ; The 2nd TiN thicknesses of layers is between 150-200 .
The one Ti thicknesses of layers is between 100-150 .
The one TiN thicknesses of layers is between 150-200 .
The 2nd Ti thicknesses of layers is between 100-150 .
The 2nd TiN thicknesses of layers is between 150-200 .
Because the semi-conductive sandwich anti-reflection structure of the present invention metal level comprises a Ti rete, be positioned at a TiN rete on the Ti rete, be positioned at the 2nd Ti rete on the TiN rete and be positioned at the 2nd TiN rete on the 2nd Ti rete.
The semi-conductive processing procedure of the present invention comprises the formation dielectric layer; Comprise a Ti rete in forming on the dielectric layer, be positioned at a TiN rete on the Ti rete, be positioned at the 2nd Ti rete on the TiN rete and be positioned at the sandwich anti-reflection structure metal level of the 2nd TiN rete on the 2nd Ti rete; On the dielectric layer that forms sandwich anti-reflection structure metal level, form several isolated areas; Cleaning etching metacoxal plate; Form field oxide.Utilize sandwich anti-reflection structure metal level to disperse and balance based on the stress between TiN rete and dielectric layer, thereby reduce the skew of metal pair contact hole, side-play amount can be dropped to 25nm from the 100nm of previous technology; Improve not only that metal level is offset contact hole in the semiconductor element manufacture process, and improve the semiconductor element quality parameter, thereby reach purpose of the present invention.
Description of drawings
Fig. 1, for the semiconductor crystal wafer electronic type microscope of the prior art manufacturing front view (metal level is offset contact hole) of showing up.
Fig. 2, semiconductor crystal wafer cutaway view (metal level is offset contact hole) for making with prior art.
Fig. 3, for the semiconductor crystal wafer electronic type microscope of the manufacturing of the present invention front view of showing up.
Embodiment
The present invention can be applied to any semiconductor element, as the processing procedure of non-volatility memory.The present invention imports sandwich anti-reflecting layer Ti/TiN/Ti/TiN structure.The metal pair contact hole skew that prior art caused will be enhanced based on the present invention.
The semi-conductive sandwich anti-reflection structure of the present invention metal level comprises:
The one Ti rete, thickness is between 100-150 (dust);
The one TiN rete is positioned on the Ti rete, and thickness is between 150-200 (dust);
The 2nd Ti rete is positioned on the TiN rete, and thickness is between 100-150 (dust);
The 2nd TiN rete is positioned on the 2nd Ti rete, and thickness is between 150-200 (dust);
Utilize the special sandwich anti-reflection structure metal level of this rete to disperse and balance based on the stress between TiN rete and dielectric layer, thereby reduce the skew of metal pair contact hole, side-play amount can be dropped to 25nm from the 100nm of previous technology.
The semi-conductive processing procedure of the present invention comprises the steps:
Form dielectric layer;
As semiconductor substrate, form dielectric layer with the monocrystalline silicon of crystal plane, on dielectric layer, form the number contact window, in contact window, fill up conducting medium.
Form metal level;
Form sandwich anti-reflection structure metal level on dielectric layer, it comprises:
The one Ti rete, thickness is between 100-150 (dust);
The one TiN rete is positioned on the Ti rete, and thickness is between 150-200 (dust);
The 2nd Ti rete is positioned on the TiN rete, and thickness is between 100-150 (dust);
The 2nd TiN rete is positioned on the 2nd Ti rete, and thickness is between 150-200 (dust);
Utilize the special sandwich anti-reflection structure metal level of this rete to disperse and balance based on the stress between TiN rete and dielectric layer, thereby reduce the skew of metal pair contact hole, side-play amount can be dropped to 25nm from the 100nm of previous technology.
Form several isolated areas
Between each element on the dielectric layer that forms sandwich anti-reflection structure metal level, form several isolated areas with stope oxidation isolation method or trench isolation method; The field oxide region of field oxidation isolation method can adopt little shadow and dry ecthing procedure that silicon nitride and silicon combination layer are carried out the etching definition.
Cleaning etching metacoxal plate;
The resistance layer of delustering is also carried out wet type and is removed.
Form field oxide
In the oxygen steam, form one deck field oxide with the thermal oxidation method growth.
From known experience as can be known, the possibility of the depositing temperature of aluminum metal influence skew is lower, still can be observed the influence that the skew that causes based on anti-reflecting layer mainly is based on the TiN rete between 100 ℃ temperature.
The present invention adopts sandwich anti-reflection structure (anti reflection coating; ARC) metal level can drop to 25nm from 100nm with side-play amount.
As shown in Figure 3, in the semiconductor crystal wafer made from the present invention, by it positive in the middle of, the electronic type microscope of left side and right side area shows up and can observe the skew that the present invention can improve the metal pair contact hole that causes based on stress.
Claims (7)
1, a kind of semi-conductive sandwich anti-reflection structure metal level is characterized in that it comprises:
The one Ti rete;
The one TiN rete is positioned on the Ti rete;
The 2nd Ti rete is positioned on the TiN rete;
The 2nd TiN rete is positioned on the 2nd Ti rete.
2, semi-conductive sandwich anti-reflection structure metal level according to claim 1 is characterized in that a described Ti thicknesses of layers is between 100-150 ; The one TiN thicknesses of layers is between 150-200 ; The 2nd Ti thicknesses of layers is between 100-150 ; The 2nd TiN thicknesses of layers is between 150-200 .
3, a kind of semi-conductive processing procedure, it comprises the steps:
Form dielectric layer; On dielectric layer, form metal level; On the dielectric layer that forms metal level, form several isolated areas; Cleaning etching metacoxal plate; Form field oxide; It is characterized in that lying in the described formation metal level step formation sandwich anti-reflection structure metal level on the dielectric layer, it comprises:
The one Ti rete; The one TiN rete is positioned on the Ti rete; The 2nd Ti rete is positioned on the TiN rete; The 2nd TiN rete is positioned on the 2nd Ti rete.
4, semi-conductive processing procedure according to claim 3 is characterized in that a described Ti thicknesses of layers is between 100-150 .
5, semi-conductive processing procedure according to claim 3 is characterized in that a described TiN thicknesses of layers is between 150-200 .
6, semi-conductive processing procedure according to claim 3 is characterized in that described the 2nd Ti thicknesses of layers is between 100-150 .
7, semi-conductive processing procedure according to claim 3 is characterized in that described the 2nd TiN thicknesses of layers is between 150-200 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031373828A CN1316613C (en) | 2003-06-19 | 2003-06-19 | Sandwich antireflection structural metal layer of semiconductor and making process thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031373828A CN1316613C (en) | 2003-06-19 | 2003-06-19 | Sandwich antireflection structural metal layer of semiconductor and making process thereof |
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| Publication Number | Publication Date |
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| CN1567588A CN1567588A (en) | 2005-01-19 |
| CN1316613C true CN1316613C (en) | 2007-05-16 |
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| CN102157356B (en) * | 2011-03-15 | 2015-10-07 | 上海华虹宏力半导体制造有限公司 | The preparation method of the bottom electrode of metal-insulator-metal semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198252A (en) * | 1995-09-29 | 1998-11-04 | 英特尔公司 | Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions |
| JPH10308362A (en) * | 1997-04-30 | 1998-11-17 | Internatl Business Mach Corp <Ibm> | Metallization structure |
| JPH1197531A (en) * | 1997-09-17 | 1999-04-09 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US6383947B1 (en) * | 1998-12-04 | 2002-05-07 | Advanced Micro Devices, Inc. | Anti-reflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies |
| US6555465B2 (en) * | 1997-12-05 | 2003-04-29 | Yamaha Corp. | Multi-layer wiring structure of integrated circuit and manufacture of multi-layer wiring |
-
2003
- 2003-06-19 CN CNB031373828A patent/CN1316613C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198252A (en) * | 1995-09-29 | 1998-11-04 | 英特尔公司 | Metal stack for integrated circuit having two thin layers of titanium with dedicated chamber depositions |
| JPH10308362A (en) * | 1997-04-30 | 1998-11-17 | Internatl Business Mach Corp <Ibm> | Metallization structure |
| JPH1197531A (en) * | 1997-09-17 | 1999-04-09 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US6555465B2 (en) * | 1997-12-05 | 2003-04-29 | Yamaha Corp. | Multi-layer wiring structure of integrated circuit and manufacture of multi-layer wiring |
| US6383947B1 (en) * | 1998-12-04 | 2002-05-07 | Advanced Micro Devices, Inc. | Anti-reflective coating used in the fabrication of microcircuit structures in 0.18 micron and smaller technologies |
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| CN1567588A (en) | 2005-01-19 |
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