CN1314976C - Universal test interface between device under test and test head - Google Patents

Universal test interface between device under test and test head Download PDF

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Publication number
CN1314976C
CN1314976C CN 02800678 CN02800678A CN1314976C CN 1314976 C CN1314976 C CN 1314976C CN 02800678 CN02800678 CN 02800678 CN 02800678 A CN02800678 A CN 02800678A CN 1314976 C CN1314976 C CN 1314976C
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connector
interface
dut
connectors
cable
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CN 02800678
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Chinese (zh)
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CN1494659A (en )
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詹姆士·沃伦·弗雷姆
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爱德旺太斯特株式会社
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers

Abstract

为了在容纳待测器件(DUT)的DUT板和连接到测试头的电缆之间形成模块化接口,提供一个具有连接器阵列的板垫块。 In order to form a modular interface between the receiving device under test (DUT) connected to the DUT board and the test head cable connector array having a spacer plate. 每个电缆连接到一个相应的连接器,并且DUT板包含一个对应的连接点阵列,连接点的数量等于或小于板垫块上的阵列中的连接器的数量。 Each cable is connected to a respective connector, and a respective DUT board comprises an array of connection points, or the number of connection points is equal to the number of connectors on the array is less than spacer plate. 以此方式,可以使用一个公共板垫块来把电缆连接到容纳不同类型DUT的DUT板,因为板垫块上的连接点的位置是已知的并且保持恒定。 In this manner, it is possible to use a common spacer plate to the cable receiving different types of DUT DUT board, because the position of the connection point on the spacer plate are known and held constant. 该接口允许测试头和DUT上器件之间的用于超过50MHz频率的高速和高保真度连接。 This interface allows for frequencies exceeding 50MHz speed and high fidelity connections between the test head and the DUT devices.

Description

待测器件和测试头之间的通用测试接口 General test the interface between the test head and the device under test

技术领域 FIELD

本发明涉及用于测试集成电路元件的自动测试设备,具体涉及自动测试设备中使用的接口硬件,用于把待测器件连接到测试头以便执行测试。 The present invention relates to automatic test equipment for testing integrated circuit elements, particularly relates to interface hardware used in automatic test equipment for the test head is connected to the device under test to perform the test.

背景技术 Background technique

自动测试设备(即测试器)通常用于测试半导体器件和集成电路元件(例如存储器或逻辑电路)的制造缺陷。 Automatic test equipment (i.e. tester) is typically used for testing semiconductor devices and integrated circuit elements (e.g., memory or logic circuit) manufacturing defects. 图1显示了一个测试器的一般表示。 Figure 1 shows a general representation of the tester. 如图所示,测试器1具有测试器体10,测试器体10与测试头20通信。 As shown, the tester 1 has a communication 10 with the test head 20 tester 10, the tester body. 测试头20通过接口30与待测器件(DUT)60通信。 Communication test head 20 via the interface 30 and the device under test (DUT) 60. DUT 60是待测试的各种集成电路元件。 DUT 60 are various integrated circuit components to be tested. 以此方式,可以迅速和同时地测试多个DUT 60。 In this way, you can quickly and simultaneously test multiple DUT 60. 此外,在测试了一组DUT60后,使用一个装卸装置5引入另一组DUT 60以进行测试。 In addition, after testing a set of DUT60, a handling device 5 is introduced using the other set of DUT 60 to be tested.

如图2和3所示,在DUT板80上排列多个DUT 60。 As shown in FIGS. 2 and 3, 80 are arranged in a plurality of DUT 60 on the DUT board. DUT板80(也称作插槽板、器件接口板和装载板)位于相应的板垫块40上,板垫块40放置在一个间隔框架50上。 DUT board 80 (also referred to as a slot plate, loading plate and a device interface board) located on a respective spacer plate 40, spacer plate 40 is placed on a spacer frame 50. 板垫块40是空心的以允许电缆70连接到DUT板80。 Board spacer 40 is hollow to allow the cable 70 is connected to the DUT board 80. 每个DUT 60通过DUT板80中的带焊接内衬的通孔83连接到相应电缆70,其实际连接是在焊点82。 Each DUT 60 is connected to cable 70 through the respective through holes 83 with solder lining of the DUT board 80, which is actually connected to the pad 82. 由此,每个电缆70分别焊接到DUT板80。 Thus, each cable 70 are soldered to the DUT board 80.

对于一个常规测试器1,当要测试一种新类型的DUT 60时,通过装卸装置5把该新DUT 60移动到测试器1并连接到一个测试插槽(未示出),完成测试头20和新DUT 60之间的电连接。 1 for a conventional test, when to test a new type of DUT 60, by the handling device 5 is moved to the new DUT 60 and the tester 1 is connected to a test socket (not shown), to complete the test head 20 and between the new DUT 60 electrical connections. 然后执行测试。 Then run the test. 在测试完成后,通过装卸装置5把DUT 60从测试插槽移开,并使用装卸装置5把一个相同类型的新DUT60安装到测试插槽中。 After the completion of the test, DUT 60 is removed by a handling device 5 from the test slot, and using a new handling device 5 is mounted to the same type DUT60 test socket.

如果要测试一个新类型的DUT 60,必须替换旧DUT板80并且把一个新DUT板80插入其位置。 To test a new type of DUT 60, the DUT board 80 must replace the old and the new DUT board 80 inserted in its place. 该新DUT板80将具有反映该新类型DUT 60的不同连接需要。 The new DUT board 80 is connected with different types reflect the new needs of DUT 60. 由此,或者是必须使用一个新的接口组件,或者是必须在不同的焊点82重新焊接电缆70。 Accordingly, or you must use a new interface component, or a different pad 82 must be re-welding cable 70. 在任何一种情况下,电缆70都要与用于待测试的每个新类型DUT 60的不同DUT板80进行定制装配。 In either case, the cable 70 must be used for different DUT board 60 for each new type of DUT 80 to be tested is assembled customized. 此外,在重新焊接电缆70时,DUT 60类型的每次改变都需要把接口组件(包括板垫块40)部分地或全部地拆卸,把电缆70焊接到新DUT板80的相应焊点82,并且把接口重新组装。 Further, when re-welding cable 70, each change in the type of DUT 60 are required to interface components (including the board spacer 40) partially or completely detached, the new cable 70 is soldered to the respective pads 80 of the DUT board 82, and the interface to reassemble. 另一方面,在替换整个接口组件时,必须为待测试的每种类型DUT 60储备大量接口组件。 On the other hand, when the replacement of the entire interface component, must reserve for each type of DUT 60 to be tested a large number of interface components.

这种焊接方式是有问题的,因为把电缆70连接到DUT板80的焊点82要耗费时间。 This welding is problematic, because the cable 70 is connected to the pad 82 of DUT board 80 takes time. 当DUT 60的密度和/或数量增加时,这个问题更加严重。 When increasing the density of the DUT 60 and / or the number, the problem is more serious. 例如,现代测试器可以容纳多达128个DUT 60/每个测试头20,每星期(甚至每天)DUT60的类型改变很多次。 For example, modern tester may accommodate up to 128 DUT 60 / head 20 for each test, per week (or even daily) type DUT60 change many times. 由此,对于待测试的DUT 60类型的每次改变,为执行接口的拆卸和组装以及用于把电缆70连接到不同类型DUT板80的定制焊接都需要大量时间和费用,而且显著地增加了测试DUT 60所需的时间量。 Thus, for each change in the type of DUT 60 to be tested, for the implementation of disassembly and assembly, and an interface for customizing the welding cable 70 is connected to a different type of DUT board 80 requires considerable time and expense, but also significantly increased the 60 DUT test the amount of time required.

如图4A所示,一种解决该焊接限制的方案是利用放置在相应pogo板110上的弹簧加载的pogo 100,例如由Everett Charles制造的pogo插头。 4A, a solution of the embodiment is the use of welding limitation placed on the respective pogo plate 110 of spring-loaded pogo 100, manufactured by Everett Charles pogo plug, for example. Pogo 100包括一个内部弹簧,该内部弹簧允许插头100的上半部偏压DUT板80上的焊盘90,由此形成一个到相应DUT 60的通信通路。 Pogo 100 includes an internal spring, which allows the internal spring biasing the plug 100 in the upper half of the pads on the DUT board 8090, thereby forming a communication path corresponding to the DUT 60. 使用该系统,当要测试一个新类型的DUT 60时,不必把电缆70焊接到DUT板80。 Using this system, when testing a new type of DUT 60, the cable 70 does not have to be welded to the DUT board 80. 而是使电缆70保持焊接到pogo板110,并且把新DUT板80放置在pogo板110上,使得插头100偏压相应的焊盘90以形成通信通路。 But the cable holder 70 is welded to the pogo plate 110, and the new DUT board 80 is placed on the pogo plate 110, such that the respective pads 100 biases the plug 90 to form a communication path. 由此,不必改变整个接口。 This eliminates the need to change the entire interface.

但是,随着所测试的DUT 60的数量和密度增加,这种方案也有问题。 However, with the increase being tested DUT 60 the number and density of this solution is also problematic. 随着所测试的DUT 60的密度增加,必须使用越来越小的pogo 100以便装配到DUT板80下的空间中。 With the increase of the density of the tested DUT 60 must be used for smaller and smaller pogo 100 fitted into the space 80 in the DUT board. 随着pogo 100变小,它们变得更加易损并且难以操作。 As pogo 100 becomes smaller, they become more vulnerable and difficult to handle. 此外,随着pogo 100变小,它们的冲程(即插头100的尖端为了偏压焊盘90而可以垂直行进的距离)降低,这意味着DUT板80和pogo板110必须制造得非常平以确保在所有焊盘90的连接。 Further, as pogo 100 becomes small, the stroke thereof (i.e., the tip of the plug 100 to be biased from the vertical travel of the pad 90) is reduced, which means that the DUT board 80 and the pogo plate 110 must be made very flat to ensure in all of connection pads 90. 这增加了pogo板110和DUT板80的制造成本。 This increases the manufacturing cost of the pogo plate 110 and the DUT board 80. 而且,pogo 100本身的使用非常昂贵。 Moreover, pogo 100 use itself is very expensive. 由此,在DUT 60的密度和/或数量增加时,pogo 100并不是焊接的一个理想替代。 Accordingly, when increasing the density of the DUT 60 and / or quantity, a pogo 100 is not welded over replacement.

当DUT 60是一个逻辑元件65时,如图4B和4C所示,已经知道使用插塞160执行低并行性测试。 When the DUT 60 is a logic element 65 when, as shown in FIG 4B and 4C, the plug 160 is known to use low-parallelism testing performed. 对于逻辑元件,电缆70被焊接到插塞160内的子插件板中。 For a logic element, the cable 70 is soldered to the plug within the daughtercard 160. 插塞160(例如FCI制造的Micopax插塞)由插塞支架180支持,并连接到相应插座170。 The plug 160 (e.g., plug manufactured Micopax FCI) supported by the plug frame 180, and 170 are connected to the corresponding receptacle. 插座170连接到逻辑板150。 Receptacle 170 is connected to the logic board 150. 以此方式,并不是直接把电缆70焊接到逻辑板150,而是使插塞160由位于逻辑板150上的插座170接纳。 In this manner, the cable 70 is not directly soldered to the logic board 150, but to make the plug 160 is received by the logic board is located on the socket 150 170. 不是所有插塞160都用于所测试的每种类型的逻辑元件65。 Not all of the logic elements of each type plugs 160 were tested for 65.

但是,已知这种结构用于逻辑元件65的低并行性测试,并且需要使用8个或更多个插塞160/每个逻辑板150。 However, such a structure is known for a low-parallelism testing of logic elements 65, and requires the use of eight or more plugs 160/150 per logic board. 这种结构不适于DUT的高密度、高并行性测试,尤其是在DUT是较小的器件(例如存储器件)时。 This structure is not suitable for DUT high-density, high-parallelism testing, especially in smaller devices DUT (e.g., memory device) is. 为了测试这些器件,DUT板较小,这防碍了使用大量插塞160。 To test these devices, the DUT board smaller, which hinders the use of a large number of plug 160. 此外,移动存储器件的装卸装置5(例如Advantest M65XX和M67XX系列的装卸装置)所使用的间隔框架的间距不允许使用大量插塞160以便测试这些器件。 Further, the pitch of the spacer frame handling device 5 (e.g., Advantest M65XX handling device and M67XX series) a removable memory device is not allowed to be used to test a large number of plugs 160 of these devices. 因此,对于存储器件的高并行性测试(即32个或更多器件的同时测试),常规插塞布置是不可能的。 Thus, for high-parallelism testing of memory devices (i.e., 32 or more testing devices simultaneously), the conventional plug is disposed interposed impossible.

发明内容 SUMMARY

本发明的一个目的是提供一种待测器件和测试头之间的连接系统,其提供对高数据率的待测器件的安全模块化连接而不会造成信号质量的降低。 An object of the present invention is to provide a connection system of the device under test and the test head between which offers without causing decreased signal quality of the modular safety device under test is connected to a high data rate.

本发明的另一个目的是提供一种待测器件和测试头之间的高密度、可升级的连接系统。 Another object of the present invention is to provide a high density connection system between devices under test and a test head, it can be upgraded.

本发明的其它目的和优点将部分地在后面的说明中给出,并且部分地可以从该说明中了解,或者通过本发明的实践获得。 Other objects and advantages of the invention will be set forth in part in the description which follows, and in part will be understood from the description, or learned by practice of the invention.

因此,为了实现这些和其它目的,本发明的一个实施例使用待测器件(DUT)和电缆之间的接口,该接口包括:第一板,具有第一连接器阵列,每个第一连接器连接到一个相应电缆;和第二板,保持该DUT并且具有多个第二连接器,每个第二连接器连接到该DUT和一个相应的第一连接器,其中第二连接器的数量小于第一连接器的数量。 Thus, to achieve these and other objects, an embodiment of the present invention using an interface between the device under test (DUT) and cables, the interface comprising: a first plate having a first connector array, each of the first connector connected to a respective cable; and a second plate, a plurality of holding the DUT and having second connectors, each second connector is connected to the DUT and a respective first connector, wherein the connector is less than the number of second the number of first connectors.

根据本发明的另一个实施例,第一连接器和第二连接器包括成对的头连接器和屏蔽控制的阻抗连接器。 According to another embodiment of the present invention, the first connector and the second connector comprises a pair of Impedance Connector connector and the shield control.

根据本发明的再一个实施例,第一连接器和第二连接器包括成对的焊盘,以允许第一板和第二板之间的板-板连接。 According to a further embodiment of the present invention, the first connector and the second connector comprises a pair of pads to allow the plate between the first plate and the second plate - plate connection.

根据本发明的另一个实施例,一种用于执行存储器件的高并行性测试的接口包括:第一板,保持其中一个存储器件并具有一个连接到该存储器件的插座;和一个插塞,连接到相应电缆和该插座以产生一个通信通路,其中第一板和插塞的组合允许存储器件的高并行性测试。 Interface according to another embodiment of the present invention, a high-parallelism testing of memory devices for execution comprising: a first plate, wherein a holding socket and having a memory device connected to the memory device; and a plug, and the respective cable connected to the outlet to produce a communication path, wherein the first plate and the combination of the plug allows for high-parallelism testing of memory devices.

根据本发明的再一个实施例,一种用于把DUT板上的DUT连接到电缆以进行测试的方法包括:把一个具有第一数量连接器的第一DUT板从一个板垫块上以阵列保持的相应电缆上拔下,并把一个具有与第一数量不同的第二数量连接器的第二DUT板插入电缆。 According to a further embodiment of the present invention, a method for connecting the DUT DUT board to cables for testing comprises of: a first DUT board having a first number of connectors in an array on a board spacer from Pull the respective cable held, and having a first number to a second number of connectors different from a second DUT board inserted cable.

根据本发明的再一个实施例,一种把DUT板上的DUT连接到电缆以进行测试的方法包括:把一个具有连接到第一DUT的多个第一焊盘的第一DUT板从一个具有连接到电缆的板焊盘的板垫块上除去,其中相应对的第一焊盘和板焊盘形成一个板-板连接,以产生用于电缆和第一DUT之间信号的第一通信通路;并把具有连接到第二DUT的多个第二焊盘的第二DUT板放置到板垫块上以形成一个板-板连接,以产生用于电缆和第二DUT之间信号的第二通信通路。 The method according to the present invention in a further embodiment, a DUT to DUT board to cables for testing the connection comprises: the first DUT board connected to a plurality of first pads having a first DUT having from a cable connected to the board pads on the board spacer is removed, the first pads and board pads which are formed on a respective plate - plate connected to generate a signal for a first communication between the cable and passage of the first DUT ; and the second DUT board having a plurality of second DUT coupled to the second pad is placed on the board to form a spacer plate - plate connected to generate a signal between the DUT and a second cable for a second communication path.

根据本发明的再一个实施例,一种把DUT板上的存储器件连接到电缆以进行存储器件的高并行性测试的方法包括:把具有第一插座的第一DUT板从一个连接到相应电缆的插塞上拔下;并把具有第二插座的第二DUT板插入该插塞以形成存储器件和电缆之间的通信通路,其中第二DUT板和插塞的组合允许存储器件的高并行性测试。 The method of high-parallelism testing of the present invention according to a further embodiment of a connecting device DUT board to cables for storage memory device comprising: the first DUT board having a first socket connected to a respective cable from the disconnect the plug; and the second DUT board having a second receptacle inserted into the plug to form a communication path between a memory device and a cable, wherein the combination of the second DUT board and the plug allows for highly parallel memory devices test.

附图说明 BRIEF DESCRIPTION

通过以下结合附图对优选实施例的说明,可以更清楚地了解本发明的这些和其它目的和优点,在附图中:图1是显示包括测试器体、测试头、装卸装置和待测器件(DUT)之间通信的常规测试器的示意图;图2是在DUT板和电缆之间的包括板垫块和间隔框架的常规焊接接口的侧剖视图;图3是用于单个DUT的电缆和DUT板之间的常规焊接的侧剖视图;图4A是使用安装在子插件板上的弹簧加载的pogo的DUT板和电缆之间的常规pogo接口的侧剖视图;图4B是逻辑板和电缆之间的常规插塞-插座接口的侧剖视图;图4C是显示径向排列的插座的常规逻辑板底视图;图5A是使用屏蔽控制的阻抗(SCI)连接器的根据本发明一个实施例的接口的前剖视图;图5B是使用SCI连接器的根据本发明一个实施例的接口的侧剖视图,显示出未使用所有的SCI连接器;图6A是根据本发明一个实施例的板垫块上的 By way of illustration of the preferred embodiment in conjunction with the following drawings, these will be more clearly understood and other objects and advantages of the present invention, in which: FIG. 1 is a graph showing a test device comprising a body, a test head and a handling device DUT a schematic view of a conventional communication between tester (DUT); FIG. 2 is a side cross-sectional view of a conventional welding interface board spacer includes the spacer frame and between the cable and the DUT board; FIG. 3 is a single cable and the DUT DUT conventional welding between the side sectional view of the plate; FIG. 4A is mounted using a spring-loaded plate daughterboard conventional pogo-side interface between the DUT board and the cable cross-sectional view of the pogo; FIG. 4B is between the logic board and cable conventional plug - side cross-sectional view of the socket interface; FIG. 4C is a conventional logic board radially arranged outlet bottom view of a display; FIG. 5A is a front interface according to the present invention, one embodiment of the shielded controlled impedance (SCI) connectors cross-sectional view; FIG. 5B is an SCI connector using a side cross-sectional view of one embodiment of an interface of the present invention, showing all the unused SCI connectors; FIG. 6A is a spacer plate according to the present invention, one embodiment of the SCI连接器的阵列的顶视图;图6B是显示根据本发明一个实施例的位于一个阵列孔中的SCI连接器的板垫块的侧剖视图;图7是显示使用插塞和插座把电缆连接到DUT板的根据本发明另一个实施例的接口的示意图;图8是显示根据本发明另一个实施例的连接到PCB的电缆的插塞剖视图;图9是显示使用弹性体以形成各个焊盘之间的导电通路的根据本发明另一个实施例的接口的示意图。 A top view of an array of SCI connector; FIG. 6B is a sectional view of a side of the SCI connector an array of holes in the board spacer according to one embodiment of the present invention; FIG. 7 is a graph showing the use of the plug and receptacle of the cable connected to a schematic view of an interface according to another embodiment of the present invention, the DUT board; FIG. 8 is a connector according to another embodiment of the present invention is inserted into the plug of the cable cross-sectional view of a PCB; FIG. 9 is a use of an elastomer to form individual pads of a schematic view of an interface according to another embodiment of the present invention, the conductive paths between.

具体实施方式 Detailed ways

下面参考附图中的例子对本发明优选实施例进行说明,在所有附图中相似标号表示相似元件。 The following example with reference to the accompanying drawings of the preferred embodiments of the present invention will be described, in the drawings like numerals refer to like elements. 下面参考附图描述实施例以解释本发明。 The embodiments are described below with reference to the accompanying drawings to explain the present invention.

对于图5A到6B中显示的本发明的一个实施例,屏蔽控制的阻抗(SCI)连接器220的阵列被布置在板垫块230中的连接器开口249中。 For one embodiment of the present invention shown in FIG 5A to 6B, an array of mask control impedance (SCI) connectors 220 are disposed in the connector plate spacer 230 in opening 249. 每个SCI连接器220连接到一个电缆70,电缆70通过板垫块230中的电缆开口247延伸。 Each SCI connector 220 is connected to a cable 70, cable 70 extends through an opening 247 in the plate 230 of the cable spacer. 形成阵列孔245的电缆开口247和连接器开口249的相对尺寸限制了SCI连接器220在X、Y和Z方向的移动,并且防止SCI连接器220被拉入接口中。 Array of apertures formed in the cable 245 and the connector opening 247 opposite the opening 249 limits the size of the SCI connector 220 movement in X, Y and Z directions, and prevents the SCI connector 220 is drawn into the connector. 阵列孔245被布置为板垫块230上的较大阵列240的一部分。 An array of apertures 245 are arranged on a larger array plate portion 240 of the spacer 230.

为了形成SCI连接器220和相应DUT 60之间的通信通路,在DUT板280上排列成组的头部210。 To form the SCI connector 220 and the communication paths between the respective DUT 60, the DUT board 280 in the head group 210 are arranged. 每个头部210包含头部连接器215,头部连接器215是成对的插头,每对插头具有一个信号插头和一个接地插头。 Each header 210 includes a header connector 215, header connector 215 is a pair of plugs, each plug having a pair of signal pins and a grounding plug. 来自一个相应电缆70的连接器220连接到一个头部连接器215。 From a respective cable 70 is connected to a head portion 220 connected to connector 215. 如图5A和5B所示,头部210被表面安装到DUT板280,并且连接到DUT板280上的相应的一个或多个DUT60(取决于其结构)。 5A and 5B, the head 210 is surface mounted to the DUT board 280, and is connected to a respective one or more of the DUT board 280 DUT60 (depending on its structure). 这些头部210和SCI连接器220在连接时,形成电缆70和相应DUT 60之间的通信通路。 These headers 210 and SCI connectors 220 at the connection, a communication path is formed between the cable 70 and the respective DUT 60.

通常,板垫块230具有完全填充的阵列240,这意味着阵列240中的每个阵列孔245都具有相应的SCI连接器220。 Typically, spacer plate 230 having a fully populated array 240, which means that each array of apertures 245 in the array 240 has a corresponding SCI connector 220. 反之,如图5B所示,DUT板280不总是需要使用所有的SCI连接器220,并且依据所要测试的DUT 60的类型,仅连接所选择的连接器220。 Conversely, as shown in FIG. 5B, the DUT board 280 is not always necessary to use all of the SCI connector 220, and based on the type of DUT 60 to be tested, and connecting only the selected connector 220. 由此,对于每个SCI连接器220,可以有或没有一个对应的头部连接器215。 Thus, for each SCI connector 220, with or without a corresponding header connector 215. 但是,对于每个头部连接器215,有一个对应的SCI连接器220。 However, for each of the header connector 215, a connector 220 corresponding SCI. 以此方式,板垫块230形成对多个DUT板280的模块化连接器。 In this manner, the spacer plate 230 is formed of a plurality of modular connector 280 in the DUT board. 对于所要测试的每个新类型的DUT 60,仅需要改变DUT板280,使得用于该DUT板280的头部210连接到所选择的SCI连接器220。 For each new type of DUT 60 to be tested, the DUT board 280 only needs to be changed, such a head plate 280 of the DUT 210 is connected to the selected SCI connector 220.

如图所示,SCI连接器220是一个2mm连接器,具有一个信号线和一个接地线。 As shown, the SCI connector 220 is a connector 2mm, having a signal line and a ground line. 这种2mm连接器220可以是WL Gore 2mm EYEOPENER电缆连接器,或来自3M的SCI连接器,其是1×22mm受控阻抗连接器。 This connector 220 may be 2mm WL Gore 2mm EYEOPENER cable connector, the connector or SCI from 3M, which is a 1 × 22mm controlled impedance connector. 类似地,头部210是表面安装技术2mm头部,其允许在每个DUT板280上使用60-70个头部连接器215。 Similarly, the head 210 is a head 2mm surface mount technology, which allows the use of 60-70 header connector 215 on each DUT board 280.

当然,应该理解,也有可能使用在相同连接器220的信号线和接地线之间,和/或相邻连接器220的信号线和接地线之间具有其它距离的连接器220(即其它间距)。 Of course, it should be understood that it is also possible to use between the signal line and a ground line 220 connected to the same, and / or between the signal line and a ground line connector 220 having adjacent 220 (i.e., other pitch) of the other connector distance . 例如,有可能使用具有1.27mm间距或2.54mm间距的连接器220。 For example, it is possible to use a connector having a pitch of 1.27mm or 2.54mm pitch 220.

此外,虽然所示的头部210被表面安装到DUT板280上,应该理解,可以使用通孔连接。 Moreover, although the head 210 is shown surface mounted to the DUT board 280, it should be understood that, via connection may be used. 此外还应该理解,尽管未示出,头部210和SCI连接器220可以颠倒,使得头部210位于阵列240中,而SCI连接器220被表面安装到DUT板280上。 It should also be appreciated that, although not shown, the head 210 and SCI connectors 220 may be reversed, so that the head 210 of the array 240, the SCI connector 220 is surface mounted to the DUT board 280. 无论如何配置,根据本发明优选实施例的接口都能够支持高于50MHz的频率的高速度和高保真度信号。 Anyway configuration, can support high-speed signals and high fidelity 50MHz higher than the frequency of the interface according to the preferred embodiment of the present invention.

图7和8显示本发明的另一个实施例。 7 and 8 show another embodiment of the present invention. 如图7所示,电缆70连接到插塞320,插塞320被插入插座310。 7, the cable 70 is connected to the plug 320, the plug 320 is inserted into the socket 310. 插座310被安装到DUT板380,DUT板380保持相应的一个或多个DUT 60(取决于其结构)。 Receptacle 310 is mounted to the DUT board 380, the DUT board 380 holding a respective DUT 60 or more (depending on its structure). DUT板380通过板垫块300由间隔框架50支持。 38050 DUT board supported by the spacer plate 300 by a spacer frame.

通常,使用螺钉、拉力销、一系列凸轮、或类似连接机构把插塞320连接到插座310。 Typically, using screws, tension pin, a series of cams, or the like connected to the plug means 320 connected to the socket 310. 但是,尽管未示出,也有可能构造一个板垫块以成阵列地支持和保持插塞320。 However, although not shown, it is also possible to construct a spacer plate support in an array and holding the plug 320.

如图8所示,插塞320包括插塞322,插塞322被跨骑安装(straddle-mount)连接到印刷电路板(PCB)323。 8, the plug 320 includes a plug 322, the plug 322 is straddle mounted (straddle-mount) is connected to a printed circuit board (PCB) 323. 插塞322和插座310对可以是一个市售的配件对,例如FCI提供的Micropax插塞/插座。 The plug 322 and the receptacle 310 pair can be a commercially available accessories pairs, for example to provide Micropax FCI plug / socket.

PCB 323包括内部导线326,内部导线326形成到对应电缆70的通信通路。 PCB 323 includes an inner conductor 326, inner conductor 326 is formed a communication path corresponding to the cable 70. 电缆70通过常规方法(例如焊接)连接到相应导线326。 Cable 70 is connected to a respective conductor 326 by a conventional method (e.g. welding). 使用电缆卡夹部件328支持电缆70,电缆卡夹部件328连接到用于保护该组件的壳体324。 Cable clip member 328 supports cable 70, the cable 328 is connected to the clip member 324 for protecting the housing assembly.

插座310还具有内部连接点(未示出),该内部连接点连接到插座导线315,插座导线315通向DUT 60。 Socket 310 also has an internal connection points (not shown), the inner conductor connection point is connected to the socket 315, the wires 315 leading to the socket DUT 60. 内部连接点和相关导线315的数量可以等于或少于一个相应插塞320的导线326/电缆70的数量,这取决于需要多少电缆70来测试一个特定类型的DUT 60。 Number of internal connection points and the associated conductor 315 may be equal to or less than a number of conductors 320 326/70 corresponding cable plug, depending on how many cables 70 need to test a particular type of DUT 60. 以此方式,相同插塞320可以用于各种DUT板380(DUT板380保持不同类型的DUT 60),其中通过选择性地连接到相应插塞320中的导线326来提供不同连接。 In this manner, the plug 320 may be used for the same variety of DUT board 380 (DUT board 380 hold different types of DUT 60), which is connected to a respective wire 320 in the plug 326 is provided by selectively connecting different.

此外,使用该结构,可以减少插塞320的数量,使得每个DUT板380使用一个或两个插塞320。 In addition, this configuration can reduce the number of the plug 320, such that each DUT board 380 using one or two plugs 320. 对于DUT 60是存储器件,并且对于空间限制已经防碍了插塞-插座连接的使用的情况,上述结果是非常希望的。 For the DUT 60 is a memory device, and has spatial limits hinders plug - in the case of using the socket connector, the above results are very desirable. 例如,对于一个M65XX和M67XX Advantest装卸装置,其能够递送32个器件/每个间隔框架(64个器件AD类型),但是其间距限制防碍了常规插塞结构的使用,此时上述接口是非常有用的。 For example, for a M65XX M67XX Advantest and handling device, which device is capable of delivering 32 / per frame interval (64 AD type devices), but using a conventional pitch limiting hinders plug structure, in which case the interface is above useful.

对于图9显示的本发明再一个实施例,板垫块500包括焊盘510的阵列。 For the present invention, Figure 9 shows a further embodiment, plate 500 includes an array of spacer pads 510. 每个焊盘510连接到一个相应电缆70。 Each pad 510 is connected to a respective cable 70. 保持DUT 60的板垫块480具有一个对应的焊盘490的阵列。 DUT 60 holding spacer plate 480 having a corresponding array of pads 490. 焊盘490的数量小于或等于板垫块500上的焊盘510的数量。 The number of pads 490 is less than or equal to the number of pads 510 on the board 500 of the spacer. 利用弹性体600把DUT板480连接到板垫块500,从而允许信号从焊盘510传递到焊盘490并传递到相应DUT 60。 An elastic member 600 connected to the DUT board 480 spacer plate 500, thereby allowing signal transfer from the pad 510 to the pad 490 and transmitted to the respective DUT 60. 弹性体600可以是由Shin-Etsu或Fujipoly提供的弹性体。 Elastomer 600 may be elastomeric provided by Shin-Etsu or Fujipoly. 应该理解,无需在所有应用中都使用弹性体60。 It should be understood, without having to use the elastomer 60 in all applications.

作为例子,为了使用图5A所示根据本发明实施例的接口测试一个不同类型的DUT 60,把用于第一类型DUT 60的DUT板280从板垫块230上拔下,并且把用于一个新类型DUT 60的DUT板280插入板垫块230。 By way of example, to use a different type of DUT FIG interface according to Test Example 60 of the present invention shown in FIG. 5A, the DUT board 280 for a first type of DUT 60 is disconnected from the spacer plate 230, and to put a the new type of DUT 60 of DUT board 280 is inserted into plate 230 spacer. 用于新类型DUT60的DUT板280可能在如图5A所示各个头部210中的尖端215的对数方面有不同布置,或者可能被布置为不被与连接器220同样多的尖端215完全填充。 For a new type of DUT board 280 may DUT60 5A, the tip 210 of each head portion 215 has a different arrangement of the several areas, or may be arranged so as not to be similar to the connector 220 and more complete filling of the tip 215 .

由此,根据本发明的优选实施例,可以使用公共板垫块或连接方案,这允许在一个测试器中互换容纳不同类型DUT的DUT板而无需把电缆重新布线和连接到DUT板上的相应DUT。 Thus, according to a preferred embodiment of the present invention, it may use a common spacer plate or connection scheme, which allows a tester interchangeably accommodate different types of DUT DUT board without rewiring the cable connected to the DUT board corresponding DUT. 反之,可以允许使用在板垫块上或在插塞中排列的预定连接点来形成到电缆的连接。 Conversely, may allow on board spacer or at predetermined connection points of the plug are formed to be arranged in the connecting cable.

尽管已经显示和描述了本发明的少量优选实施例,本领域技术人员应该理解,在不偏离本发明精神和原理的条件下,可以进行改变,本发明的范围由权利要求及其等同物定义。 While there have been shown and described with a small number of preferred embodiments of the present invention, those skilled in the art will appreciate, without departing from the spirit and principles of the invention, changes may be made, the scope of the present invention is defined in the claims and their equivalents.

从上述可以看出,根据本发明,可以提供一种待测器件和测试头之间的连接系统,其提供了对高数据率的待测器件的安全模块化连接而不会造成信号质量的降低。 As can be seen from the above, in accordance with the present invention, the system may provide a connection between a device under test and the test head, which provides a reduced modular safety device under test is connected to a high data rate without causing signal quality .

Claims (17)

  1. 1.一种待测器件和电缆之间的接口,包括:第一板,具有第一连接器阵列,每个第一连接器连接到一个相应电缆;和第二板,保持该待测器件并且具有多个第二连接器,每个第二连接器连接到该待测器件和一个相应的第一连接器,其中第二连接器的数量小于第一连接器的数量。 An interface between the cable and the device under test, comprising: a first plate having a first connector array, each of the first connector is connected to a respective cable; and a second plate, and holding the device under test having a plurality of second connectors, each second connector is connected to the device under test and a respective first connector, the second connector wherein the number smaller than the number of the first connector.
  2. 2.根据权利要求1所述的接口,其中在第一和第二连接器之间形成的每个连接形成了用于具有至少50MHz频率的信号的通信通路。 2. The interface of claim 1, wherein each connection between the first and second connector forms a communication path formed by a signal having a frequency of at least 50MHz.
  3. 3.根据权利要求1所述的接口,其中第一连接器包括一个屏蔽控制的阻抗连接器;和第二连接器包括一个头部。 3. The interface of claim 1, wherein the first connector comprises a shielded controlled impedance connector; and a second connector comprises a header.
  4. 4.根据权利要求1所述的接口,其中第一连接器包括一个头部;和第二连接器包括一个屏蔽控制的阻抗连接器。 4. The interface of claim 1, wherein the first connector comprises a head portion; and a second connector comprises a shielded controlled impedance connector.
  5. 5.根据权利要求3所述的接口,其中第一和第二连接器包括成对的2mm连接器和头部。 5. The interface of claim 3, wherein the first and second connectors comprises a pair of header connectors and 2mm.
  6. 6.根据权利要求4所述的接口,其中第一和第二连接器包括成对的2mm连接器和头部。 6. Interface according to claim 4, wherein the first and second connectors comprises a pair of header connectors and 2mm.
  7. 7.根据权利要求1所述的接口,其中第二连接器在所述第二板上以阵列形式成行布置。 7. The interface of claim 1, wherein the second connector disposed in the second row in an array plate.
  8. 8.根据权利要求7所述的接口,其中第二连接器被保持在所述第二板中的阵列的相应阵列孔中。 8. The interface of claim 7, wherein the second connector is held in a respective array of said array of apertures in the second plate.
  9. 9.根据权利要求8所述的接口,其中第一连接器包括一个头部;和第二连接器包括一个屏蔽控制的阻抗连接器。 9. The interface of claim 8, wherein the first connector comprises a head portion; and a second connector comprises a shielded controlled impedance connector.
  10. 10.根据权利要求9所述的接口,其中在第一和第二连接器之间形成的每个连接形成了用于具有至少50MHz频率的信号的通信通路。 10. The interface of claim 9, each connected to form a communication path for signals having a frequency of at least 50MHz wherein between the first and second connectors formed.
  11. 11.根据权利要求10所述的接口,其中第一和第二连接器具有信号线和接地线,并且在相邻信号线和接地线之间的间距等于或小于2.54mm。 11. The interface of claim 10, wherein the first and second connectors have signal and ground lines, and the spacing between adjacent signal and ground lines is equal to or less than 2.54mm.
  12. 12.根据权利要求11所述的接口,其中第一和第二连接器包括成对的2mm连接器和头部。 12. Interface as claimed in claim 11, wherein the first and second connectors comprises a pair of header connectors and 2mm.
  13. 13.根据权利要求11所述的接口,其中第一和第二连接器包括成对的1.27mm连接器和头部。 13. Interface according to claim 11, wherein the first connector and the second connector includes a pair of 1.27mm and a head.
  14. 14.根据权利要求1所述的接口,其中第一和第二连接器包括多个焊盘,其中使焊盘汇集到一起以形成用于从电缆到相应待测器件的信号的通信通路。 14. The interface of claim 1, wherein the first and second connector comprises a plurality of pads, wherein the pad pooled together to form a communication path for signals from the cable to the respective device under test.
  15. 15.根据权利要求14所述的接口,进一步包括设置在第一和第二连接器之间的弹性体。 15. The interface of claim 14, further comprising an elastic member disposed between the first and second connectors.
  16. 16.根据权利要求15所述的接口,其中在第一和第二连接器之间形成的每个连接形成了用于具有至少50MHz频率的信号的通信通路。 16. The interface of claim 15, each connected to form a communication path for signals having a frequency of at least 50MHz wherein between the first and second connectors formed.
  17. 17.根据权利要求16所述的接口,其中第二连接器在所述第二板上以阵列形式成行设置。 17. The interface of claim 16, wherein the second connector is provided on the second row in an array plate.
CN 02800678 2001-03-15 2002-03-13 Universal test interface between device under test and test head CN1314976C (en)

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WO2002075330A2 (en) 2002-09-26 application
KR20030024668A (en) 2003-03-26 application
CN1975440A (en) 2007-06-06 application
US20020130653A1 (en) 2002-09-19 application
US6552528B2 (en) 2003-04-22 grant
WO2002075330A3 (en) 2003-12-04 application
US20030090259A1 (en) 2003-05-15 application
CN1494659A (en) 2004-05-05 application
US20050040811A1 (en) 2005-02-24 application
US6822436B2 (en) 2004-11-23 grant

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