CN1312758C - CMOS element with strain equilibrium structure and making method thereof - Google Patents
CMOS element with strain equilibrium structure and making method thereof Download PDFInfo
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- CN1312758C CN1312758C CNB021316112A CN02131611A CN1312758C CN 1312758 C CN1312758 C CN 1312758C CN B021316112 A CNB021316112 A CN B021316112A CN 02131611 A CN02131611 A CN 02131611A CN 1312758 C CN1312758 C CN 1312758C
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Abstract
The present invention relates to a CMOS element with a strain equilibrium structure and a making method of the CMOS element. The making method comprises the following steps: firstly, providing a substrate having an insulating layer with a silicon layer; secondly, growing a silicon germanium layer on the silicon layer, wherein the silicon layer is under a biaxial extending strain situation and the silicon germanium layer is under a biaxial compressing strain situation to obtain the strain equilibrium structure; thirdly, forming a second silicon layer on the silicon germanium layer, wherein the second silicon layer is provided with first thickness which is suitable for a PMOS element and second thickness which is suitable for an NMOS element; then, performing a pattern making process for the substrate for defining a PMOS element zone and an NMOS element zone and forming a brake electrode insulation layer on the second silicon layer; finally, forming a brake pole electrode on the brake pole insulation layer.
Description
Technical field
The present invention relates to a kind of field-effect transistor, particularly a kind of CMOS (CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor) element and manufacture method thereof that has the n pass element of tensile-strained silicon layer and have the p pass element of compression strain germanium-silicon layer.
Background technology
With the downsizing of work grid element size, make mos field effect transistor (MOSFET) element can be under low operating voltage, having tend to act electric current and usefulness at a high speed of height is suitable difficulty.Therefore, many people are in the method for making great efforts to seek to improve the usefulness of burning compound semiconductor field effect transistor element.
The band structure modification of utilizing strain to cause increases the mobility of carrier, to increase the electric current of tending to act of field-effect transistor, can improve the usefulness of field effect transistor element, and this kind method has been applied in the various elements.The silicon passage of these elements is the situations that are in biaxial stretch-formed strain.
Increase mobility (the K.Ismail et al. of electronics in the situation that existing research is pointed out to utilize the silicon passage to be in biaxial stretch-formed strain, " Electron transport properties in Si/SiGe heterostructures:Measurements and device applications ", Appl.Phys.Lett.63, pp.660,1993.), and utilize the SiGe passage is in increases electric hole in the situation of biaxial compressive strain mobility (D.K.Nayak et al., " Enhancement-mode quantum-well GeSi PMOS ", IEEE Elect.Dev.Lett.12, pp.154,1991).Yet, be difficult to reach in conjunction with the NMOSFETs (N type metal oxide semiconductor field-effect transistor) of silicon passage and CMOS process technique with PMOSFETs (P-type mos field-effect transistor) of the SiGe passage of biaxial compressive strain with biaxial stretch-formed strain.Many strained layer manufacture methods (K.Ismail et al. such as utilizing thick resilient coating or complex multilayer is arranged in transistorized manufacturing, IBM, Jul.1996, Complementary metal-oxidesemiconductor transistor logic using strained Si/SiGe heterostructure layers, U.S.Patent No.5534713.), these methods are not readily integrated in traditional CMOS processing procedure.
Therefore, have the tend to act mos field effect transistor element of electric current and high speed usefulness of height, demand seeking the road of improvement urgently at the problems referred to above in order to make.
Summary of the invention
The object of the present invention is to provide a kind of cmos element structure and manufacture method thereof with strain equilibrium structure, it utilizes and forms the strain equilibrium structure that has the n pass element of tensile-strained silicon layer and have the p pass element of compression strain germanium-silicon layer, to promote the usefulness of field effect transistor element.
Purpose of the present invention can realize by following measure:
A kind of manufacture method with cmos element of strain equilibrium structure at first provides the substrate that silicon layer (SOI) arranged on the insulating barrier.Secondly, the germanium-silicon layer of on this silicon layer, growing up, wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure.Now forms one second silicon layer on this germanium-silicon layer, this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.Then, implement patterning process to define a PMOS element region and a NMOS element region for this substrate.Moreover, on this second silicon layer, form gate insulator.At last, on this gate insulator, form a gate electrode.
Said method also be included in before or after this germanium-silicon layer of growing up by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
The formation method of the second above-mentioned silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a mask layer in the PMOS zone;
Grow up this second silicon layer to this two thickness at the exposed region selective epitaxial that does not cover this mask layer; And
Remove this mask layer.
Above-mentioned mask layer is an one silica layer.
Above-mentioned this first thickness is 20 dusts.
The second above-mentioned thickness is 100 dusts.
Above-mentioned gate insulator uses chemical vapour deposition technique deposition one silica layer.
This germanium-silicon layer of above-mentioned growth is to use the selective epitaxial method.
The mole fraction of germanium is between 0.1 to 0.5 in the above-mentioned germanium-silicon layer.
A kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this germanium-silicon layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this second germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulator; And
On this gate insulator, form a gate electrode.
For having on the above-mentioned insulating barrier germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
The formation method of germanium-silicon layer substrate is arranged on this above-mentioned insulating barrier, comprise the following steps:
The semiconductor substrate is provided;
Form a buried insulation layer and a silicon layer on this semiconductor-based end, wherein this silicon layer is formed at the top of this buried insulation layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
The thickness of this above-mentioned silicon layer is less than 100 dusts.
The formation method of the second above-mentioned silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a mask layer in the PMOS zone;
Grow up this second silicon layer to this two thickness at the exposed region selective epitaxial that does not cover this mask layer; And
Remove this mask layer.
Above-mentioned mask layer is an one silica layer.
Above-mentioned this first thickness is 20 dusts.
The second above-mentioned thickness is 100 dusts.
Above-mentioned gate insulator is to use chemical vapour deposition technique deposition one silica layer.
This second germanium-silicon layer of above-mentioned growth is to use the selective epitaxial method.
Purpose of the present invention also realizes by following measure:
A kind of cmos element with strain equilibrium structure comprises: on the insulating barrier silicon layer is arranged; One germanium-silicon layer, on the silicon layer on this insulating barrier of growing up, wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure; One second silicon layer is grown up on this germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element; One gate insulator is formed on this second silicon layer; And a gate electrode, be formed on this gate insulator.
The first above-mentioned thickness is 20 dusts.
The second above-mentioned thickness is 100 dusts.
Above-mentioned gate insulator is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure comprises:
The substrate of germanium-silicon layer is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in the substrate of the germanium-silicon layer on this insulating barrier, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than the substrate of this germanium-silicon layer, make that the substrate of this germanium-silicon layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this second germanium-silicon layer, and wherein this second low layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulator is formed on this second silicon layer; And
One gate electrode is formed on this gate insulator.
For the substrate that germanium-silicon layer is arranged on the above-mentioned insulating barrier is to ignore between this insulating barrier and this germanium-silicon layer interface not to be easy to as big as you please adjust.
Above-mentioned this first thickness is 20 dusts.
Above-mentioned this second thickness is 100 dusts.
Above-mentioned gate insulator is to use chemical vapour deposition technique deposition one silica layer.
The present invention has following advantage compared to existing technology:
Utilization of the present invention has the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, make semiconductor film layer be under the elongation strain situation, and the semiconductor film layer that has than the macrolattice constant is to be under the compression strain situation with less lattice constant; Thereby the transistorized usefulness of the stack layer structure of being made up of silicon layer with different lattice constants and germanium-silicon layer is increased.
Description of drawings
Fig. 1 to Fig. 8 represents the processing procedure profile according to the cmos element with strain equilibrium structure of embodiments of the invention 1.
Fig. 9 to Figure 11 represents according to the flatten processing procedure profile of cmos element of weighing apparatus structure of having of embodiments of the invention 2.
Embodiment
Embodiment 1:
The invention provides a kind of cmos element structure and manufacture method thereof with strain equilibrium structure.Principle of the present invention is to use to have the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, the semiconductor film layer that has than macrolattice at relaxed state is to be under the compression strain situation, and the semiconductor film layer with less lattice constant is under the elongation strain situation, and then forms one and have strain equilibrium structure.For example, the stack layer structure that one silicon layer and a germanium-silicon layer are formed, under the interaction at relaxed state between silicon layer with different lattice constants and germanium-silicon layer, wherein germanium-silicon layer is to be under the biaxial compressive strain situation and silicon layer is under the biaxial stretch-formed strained situation.
Strain equilibrium structure can be made by the method for aftermentioned explanation, at first please refer to Fig. 1, in semiconductor substrate 10, form a buried insulation layer 11 and semi-conductor layer 12, present embodiment is then there to be silicon layer (silicon-on-insulator on the insulating barrier, SOI) wafer is an example, in order to as parent material, can utilize and implant oxygen (SIMOX) or SmartCut
Technology obtains isolating, but not as restriction.Semiconductor layer 12 generally is the silicon materials of about 200 of thickness.Buried insulation layer 11 is made of silica.Afterwards, epitaxial growth one germanium-silicon layer 14 on silicon layer 12, as shown in Figure 2, the thickness t 2 of germanium-silicon layer 14 is quite to make silicon layer 12 be under the biaxial stretch-formed strained situation with the thickness t 1 of silicon layer 12, and germanium-silicon layer 14 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Then, epitaxial growth one second silicon layer 16 on germanium-silicon layer 14, as shown in Figure 3, the thickness t 3 of second silicon layer 16 will quite make second silicon layer 16 be under the biaxial stretch-formed strained situation with the thickness t 1 of silicon layer 12 and the thickness t 2 of germanium-silicon layer 14.
In the situation of p pass element, the thickness t 3 of second silicon layer 16 must be enough thin, as 20 dusts, make and when element is opened, can not form parasitic capacitance therein, and the thickness t 2 of germanium-silicon layer 14 must be enough thick, as 100 dusts, make it can hold most movable carrier (Y.-C.Yeo et al., " Enhancedperformance in sub-100 nm CMOSFETs using strained epitaxialsilicon-germanium ", IEEE International Electron Device Meeting TechnicalDigest, pp.753-756, San Francisco, CA, Dec.2000.).And germanium-silicon layer 14 is under the biaxial compressive strain situation and can significantly increase transport property (the S.Kaya et al in electric hole, " Indication of velocity overshoot in strained Si 0.8Ge 0.2 p-channelMOSFETs ", Semiconductor Science and Technology.Vol.15, pp.573,2000.).Si
(1-x)Ge
(x)The enough high usefulness of the mole fraction x palpus of Ge in the layer 14 with enhancement p pass element, but can not too highly connect the face leakage current and prevent the strain relaxation problem with control.Si
(1-x)Ge
(x)The mole fraction x of Ge in the layer 14 can be between 0.1 to 0.5.
In the situation of n pass element, second silicon layer 16 is to use as passage, because second silicon layer 16 is under the biaxial stretch-formed strained situation and can significantly increases mobility and transport property (Rim K.etal., " Fabrication and analysis of deep submicron strained-Si n-MOSFETs ", IEEETrans, Elect.Dev., vol.47, no.7, pp.1406, Jul.2000.).Second silicon layer 16 must be enough thick in the thickness t 3 in nmos area territory, makes it can hold the most movable carrier of n pass element as 100 dusts.
About the thickness demand of second silicon layer 16 for n pass element and p pass element, for the p pass element, the thickness t 3 of second silicon layer 16 must be enough thin, as 20 dusts, to prevent forming parasitic capacitance in the PMOS element.For the n pass element, the thickness t 3 in nmos area territory must be enough thick, as 100 dusts, makes it can hold the most reversed charge of n pass element (electronics).Make second silicon layer 16 can have two thickness, can reach by following method, second silicon layer 16 of the growth thickness t 3a in the CMOS processing procedure of elder generation, then, cover a mask layer 18 in the PMOS zone, as silicon oxide layer, then grow up second silicon layer 16 to thickness t 3b, as shown in Figure 4 at CMOS institute area exposed selective epitaxial again.
Afterwards, please refer to Fig. 5, remove mask layer 18.Secondly, carry out the processing procedure of general cmos element again, at first as shown in Figure 6, define PMOS element region and NMOS element region by patterning process.
Then, please refer to Fig. 7, on second silicon layer 16, form gate insulator 22, for example use chemical vapour deposition technique silicon oxide layer deposited on second silicon layer 16.
At last, please refer to Fig. 8, on gate insulator 22, form gate electrode 24, carry out n type and p type ion doping (not shown) in the p-well area and the n-well area of gate electrode 24 both sides respectively again, and form clearance wall 26 at the sidewall of gate electrode 24, for example use chemical vapor deposition method to form silicon nitride layer as clearance wall 26.
It is noted that, in above-mentioned strain equilibrium structure, must be unconstrained as much as possible at the interface of 12 of insulating barrier 11 and silicon layers so that silicon layer 12 can change its lattice constant.Make the interface of 12 of insulating barrier 11 and silicon layers be easy to as much as possible adjust so that silicon layer 12 can change its lattice constant, can be by implanted atom to interrupt or the bond of lax insulating barrier 11 and 12 interfaces of silicon layer.Said method can be in the front or rear execution of epitaxial growth germanium-silicon layer 14.
Feature of the present invention is to utilize to have the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, make semiconductor film layer be under the elongation strain situation, and the semiconductor film layer that has than the macrolattice constant is to be under the compression strain situation with less lattice constant.Apparently, this strain equilibrium structure does not limit and uses above-mentioned three-decker, have silicon/SiGe/... .. silicon/SiGe/Si/silicon dioxide or SiGe/Si/... .. the two-layer at least above structure of SiGe/Si/SiGe/silicon dioxide can realize the present invention.Moreover applied material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
By among Fig. 8 as can be seen, have the compression strain germanium-silicon layer and can significantly increase the transport property in electric hole to increase the electric current of tending to act of p pass element, can produce the tend to act electric current of velocity of electrons effect at full speed and have tensile-strained silicon layer, and then promote the usefulness of field effect transistor element with increase n pass element.
Embodiment 2:
In the embodiment of the invention 2, the formed germanium-silicon layer that has the silicon layer of elongation strain and have compression strain is whether the interface of ignoring 12 of insulating barrier 11 among the embodiment 1 and silicon layers is easy to adjust as big as you please.
At first please refer to Fig. 9, form a buried insulation layer 61 and a germanium-silicon layer 62 in semiconductor substrate 60, present embodiment is then to have the wafer of germanium-silicon layer as parent material on the insulating barrier.The Ge content of germanium-silicon layer 62 is x1 and thickness is t6.Buried insulation layer 61 is made of silica.Present embodiment still has another to be chosen as, and as parent material, forms a buried insulation layer 91 and a silicon layer 92 with the wafer that on the insulating barrier silicon layer arranged in semiconductor substrate 90, and the thickness of silicon layer 92 is less than 100 .Buried insulation layer 91 is made of silica.Afterwards, epitaxial growth one germanium-silicon layer 94 on silicon layer 92 utilizes diffusion process that germanium is diffused into silicon layer 92 and the interface of the silicon oxide layer 91 that arrives, to change regional bond afterwards again, and the substrate (SlGe-on-insulator) of germanium-silicon layer is arranged on the formation insulating barrier, as shown in figure 10.Because germanium diffuses to the interface of silicon oxide layer 91, make the lattice constant of initial silicon layer 92, the mole fraction of the germanium of germanium-silicon layer 92 is x1, so can form the Si of similar germanium-silicon layer 62
(1-x1)Ge
(x1)Layer.
Please refer to Figure 11 afterwards, at Si
(1-x1)Ge (
X1)The layer 62 or 94 (for the purpose of simplified illustration, below only with Si
(1-x1)Ge
(x1)Layer 62 is done representative and is illustrated) last epitaxial growth 1 the 2nd Si
(1-x2)Ge
(x2)Layer 64, wherein the 2nd Si
(1-x2)Ge
(x2)Layer 64 Ge content is x2 and thickness is t7.The 2nd Si
(1-x2)Ge
(x2)The mole fraction x2 of layer 64 germanium is greater than x1, so makes the 2nd Si
(1-x2)Ge
(x2)Layer 64 is under the biaxial compressive strain situation.This strain intensity is equivalent to (pseudomorphical) Si of growth one pseudomorphic crystal on a silicon matrix layer
[1-(x2-x1)]Ge
(x2-x1)The layer, and the interface bond of this silicon matrix layer and insulating barrier (silicon oxide layer) be firm and be not be easy to as big as you please the adjustment.Yet, this 2nd Si
(1-x2)Ge
(x2)Layer 64 is under the biaxial compressive strain situation, and whether the interface bond of ignoring 62 of insulating barrier 61 and silicon layers is easy to adjust as big as you please.
Then, epitaxial growth one second silicon layer 16 on second germanium-silicon layer 64, as shown in Figure 3, this strain intensity is equivalent at a Si
(1-x1)Ge
(x1)The silicon layer of growth one pseudomorphic crystal on the hypothallus, and this Si
(1-x1)Ge
(x1)The interface bond of hypothallus and insulating barrier (silicon oxide layer) is firm and be not to be to be easy to as big as you please adjust.If Si
(1-x1)Ge
(x1)The interface bond of hypothallus and insulating barrier (silicon oxide layer) is to be easy to as big as you please wholly or in part adjust, and then the elongation strain degree of the superiors' silicon layer can reduce.Yet this second silicon layer 66 (the superiors' silicon layer) is to be under the biaxial stretch-formed strained situation, and whether the interface bond of ignoring 62 of insulating barrier 61 and silicon layers is easy to adjust as big as you please.
In sum, in the explanation of present embodiment 2, can form silicon layer with elongation strain and germanium-silicon layer, and whether the interface of ignoring 62 of buried insulation layer (silicon oxide layer) 61 and bottom silicon layers is easy to as big as you please adjust with compression strain.Because second silicon layer 66 also must have two thickness for the thickness demand of n pass element and p pass element, so, carry out every fabrication steps and program, to finish the making of cmos element with last embodiment then according to Fig. 4 to Fig. 8.Moreover applied material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
The present invention still proposes a kind of cmos element with strain equilibrium structure, and as shown in Figure 8, this cmos element has following each element.First element is that silicon layer substrate 10 is arranged on the insulating barrier.
Second element is that a germanium-silicon layer 14 is to use the said method epitaxial growth on silicon layer 12, and wherein silicon layer 12 is under the biaxial stretch-formed strained situation, and germanium-silicon layer 14 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Three element is one second silicon layer 16, grows up in germanium-silicon layer 141, and wherein second silicon layer 16 has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.
This cmos element still has following each element: a gate insulator 22 is formed on second silicon layer 16; One gate electrode 24 is formed on the gate insulator 22.
The present invention proposes a kind of cmos element with strain equilibrium structure in addition, and as shown in Figure 8, this cmos element has following each element.First element is that germanium-silicon layer substrate 60 is arranged on the insulating barrier, and insulating barrier 61 is ignored in this substrate 60 and whether 62 interfaces of germanium-silicon layer are easy to adjust as big as you please.
Second element is that one second germanium-silicon layer 64 is to use the said method epitaxial growth on germanium-silicon layer 62, wherein the mole fraction of the germanium of second germanium-silicon layer 64 is greater than germanium-silicon layer 62, make germanium-silicon layer 62 be under the biaxial stretch-formed strained situation and second germanium-silicon layer 64 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Three element is one second silicon layer 66, grows up on second germanium-silicon layer 64, and wherein second silicon layer 66 has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.
This cmos element still has following each element: a gate insulator 22 is formed on second silicon layer 16; One gate electrode 24 is formed on the gate insulator 22.
Applied material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; change and retouching when doing, so protection scope of the present invention is as the criterion with the scope of claim.
Claims (28)
1, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that silicon layer is arranged on one insulating barrier is provided;
Growth one germanium-silicon layer on this silicon layer, wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulator; And
On this gate insulator, form a gate electrode.
2, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1, it is characterized in that also being included in grow up before or after this germanium-silicon layer by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
3, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that the formation method of described second silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a mask layer in the PMOS zone;
Grow up this second silicon layer to this second thickness at the exposed region selective epitaxial that does not cover this mask layer; And
Remove this mask layer.
4, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 3 is characterized in that described mask layer is an one silica layer.
5, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described this first thickness is 20 dusts.
6, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described second thickness is 100 dusts.
7, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described gate insulator uses chemical vapour deposition technique deposition one silica layer.
8, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that this germanium-silicon layer of described growth is to use the selective epitaxial method.
9, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1, the mole fraction that it is characterized in that germanium in the described germanium-silicon layer is between 0.1 to 0.5.
10, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this germanium-silicon layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this second germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulator; And
On this gate insulator, form a gate electrode.
11, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that for having on this insulating barrier the germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
12, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that having on described this insulating barrier comprising the following steps: the formation method of germanium-silicon layer substrate
The semiconductor substrate is provided;
Form a buried insulation layer and a silicon layer on this semiconductor-based end, wherein this silicon layer is formed at the top of this buried insulation layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
13, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 12, the thickness that it is characterized in that described this silicon layer is less than 100 dusts.
14, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that comprising the following steps: the formation method of described second silicon layer
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a mask layer in the PMOS zone;
Grow up this second silicon layer to this second thickness at the exposed region selective epitaxial that does not cover this mask layer; And
Remove this mask layer.
15, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 14 is characterized in that described mask layer is an one silica layer.
16, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that described this first thickness is 20 dusts.
17, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that described second thickness is 100 dusts.
18, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that described gate insulator is to use chemical vapour deposition technique deposition one silica layer.
19, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 10 is characterized in that this second germanium-silicon layer of described growth is to use the selective epitaxial method.
20, a kind of cmos element with strain equilibrium structure comprises:
On one insulating barrier silicon layer is arranged;
One germanium-silicon layer, on the silicon layer on this insulating barrier of growing up, wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulator is formed on this second silicon layer; And
One gate electrode is formed on this gate insulator.
21, the cmos element with strain equilibrium structure as claimed in claim 20 is characterized in that described first thickness is 20 dusts.
22, the cmos element with strain equilibrium structure as claimed in claim 20 is characterized in that described second thickness is 100 dusts.
23, the cmos element with strain equilibrium structure as claimed in claim 20 is characterized in that described gate insulator is to use chemical vapour deposition technique deposition one silica layer.
24, a kind of cmos element with strain equilibrium structure comprises:
The substrate of germanium-silicon layer is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in the substrate of the germanium-silicon layer on this insulating barrier, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than the substrate of this germanium-silicon layer, make that the substrate of this germanium-silicon layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this second germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulator is formed on this second silicon layer; And
One gate electrode is formed on this gate insulator.
25, the cmos element with strain equilibrium structure as claimed in claim 24 is characterized in that for the substrate that germanium-silicon layer is arranged on this insulating barrier it being to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
26, the cmos element with strain equilibrium structure as claimed in claim 24 is characterized in that described this first thickness is 20 dusts.
27, the cmos element with strain equilibrium structure as claimed in claim 24 is characterized in that described this second thickness is 100 dusts.
28, the cmos element with strain equilibrium structure as claimed in claim 24 is characterized in that described gate insulator is to use chemical vapour deposition technique deposition one silica layer.
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| US7993998B2 (en) * | 2008-03-06 | 2011-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS devices having dual high-mobility channels |
| US20100109044A1 (en) * | 2008-10-30 | 2010-05-06 | Tekleab Daniel G | Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer |
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| US4710788A (en) * | 1985-11-30 | 1987-12-01 | Licentia Patent-Verwaltungs-Gmbh | Modulation doped field effect transistor with doped Six Ge1-x -intrinsic Si layering |
| US5155571A (en) * | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
| US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| US6111267A (en) * | 1997-05-13 | 2000-08-29 | Siemens Aktiengesellschaft | CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer |
| CN1366711A (en) * | 2000-02-17 | 2002-08-28 | 皇家菲利浦电子有限公司 | Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same |
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2002
- 2002-09-11 CN CNB021316112A patent/CN1312758C/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4710788A (en) * | 1985-11-30 | 1987-12-01 | Licentia Patent-Verwaltungs-Gmbh | Modulation doped field effect transistor with doped Six Ge1-x -intrinsic Si layering |
| US5155571A (en) * | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
| US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| US6111267A (en) * | 1997-05-13 | 2000-08-29 | Siemens Aktiengesellschaft | CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer |
| CN1366711A (en) * | 2000-02-17 | 2002-08-28 | 皇家菲利浦电子有限公司 | Semiconductor device with integrated CMOS circuit with MOS transistors having silicon-germanium (Sil-Gex) gate electrodes, and method for manufacturing same |
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