CN1482673A - CMOS element with strain equilibrium structure and making method thereof - Google Patents
CMOS element with strain equilibrium structure and making method thereof Download PDFInfo
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- CN1482673A CN1482673A CNA021316112A CN02131611A CN1482673A CN 1482673 A CN1482673 A CN 1482673A CN A021316112 A CNA021316112 A CN A021316112A CN 02131611 A CN02131611 A CN 02131611A CN 1482673 A CN1482673 A CN 1482673A
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Abstract
The invention discloses a CMOS element having strain balancing arrangement and method for manufacturing the same comprising, providing a substrate having an insulation layer with silicon layer, growing a silicon germanium layer on the silicon layer, forming a second silicon layer on the silicon germanium layer, wherein the second silicon layer has a first thickness adapted for a PMOS element, and a second thickness adapted for a NMOS element, performing a pattern making process for the substrate, for defining a PMOS element zone and a NMOS element zone, forming a lock pole insulation layer on the second silicon layer, and forming a lock pole electrode on the lock pole insulating layer.
Description
Technical field
The present invention relates to a kind of field-effect transistor, particularly a kind of CMOS (CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor) element and manufacture method thereof that has the n pass element of tensile-strained silicon layer and have the p pass element of compression strain germanium-silicon layer.
Background technology
With the downsizing of work gate component size, make mos field effect transistor (MOSFET) element can be under low operating voltage, having tend to act electric current and usefulness at a high speed of height is suitable difficulty.Therefore, many people are in the method for making great efforts to seek to improve the usefulness of burning compound semiconductor field effect transistor element.
The band structure modification of utilizing strain to cause increases the mobility of carrier, to increase the electric current of tending to act of field-effect transistor, can improve the usefulness of field effect transistor element, and this kind method has been applied in the various elements.The silicon passage of these elements is the situations that are in biaxial stretch-formed strain.
Increase mobility (the K.Ismail et al. of electronics in the situation that existing research is pointed out to utilize the silicon passage to be in biaxial stretch-formed strain, " Electron transport properties in Si/SiGe heterostructures:Measurements and device applications ", Appl.Phys.Lett.63, pp.660,1993.), and utilize the SiGe passage is in increases electric hole in the situation of biaxial compressive strain mobility (D.K.Nayaket al., " Enhancement-mode quantum-well GeSi PMOS ", IEEE Elect.Dev.Lett.12, pp.154,1991.).Yet, be difficult to reach in conjunction with the NMOSFETs (N type metal oxide semiconductor field-effect transistor) of silicon passage and CMOS process technique with PMOSFETs (P-type mos field-effect transistor) of the SiGe passage of biaxial compressive strain with biaxial stretch-formed strain.Many strained layer manufacture methods (K.Ismail et al. such as utilizing thick resilient coating or complex multilayer is arranged in transistorized manufacturing, IBM, Jul.1996, Complementary metal-oxidesemiconductor transistor logic using strained Si/SiGe heterostructure layers, U.S.Patent No.5534713.), these methods are not readily integrated in traditional CMOS processing procedure.
Therefore, have the tend to act mos field effect transistor element of electric current and high speed usefulness of height, demand seeking the road of improvement urgently at the problems referred to above in order to make.
Summary of the invention
The object of the present invention is to provide a kind of cmos element structure and manufacture method thereof with strain equilibrium structure, it utilizes and forms the strain equilibrium structure that has the n pass element of tensile-strained silicon layer and have the p pass element of compression strain germanium-silicon layer, to promote the usefulness of field effect transistor element.
Purpose of the present invention can realize by following measure:
A kind of manufacture method with cmos element of strain equilibrium structure at first provides the substrate that silicon layer (SOI) arranged on the insulating barrier.Secondly, the germanium-silicon layer of on this silicon layer, growing up, wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure.Now forms one second silicon layer on this germanium-silicon layer, this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.Then, implement patterning process to define a PMOS element region and a NMOS element region for this substrate.Moreover, on this second silicon layer, form gate insulation layer.At last, on this gate insulation layer, form a gate electrode.
Said method also be included in before or after this germanium-silicon layer of growing up by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
Said method also be included in after this germanium-silicon layer of growing up by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
The formation method of the second above-mentioned silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a cover curtain layer in the PMOS zone;
At this second silicon layer of exposed region selectivity building crystal to grow that does not cover this cover curtain layer to this two thickness; And
Remove this cover curtain layer.
Above-mentioned cover curtain layer is an one silica layer.
Above-mentioned this first thickness is the 10-30 dust.
The second above-mentioned thickness is the 100-120 dust.
Above-mentioned gate insulation layer is used chemical vapour deposition technique deposition one silica layer.
This germanium-silicon layer of above-mentioned growth is to use selectivity to build brilliant method.
The mole fraction of germanium is between 0.1 to 0.5 in the above-mentioned germanium-silicon layer.
A kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this germanium-silicon layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this second germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
For having on the above-mentioned insulating barrier germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
The formation method of germanium-silicon layer substrate is arranged on this above-mentioned insulating barrier, comprise the following steps:
The semiconductor substrate is provided;
On this semiconductor-based end, form a buried insulation layer and a silicon layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
The thickness of this above-mentioned silicon layer is less than 100 dusts.
The formation method of the second above-mentioned silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a cover curtain layer in the PMOS zone;
At this second silicon layer of exposed region selectivity building crystal to grow that does not cover this cover curtain layer to this two thickness; And
Remove this cover curtain layer.
Above-mentioned cover curtain layer is an one silica layer.
Above-mentioned this first thickness is the 10-30 dust.
The second above-mentioned thickness is the 100-120 dust.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
This second germanium-silicon layer of above-mentioned growth is to use selectivity to build brilliant method.
A kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that silicon layer is arranged on one insulating barrier is provided;
Growth one germanium-silicon layer on this silicon layer, wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this germanium-silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
Said method also be included in before or after this germanium-silicon layer of growing up by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
Said method also be included in after this germanium-silicon layer of growing up by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer
This germanium-silicon layer of above-mentioned growth is to use selectivity to build brilliant method.
The mole fraction of germanium is between 0.1 to 0.5 in the above-mentioned germanium-silicon layer.
A kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this base silicon germanium layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second germanium-silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
For having on the above-mentioned insulating barrier germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
The formation method of germanium-silicon layer substrate is arranged on the above-mentioned insulating barrier, comprise the following steps:
The semiconductor substrate is provided;
On this semiconductor-based end, form a buried insulation layer and a silicon layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
The thickness of above-mentioned silicon layer is less than 100 dusts.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
This second germanium-silicon layer of above-mentioned growth is to use selectivity to build brilliant method.
A kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms a first film layer and one second thin layer, and wherein this first film layer is to be under the biaxial stretch-formed strained situation and this second thin layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
The lattice constant of above-mentioned the first film layer is less than the lattice constant of this second thin layer.
Above-mentioned the first film layer is silicon, germanium or germanium-silicon layer
The second above-mentioned thin layer is silicon, germanium or germanium-silicon layer.
This second thin layer of above-mentioned formation is to use selectivity to build brilliant method.
Above-mentioned gate insulation layer is to use heavy kind of the one silica layer of chemical vapour deposition technique.
A kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms one first broad rete and one second thin layer, and wherein this first film layer is to be under the biaxial compressive strain situation, and this second thin layer is to be under the biaxial stretch-formed strained situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
The lattice constant of above-mentioned the first film layer is greater than the lattice constant of this second thin layer.
Above-mentioned the first film layer is silicon, germanium or germanium-silicon layer.
The second above-mentioned thin layer is silicon, germanium or germanium-silicon layer.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms a first film layer and one second thin layer, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
The lattice constant of above-mentioned the first film layer is less than the lattice constant of this second thin layer.
The lattice constant of above-mentioned the first film layer is greater than the lattice constant of this second thin layer.
Above-mentioned the first film layer is to be under the biaxial compressive strain situation.
Above-mentioned the first film layer is to be under the biaxial stretch-formed strained situation.
The second above-mentioned thin layer is to be under the biaxial compressive strain situation.
The second above-mentioned thin layer is to be under the biaxial stretch-formed strained situation.
Above-mentioned the first film layer is silicon, germanium or germanium-silicon layer.
The second above-mentioned thin layer is silicon, germanium or germanium-silicon layer
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
Purpose of the present invention also realizes by following measure:
A kind of cmos element with strain equilibrium structure comprises: the silicon layer substrate is arranged on the insulating barrier; One germanium-silicon layer is grown up in having on this insulating barrier in the silicon layer substrate, and wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure; One second silicon layer is grown up on this germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element; One gate insulation layer is formed on this second silicon layer; And a gate electrode, be formed on this gate insulation layer.
The first above-mentioned thickness is the 10-30 dust.
The second above-mentioned thickness is the 100-120 dust.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure comprises:
The germanium-silicon layer substrate is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in having on this insulating barrier in the germanium-silicon layer substrate, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this second germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulation layer is formed on this second silicon layer; And
One gate electrode is formed on this gate insulation layer.
For having on the above-mentioned insulating barrier germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
Above-mentioned this first thickness is the 10-30 dust.
Above-mentioned this second thickness is the 100-120 dust.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure comprises:
The silicon layer substrate is arranged on one insulating barrier;
One germanium-silicon layer is grown up in having on this insulating barrier in the silicon layer substrate, and wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure comprises:
The germanium-silicon layer substrate is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in having on this insulating barrier in the germanium-silicon layer substrate, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this second germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
For having on the above-mentioned insulating barrier germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure is applicable to the semiconductor substrate, comprising:
One the first film layer is grown up in this substrate, and wherein this first film layer is to be under the biaxial stretch-formed strained situation;
One second thin layer is grown up on this first film layer, and wherein this second thin layer is to be under the compression strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
The lattice constant of above-mentioned the first film layer is greater than the lattice constant of this second thin layer.
Above-mentioned the first film layer is silicon, germanium or germanium-silicon layer.
The second above-mentioned thin layer is silicon, germanium or germanium-silicon layer.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
A kind of cmos element with strain equilibrium structure is applicable to the semiconductor substrate, comprising:
One the first film layer is grown up in this substrate;
One second thin layer is grown up on this first film layer, and wherein this second thin layer and this first film layer are a strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
The lattice constant of above-mentioned the first film layer is less than the lattice constant of this second thin layer.
The lattice constant of above-mentioned the first film layer is greater than the lattice constant of this second thin layer.
Above-mentioned the first film layer is to be under the biaxial compressive strain situation.
Above-mentioned the first film layer is to be under the biaxial stretch-formed strained situation.
The second above-mentioned thin layer is to be under the biaxial compressive strain situation.
The second above-mentioned thin layer is to be under the biaxial stretch-formed strained situation.
Above-mentioned the first film layer is silicon, germanium or germanium-silicon layer.
The second above-mentioned thin layer is silicon, germanium or germanium-silicon layer.
Above-mentioned gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
The present invention has following advantage compared to existing technology:
Utilization of the present invention has the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, make semiconductor film layer be under the elongation strain situation, and the semiconductor film layer that has than the macrolattice constant is to be under the compression strain situation with less lattice constant; Thereby the transistorized usefulness of the stack layer structure of being made up of silicon layer with different lattice constants and germanium-silicon layer is increased.
Description of drawings
Fig. 1 to Fig. 8 represents the processing procedure profile according to the cmos element with strain equilibrium structure of embodiments of the invention 1.
Fig. 9 to Figure 11 represents the processing procedure profile according to the cmos element with strain equilibrium structure of embodiments of the invention 2.
Embodiment
Embodiment 1:
The invention provides a kind of cmos element structure and manufacture method thereof with strain equilibrium structure.Principle of the present invention is to use to have the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, the semiconductor film layer that has than macrolattice at relaxed state is to be under the compression strain situation, and the semiconductor film layer with less lattice constant is under the elongation strain situation, and then forms one and have strain equilibrium structure.For example, the stack layer structure that one silicon layer and a germanium-silicon layer are formed, under the interaction at relaxed state between silicon layer with different lattice constants and germanium-silicon layer, wherein germanium-silicon layer is to be under the biaxial compressive strain situation and silicon layer is under the biaxial stretch-formed strained situation.
Strain equilibrium structure can be made by the method for aftermentioned explanation, at first please refer to Fig. 1, in semiconductor substrate 10, form a buried insulation layer 11 and semi-conductor layer 12, present embodiment is then there to be silicon layer (silicon-on-insulator on the insulating barrier, SOI) wafer is an example, in order to as parent material, can utilize and implant oxygen (SIMOX) or SmartCut
Technology obtains isolating, but not as restriction.Semiconductor layer 12 generally is the silicon materials of about 200 of thickness.Buried insulation layer 11 is made of silica.Afterwards, building crystal to grow one germanium-silicon layer 14 on silicon layer 12, as shown in Figure 2, the thickness t 2 of germanium-silicon layer 14 is quite to make silicon layer 12 be under the biaxial stretch-formed strained situation with the thickness t 1 of silicon layer 12, and germanium-silicon layer 14 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Then, building crystal to grow one second silicon layer 16 on germanium-silicon layer 14, as shown in Figure 3, the thickness t 3 of second silicon layer 16 will quite make second silicon layer 16 be under the biaxial stretch-formed strained situation with the thickness t 1 of silicon layer 12 and the thickness t 2 of germanium-silicon layer 14.
In the situation of p pass element, the thickness t 3 of second silicon layer 16 must be enough thin, as 20 dusts, make and when element is opened, can not form parasitic capacitance therein, and the thickness t 2 of germanium-silicon layer 14 must be enough thick, as 100 dusts, make it can hold most movable carrier (Y.-C.Yeo et al., " Enhanced performance insub-100nm CMOSFETs using strained epitaxial silicon-germanium ", IEEEInternational Electron Device Meeting Technical Digest, pp.753-756, SanFrancisco, CA, Dec.2000.).And germanium-silicon layer 14 is under the biaxial compressive strain situation and can significantly increase transport property (the S.Kaya et al. in electric hole, " Indication of velocity overshoot instrained Si 0.8Ge 0.2 p-channel MOSFETs ", Semiconductor Science andTechnology.Vol.15, pp.573,2000.).Si
(1-x)Ge
(x)The enough high usefulness of the mole fraction x palpus of Ge in the layer 14 with enhancement p pass element, but can not too highly connect the face leakage current and prevent the strain relaxation problem with control.Si
(1-x)Ge
(x)The mole fraction x of Ge in the layer 14 can be between 0.1 to 0.5.
In the situation of n pass element, second silicon layer 16 is to use as passage, because second silicon layer 16 is under the biaxial stretch-formed strained situation and can significantly increases mobility and transport property (Rim K.et al., " Fabrication and analysis of deep submicron strained-Si n-MOSFETs ", IEEETrans, Elect.Dev., vol.47, no.7, pp.1406, Jul.2000.).Second silicon layer 16 must be enough thick in the thickness t 3 in nmos area territory, makes it can hold the most movable carrier of n pass element as 100 dusts.
About the thickness demand of second silicon layer 16 for n pass element and p pass element, for the p pass element, the thickness t 3 of second silicon layer 16 must be enough thin, as 20 dusts, to prevent forming parasitic capacitance in the PMOS element.For the n pass element, the thickness t 3 in nmos area territory must be enough thick, makes it can hold the most reversed charge of n pass element (electronics) as 100 dusts.Make second silicon layer 16 can have two thickness, can reach by following method, second silicon layer 16 of the growth thickness t 3a in the CMOS processing procedure of elder generation, then, cover a cover curtain layer 18 in the PMOS zone, as silicon oxide layer, then again at CMOS institute area exposed selectivity building crystal to grow second silicon layer 16 to thickness t 3b, as shown in Figure 4.
Afterwards, please refer to Fig. 5, remove cover curtain layer 18.Secondly, carry out the processing procedure of general cmos element again, at first as shown in Figure 6, define PMOS element region and NMOS element region by patterning process.
Then, please refer to Fig. 7, on second silicon layer 16, form gate insulation layer 22, for example use chemical vapour deposition technique silicon oxide layer deposited on second silicon layer 16.
At last, please refer to Fig. 8, on gate insulation layer 22, form gate electrode 24, carry out n type and p type ion doping (not shown) in the p-well area and the n-well area of gate electrode 24 both sides respectively again, and form clearance wall 26 at the sidewall of gate electrode 24, for example use chemical vapour deposition technique to form silicon nitride layer as clearance wall 26.
It is noted that, in above-mentioned strain equilibrium structure, must be unconstrained as much as possible at the interface of 12 of insulating barrier 11 and silicon layers so that silicon layer 12 can change its lattice constant.Make the interface of 12 of insulating barrier 11 and silicon layers be easy to as much as possible adjust so that silicon layer 12 can change its lattice constant, can be by implanted atom to interrupt or the bond of lax insulating barrier 11 and 12 interfaces of silicon layer.Said method can be in the front or rear execution of building crystal to grow germanium-silicon layer 14.
Feature of the present invention is to utilize to have the interaction of each semiconductive thin film interlayer of different lattice constants at relaxed state, make semiconductor film layer be under the elongation strain situation, and the semiconductor film layer that has than the macrolattice constant is to be under the compression strain situation with less lattice constant.Apparently, this strain equilibrium structure does not limit and uses above-mentioned three-decker, have silicon/SiGe/... .. silicon/SiGe/Si/silicon dioxide or SiGe/Si/... .. the two-layer at least above structure of SiGe/Si/SiGe/silicon dioxide can realize the present invention.Moreover applied material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
By among Fig. 8 as can be seen, have the compression strain germanium-silicon layer and can significantly increase the transport property in electric hole to increase the electric current of tending to act of p pass element, can produce the tend to act electric current of velocity of electrons effect at full speed and have tensile-strained silicon layer, and then promote the usefulness of field effect transistor element with increase n pass element.
Embodiment 2:
In the embodiment of the invention 2, the formed germanium-silicon layer that has the silicon layer of elongation strain and have compression strain is whether the interface of ignoring 12 of insulating barrier 11 among the embodiment 1 and silicon layers is easy to adjust as big as you please.
At first please refer to Fig. 9, form a buried insulation layer 61 and a germanium-silicon layer 62 in semiconductor substrate 60, present embodiment is then to have the wafer of germanium-silicon layer as parent material on the insulating barrier.The Ge content of germanium-silicon layer 62 is x1 and thickness is t6.Buried insulation layer 61 is made of silica.Present embodiment still has another to be chosen as, and as parent material, forms a buried insulation layer 91 and a silicon layer 92 with the wafer that on the insulating barrier silicon layer arranged in semiconductor substrate 90, and the thickness of silicon layer 92 is less than 100 .Buried insulation layer 91 is made of silica.Afterwards, building crystal to grow one germanium-silicon layer 94 on silicon layer 92 utilizes diffusion process that germanium is diffused into silicon layer 92 and the interface of the silicon oxide layer 91 that arrives, to change regional bond afterwards again, and the substrate (SlGe-on-insulator) of germanium-silicon layer is arranged on the formation insulating barrier, as shown in figure 10.Because germanium diffuses to the interface of silicon oxide layer 91, make the lattice constant of initial silicon layer 92, the mole fraction of the germanium of germanium-silicon layer 92 is x1, so can form the Si of similar germanium-silicon layer 62
(1-x1)Ge
(x1)Layer.
Please refer to Figure 11 afterwards, at Si
(1-x1)Ge
(x1)The layer 62 or 94 (for the purpose of simplified illustration, below only with Si
(1-x1)Ge
(x1)Layer 62 is done representative and is illustrated) last building crystal to grow 1 the 2nd Si
(1-x2)Ge
(x2)Layer 64, wherein the 2nd Si
(1-x2)Ge
(x2)Layer 64 Ge content is x2 and thickness is t7.The 2nd Si
(1-x2)Ge
(x2)The mole fraction x2 of layer 64 germanium is greater than x1, so makes the 2nd Si
(1-x2)Ge
(x2)Layer 64 is under the biaxial compressive strain situation.This strain intensity is equivalent to (pseudomorphical) Si of growth one pseudomorphic crystal on a silicon matrix layer
[1-(x2-x1)]Ge
(x2-x1)The layer, and the interface bond of this silicon matrix layer and insulating barrier (silicon oxide layer) be firm and be not be easy to as big as you please the adjustment.Yet, this 2nd Si
(1-x2)Ge
(x2)Layer 64 is under the biaxial compressive strain situation, and whether the interface bond of ignoring 62 of insulating barrier 61 and silicon layers is easy to adjust as big as you please.
Then, building crystal to grow one second silicon layer 16 on second germanium-silicon layer 64, as shown in Figure 3, this strain intensity is equivalent at a Si
(1-x1)Ge
(x1)The silicon layer of growth one pseudomorphic crystal on the hypothallus, and this Si
(1-x1)Ge
(x1)The interface bond of hypothallus and insulating barrier (silicon oxide layer) is firm and be not to be to be easy to as big as you please adjust.If Si
(1-x1)Ge
(x1)The interface bond of hypothallus and insulating barrier (silicon oxide layer) is to be easy to as big as you please wholly or in part adjust, and then the elongation strain degree of the superiors' silicon layer can reduce.Yet this second silicon layer 66 (the superiors' silicon layer) is to be under the biaxial stretch-formed strained situation, and whether the interface bond of ignoring 62 of insulating barrier 61 and silicon layers is easy to adjust as big as you please.
In sum, in the explanation of present embodiment 2, can form silicon layer with elongation strain and germanium-silicon layer, and whether the interface of ignoring 62 of buried insulation layer (silicon oxide layer) 61 and bottom silicon layers is easy to as big as you please adjust with compression strain.Because second silicon layer 66 also must have two thickness for the thickness demand of n pass element and p pass element, so, carry out every fabrication steps and program, to finish the making of cmos element with last embodiment then according to Fig. 4 to Fig. 8.Moreover applied material village material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
The present invention still proposes a kind of cmos element with strain equilibrium structure, and as shown in Figure 8, this cmos element has following each element.First element is that silicon layer substrate 10 is arranged on the insulating barrier.
Second element is that a germanium-silicon layer 14 is to use the said method building crystal to grow on silicon layer 12, and wherein silicon layer 12 is under the biaxial stretch-formed strained situation, and germanium-silicon layer 14 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Three element is one second silicon layer 16, grows up in germanium-silicon layer 141, and wherein second silicon layer 16 has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.
This cmos element still has following each element: a gate insulation layer 22 is formed on second silicon layer 16; One gate electrode 24 is formed on the gate insulation layer 22.
The present invention proposes a kind of cmos element with strain equilibrium structure in addition, and as shown in Figure 8, this cmos element has following each element.First element is that germanium-silicon layer substrate 60 is arranged on the insulating barrier, and insulating barrier 61 is ignored in this substrate 60 and whether 62 interfaces of germanium-silicon layer are easy to adjust as big as you please.
Second element is that one second germanium-silicon layer 64 is to use the said method building crystal to grow on germanium-silicon layer 62, wherein the mole fraction of the germanium of second germanium-silicon layer 64 is greater than germanium-silicon layer 62, make germanium-silicon layer 62 be under the biaxial stretch-formed strained situation and second germanium-silicon layer 64 is under the biaxial compressive strain situation, to obtain strain equilibrium structure.
Three element is one second silicon layer 66, grows up on second germanium-silicon layer 64, and wherein second silicon layer 66 has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element.
This cmos element still has following each element: a gate insulation layer 22 is formed on second silicon layer 16; One gate electrode 24 is formed on the gate insulation layer 22.
Applied material among the present invention is not limited to embodiment citation person, and it can and form method by the material of the appropriate characteristic of various tools and be replaced, and structure space of the present invention also is not limited to the size that embodiment quotes.
Though the present invention discloses as above with preferred embodiment; right its is not in order to restriction the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; change and retouching when doing, so protection scope of the present invention is as the criterion with the scope of claim.
Claims (82)
1, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that silicon layer is arranged on one insulating barrier is provided;
Growth one germanium-silicon layer on this silicon layer, wherein this silicon layer is under the biaxial stretch-formed strained situation, and this germanium-silicon layer is under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
2, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1, it is characterized in that also being included in grow up before or after this germanium-silicon layer by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
3, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1, it is characterized in that also being included in grow up after this germanium-silicon layer by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
4, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that the formation method of described second silicon layer comprises the following steps:
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a cover curtain layer in the PMOS zone;
At this second silicon layer of exposed region selectivity building crystal to grow that does not cover this cover curtain layer to this two thickness; And
Remove this cover curtain layer.
5, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 4 is characterized in that described cover curtain layer is an one silica layer.
6, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described this first thickness is the 10-30 dust.
7, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described second thickness is the 100-120 dust.
8, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that described gate insulation layer use chemical vapour deposition technique deposition one silica layer.
9, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1 is characterized in that this germanium-silicon layer of described growth is to use selectivity to build brilliant method.
10, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 1, the mole fraction that it is characterized in that germanium in the described germanium-silicon layer is between 0.1 to 0.5.
11, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this germanium-silicon layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Form one second silicon layer on this second germanium-silicon layer, wherein this second silicon layer has first district of one first thickness, and second district of one second thickness;
Implementing patterning process for this substrate is that a PMOS element region and this second district are a NMOS element region to define this first district;
On this second silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
12, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that for having on this insulating barrier the germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
13, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that having on described this insulating barrier comprising the following steps: the formation method of germanium-silicon layer substrate
The semiconductor substrate is provided;
On this semiconductor-based end, form a buried insulation layer and a silicon layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
14, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 13, the thickness that it is characterized in that described this silicon layer is less than 100 dusts.
15, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that comprising the following steps: the formation method of described second silicon layer
On this germanium-silicon layer, form this second silicon layer of this first thickness;
Cover a cover curtain layer in the PMOS zone;
At this second silicon layer of exposed region selectivity building crystal to grow that does not cover this cover curtain layer to this two thickness; And
Remove this cover curtain layer.
16, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 15 is characterized in that described cover curtain layer is an one silica layer.
17, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that described this first thickness is the 10-30 dust.
18, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that described second thickness is the 100-120 dust.
19, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
20, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 11 is characterized in that this second germanium-silicon layer of described growth is to use selectivity to build brilliant method.
21, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that silicon layer is arranged on one insulating barrier is provided;
Growth one germanium-silicon layer on this silicon layer, wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this germanium-silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
22, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 21, it is characterized in that also being included in grow up before or after this germanium-silicon layer by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
23, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 21, it is characterized in that also being included in grow up after this germanium-silicon layer by implanted atom with interrupt or lax this insulating barrier on the bond of interface between this insulating barrier of substrate of silicon layer and this silicon layer is arranged, make that the interface between this insulating barrier and this silicon layer is easy to adjust so that this silicon layer can change its lattice constant.
24, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 21 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer
25, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 21 is characterized in that this germanium-silicon layer of described growth is to use selectivity to build brilliant method.
26, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 21, the mole fraction that it is characterized in that germanium in the described germanium-silicon layer is between 0.1 to 0.5.
27, a kind of manufacture method with cmos element of strain equilibrium structure comprises the following steps:
The substrate that germanium-silicon layer is arranged on one insulating barrier is provided;
Growth one second germanium-silicon layer on this base silicon germanium layer, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be in the following of biaxial stretch-formed strained situation and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second germanium-silicon layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
28, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 27 is characterized in that for having on this insulating barrier the germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
29, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 27 is characterized in that having on the described insulating barrier comprising the following steps: the formation method of germanium-silicon layer substrate
The semiconductor substrate is provided;
On this semiconductor-based end, form a buried insulation layer and a silicon layer;
This germanium-silicon layer of growth on this silicon layer; And
Utilize diffusion process that the germanium of this germanium-silicon layer is diffused into this silicon layer and the interface of this insulating barrier that arrives, changing regional bond, and form the substrate that germanium-silicon layer is arranged on this insulating barrier.
30, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 29, the thickness that it is characterized in that described silicon layer is less than 100 dusts.
31, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 27 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
32, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 27 is characterized in that this second germanium-silicon layer of described growth is to use selectivity to build brilliant method.
33, a kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms a first film layer and one second thin layer, and wherein this first film layer is to be under the biaxial stretch-formed strained situation and this second thin layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
34, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 33 is characterized in that the lattice constant of the lattice constant of described the first film layer less than this second thin layer.
35, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 33 is characterized in that described the first film layer is silicon, germanium or germanium-silicon layer
36, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 33 is characterized in that described second thin layer is silicon, germanium or germanium-silicon layer.
37, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 33 is characterized in that this second thin layer of described formation is to use selectivity to build brilliant method.
38, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 33 is characterized in that described gate insulation layer is to use heavy kind of the one silica layer of chemical vapour deposition technique.
39, a kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms one first broad rete and one second thin layer, and wherein this first film layer is to be under the biaxial compressive strain situation, and this second thin layer is to be under the biaxial stretch-formed strained situation, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
40, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 39 is characterized in that the lattice constant of the lattice constant of described the first film layer greater than this second thin layer.
41, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 39 is characterized in that described the first film layer is silicon, germanium or germanium-silicon layer.
42, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 39 is characterized in that described second thin layer is silicon, germanium or germanium-silicon layer.
43, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 39 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
44, a kind of manufacture method with cmos element of strain equilibrium structure is applicable to the semiconductor substrate, comprises the following steps:
Continuing on this semiconductor-based end forms a first film layer and one second thin layer, to obtain strain equilibrium structure;
Implement patterning process to define a PMOS element region and a NMOS element region for this substrate;
On this second thin layer, form gate insulation layer; And
On this gate insulation layer, form a gate electrode.
45, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that the lattice constant of the lattice constant of described the first film layer less than this second thin layer.
46, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that the lattice constant of the lattice constant of described the first film layer greater than this second thin layer.
47, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described the first film layer is to be under the biaxial compressive strain situation.
48, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described the first film layer is to be under the biaxial stretch-formed strained situation.
49, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described second thin layer is to be under the biaxial compressive strain situation.
50, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described second thin layer is to be under the biaxial stretch-formed strained situation.
51, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described the first film layer is silicon, germanium or germanium-silicon layer.
52, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described second thin layer is silicon, germanium or germanium-silicon layer
53, the manufacture method with cmos element of strain equilibrium structure as claimed in claim 44 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
54, a kind of cmos element with strain equilibrium structure comprises:
The silicon layer substrate is arranged on one insulating barrier;
One germanium-silicon layer is grown up in having on this insulating barrier in the silicon layer substrate, and wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulation layer is formed on this second silicon layer; And
One gate electrode is formed on this gate insulation layer.
55, the cmos element with strain equilibrium structure as claimed in claim 54 is characterized in that described first thickness is the 10-30 dust.
56, the cmos element with strain equilibrium structure as claimed in claim 54 is characterized in that described second thickness is the 100-120 dust.
57, the cmos element with strain equilibrium structure as claimed in claim 54 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
58, a kind of cmos element with strain equilibrium structure comprises:
The germanium-silicon layer substrate is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in having on this insulating barrier in the germanium-silicon layer substrate, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
One second silicon layer is grown up on this second germanium-silicon layer, and wherein this second silicon layer has one first thickness and is applicable to a PMOS element, and one second thickness is applicable to a NMOS element;
One gate insulation layer is formed on this second silicon layer; And
One gate electrode is formed on this gate insulation layer.
59, the cmos element with strain equilibrium structure as claimed in claim 58 is characterized in that for having on this insulating barrier the germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer.
60, the cmos element with strain equilibrium structure as claimed in claim 58 is characterized in that described this first thickness is the 10-30 dust.
61, the cmos element with strain equilibrium structure as claimed in claim 58 is characterized in that described this second thickness is the 100-120 dust.
62, the cmos element with strain equilibrium structure as claimed in claim 58 is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer.
63, a kind of cmos element with strain equilibrium structure comprises:
The silicon layer substrate is arranged on one insulating barrier;
One germanium-silicon layer is grown up in having on this insulating barrier in the silicon layer substrate, and wherein this silicon layer is to be under the biaxial stretch-formed strained situation, and this germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
64,, it is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer as the described cmos element of claim 63 with strain equilibrium structure.
65, a kind of cmos element with strain equilibrium structure comprises:
The germanium-silicon layer substrate is arranged on one insulating barrier;
One second germanium-silicon layer, grow up in having on this insulating barrier in the germanium-silicon layer substrate, wherein the mole fraction of the germanium of this second germanium-silicon layer is greater than this base silicon germanium layer, make that this base silicon germanium layer is to be under the biaxial stretch-formed strained situation, and this second germanium-silicon layer is to be under the biaxial compressive strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this second germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
66,, it is characterized in that for having on this insulating barrier the germanium-silicon layer substrate is to ignore whether interface is easy to adjust as big as you please between this insulating barrier and this germanium-silicon layer as the described cmos element of claim 65 with strain equilibrium structure.
67,, it is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer as the described cmos element of claim 65 with strain equilibrium structure.
68, a kind of cmos element with strain equilibrium structure is applicable to the semiconductor substrate, comprising:
One the first film layer is grown up in this substrate, and wherein this first film layer is to be under the biaxial stretch-formed strained situation;
One second thin layer is grown up on this first film layer, and wherein this second thin layer is to be under the compression strain situation, to obtain strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
69,, it is characterized in that the lattice constant of the lattice constant of described the first film layer greater than this second thin layer as the described cmos element of claim 68 with strain equilibrium structure.
70,, it is characterized in that described the first film layer is silicon, germanium or germanium-silicon layer as the described cmos element of claim 68 with strain equilibrium structure.
71,, it is characterized in that described second thin layer is silicon, germanium or germanium-silicon layer as the described cmos element of claim 68 with strain equilibrium structure.
72,, it is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer as the described cmos element of claim 68 with strain equilibrium structure.
73, a kind of cmos element with strain equilibrium structure is applicable to the semiconductor substrate, comprising:
One the first film layer is grown up in this substrate;
One second thin layer is grown up on this first film layer, and wherein this second thin layer and this first film layer are a strain equilibrium structure;
An one PMOS element region and a NMOS element region are positioned in this substrate;
One gate insulation layer is formed on this germanium-silicon layer; And
One gate electrode is formed on this gate insulation layer.
74,, it is characterized in that the lattice constant of the lattice constant of described the first film layer less than this second thin layer as the described cmos element of claim 73 with strain equilibrium structure.
75,, it is characterized in that the lattice constant of the lattice constant of described the first film layer greater than this second thin layer as the described cmos element of claim 73 with strain equilibrium structure.
76,, it is characterized in that described the first film layer is to be under the biaxial compressive strain situation as the described cmos element of claim 73 with strain equilibrium structure.
77,, it is characterized in that described the first film layer is to be under the biaxial stretch-formed strained situation as the described cmos element of claim 73 with strain equilibrium structure.
78,, it is characterized in that described second thin layer is to be under the biaxial compressive strain situation as the described cmos element of claim 73 with strain equilibrium structure.
79,, it is characterized in that described second thin layer is to be under the biaxial stretch-formed strained situation as the described cmos element of claim 73 with strain equilibrium structure.
80,, it is characterized in that described the first film layer is silicon, germanium or germanium-silicon layer as the described cmos element of claim 73 with strain equilibrium structure.
81,, it is characterized in that described second thin layer is silicon, germanium or germanium-silicon layer as the described cmos element of claim 73 with strain equilibrium structure.
82,, it is characterized in that described gate insulation layer is to use chemical vapour deposition technique deposition one silica layer as the described cmos element of claim 73 with strain equilibrium structure.
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| CNB021316112A CN1312758C (en) | 2002-09-11 | 2002-09-11 | CMOS element with strain equilibrium structure and making method thereof |
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| CNB021316112A CN1312758C (en) | 2002-09-11 | 2002-09-11 | CMOS element with strain equilibrium structure and making method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527280B (en) * | 2008-03-06 | 2011-07-13 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN102203924A (en) * | 2008-10-30 | 2011-09-28 | 飞思卡尔半导体公司 | Optimized compressive sige channel pmos transistor with engineered ge profile and optimized silicon cap layer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| DE3542482A1 (en) * | 1985-11-30 | 1987-06-04 | Licentia Gmbh | MODULATION-Doped FIELD EFFECT TRANSISTOR |
| US5155571A (en) * | 1990-08-06 | 1992-10-13 | The Regents Of The University Of California | Complementary field effect transistors having strained superlattice structure |
| US5534713A (en) * | 1994-05-20 | 1996-07-09 | International Business Machines Corporation | Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers |
| DE19720008A1 (en) * | 1997-05-13 | 1998-11-19 | Siemens Ag | Integrated CMOS circuit arrangement and method for its production |
| EP1183727A1 (en) * | 2000-02-17 | 2002-03-06 | Koninklijke Philips Electronics N.V. | SEMICONDUCTOR DEVICE WITH AN INTEGRATED CMOS CIRCUIT WITH MOS TRANSISTORS HAVING SILICON-GERMANIUM (Si 1-x?Ge x?) GATE ELECTRODES, AND METHOD OF MANUFACTURING SAME |
-
2002
- 2002-09-11 CN CNB021316112A patent/CN1312758C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101527280B (en) * | 2008-03-06 | 2011-07-13 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN102203924A (en) * | 2008-10-30 | 2011-09-28 | 飞思卡尔半导体公司 | Optimized compressive sige channel pmos transistor with engineered ge profile and optimized silicon cap layer |
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