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CN1302403C - Optimization verification method for processor bus - Google Patents

Optimization verification method for processor bus Download PDF

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CN1302403C
CN1302403C CN 200410002889 CN200410002889A CN1302403C CN 1302403 C CN1302403 C CN 1302403C CN 200410002889 CN200410002889 CN 200410002889 CN 200410002889 A CN200410002889 A CN 200410002889A CN 1302403 C CN1302403 C CN 1302403C
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optimization
verification
method
processor
bus
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CN 200410002889
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CN1558335A (en )
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徐明椲
彭盛昌
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威盛电子股份有限公司
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Abstract

一种处理器总线最佳化验证方法。 A method for optimizing authentication processor bus. 首先,设定处理器与北桥芯片组之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率,接下来,发出读取南桥芯片组的指令,接下来,南桥芯片组输出总线中断信号以中断处理器与北桥芯片组之间的总线的联机,并启始计数器的计数值以及输出具有第一电平的最佳化验证信号。 First, to set the bus bandwidth to initiate the bus and the bus operation starting frequency and the bandwidth of the bus operation frequency of the bus between the processor and Northbridge chipset Next, Southbridge chipset issues a command to read, the next, Southbridge chipset output bus interrupt signal to interrupt the connection bus between the processor and Northbridge chipset, and starts the count value of the counter and an output of the verification signal having the best first level. 当计数器的计数值累积达一既定值,则南桥芯片组输出总线连接信号,并将上述最佳化验证信号的电平转换为第二电平。 When the count value of the counter accumulated to a certain level, the south bridge chip set output bus connection signal, and converting the optimum level verification signal is of a second level. 最后,总线根据总线连接信号以及第二电平的最佳化验证信号而重新连接处理器与北桥芯片组,并工作于另一总线操作频宽与总线操作频率。 Finally, according to the best of the bus verification signal and a second bus connection signal level reconnected processor and Northbridge chipset and the other bus operates in operational bandwidth bus operating frequency.

Description

处理器总线最佳化验证方法 The method of optimizing authentication processor bus

技术领域 FIELD

本发明涉及一种处理器总线最佳化验证方法,特别是涉及一种应用于AMD K8操作平台(plat form)的处理器总线最佳化验证方法。 The present invention relates to a processor bus optimizing authentication method, applied particularly to a platform AMD K8 (plat form) of the processor bus optimizing authentication method.

背景技术 Background technique

Legacy I/O总线结构因其低成本以及利用已建立的标准软件以及硬件标准而容易实施等特性,因此广泛使用于嵌入式系统(embedded system)中。 Legacy I / O bus architecture standard software and hardware standards for its low cost and easily using established characteristics such embodiments, it is widely used in embedded systems (embedded system) in. 然其最高操作频率仅为66MHz左右,因此,现今操作频率达500MHz以上的处理器,必须使用具有更高频宽以及操作频率的总线。 However, the highest operating frequency is only about 66MHz, and therefore, the current operation frequency of 500MHz or more processors, necessary to use a higher operating frequency and bandwidth of the bus.

闪电数据传输I/O总线(Lightning Data Transport,LDT,I/O Bus),亦称高传输I/O总线(Hyper Transport,HT,I/O Bus),满足了目前计算机网络、通讯系统以及其它嵌入式系统所需的高频宽需求,为一种具有灵活性、扩充性以及容易使用的总线架构。 Lightning transmission data I / O bus (Lightning Data Transport, LDT, I / O Bus), also known as high transmission I / O bus (Hyper Transport, HT, I / O Bus), meet the current computer networks, communications systems, and other embedded systems required for high bandwidth requirements, as a flexible, scalable and easy to use bus architecture. LDT I/O总线能够提供下一代处理器以及通讯系统所需的频宽(width),再者,LDT I/O总线还具有可调整的总线频宽以及操作速度等功能,以符合电源、空间以及成本的需求。 LDT I / O bus and a bandwidth to provide the next generation of processors (width) required for communication systems, furthermore, LDT I / O bus bandwidth bus also has adjustable features and operating speed to meet the power, space and demand costs.

传统LDT I/O总线的频宽与操作频率的最佳化必须通过执行LDT总线中断(disconnection)以及重新连接(reconnection)程序以使得LDT总线操作于预期的频宽与操作频率。 Traditional LDT I / O bus bandwidth of the operating frequency of the best performing LDT must interrupt bus (Disconnection) and reconnected (Reconnection) program so that the intended operation of the LDT bus bandwidth and operating frequency.

图1示出了传统的具有LDT总线的计算机系统架构图。 FIG 1 illustrates a conventional computer system architecture diagram with LDT bus. 如图所示,处理器10与北桥14之间具有一LDT总线12。 As illustrated, the LDT having a bus between the processor 10 and the north bridge 12 14. 在此,处理器以AMD所制造的K8CPU为例。 Here, in order to K8CPU AMD processor manufactured as an example. 而北桥14与南桥18之间具有另一总线16。 Between the south bridge 18 and the north bridge 14 and bus 16 with the other. 当要执行处理器电源管理程序以及总线最佳化程序时,位于处理器10与北桥14之间的LDT总线12必须执行中断以及重新联机的操作,上述操作需受到由南桥18所输出的信号LDTSTOP#的电平变化所控制。 When the power management program to be executed by a processor, and a bus optimization procedure, the processor 10 is located in the bus 12 and the north bridge LDT must be performed between 14 and back online operation interrupt the operation required by the signal outputted by the south bridge 18 level change LDTSTOP # is controlled. 信号LDTSTOP#的电平在正常情形为第一电平(以高电平为例),当南桥将信号LDTSTOP#的电平拉低为第二电平时(以低电平为例),此称为设定(assert)信号LDTSTOP#,而当处理器10以及北桥14皆接收到设定(assert)的信号LDTSTOP#时,则LDT总线12中断联机。 LDTSTOP # signal level in a normal situation the first level (high level, for example), when the south bridge LDTSTOP # signal level down to a second level (a low level for example), this called set (Assert) signal LDTSTOP #, when processor 10 and the north bridge 14 are received setting (Assert) signal LDTSTOP #, the LDT bus interrupt line 12. 此时,南桥18内部的计数器19开始计数,待达到一既定值后,则南桥将信号LDTSTOP#的电平再恢复为原本的第一电平(高电平),此称为解除(deassert)信号LDTSTOP#。 At this time, the internal counter 19 starts counting the south bridge 18, a predetermined value to be achieved, the South Bridge would be restored LDTSTOP # signal to its original level of a first level (high level), this is called the release ( deassert) signal LDTSTOP #. 当处理器10以及北桥14皆接收到解除(deassert)的信号LDTSTOP#时,则LDT总线12重新联机,以套用新的LDT总线操作频率以及频宽,或者是处理器的操作电压与频率。 When the processor 10 and the north bridge 14 are received by releasing (deassert) signal LDTSTOP #, the LDT bus 12 back online, to apply new LDT bus bandwidth and operating frequency, the operating voltage or frequency of the processor.

图2示出了传统LDT I/O总线的频宽与操作频率最佳化的操作流程图。 FIG 2 illustrates a conventional LDT I / optimizing the operating frequency bandwidth of an operational flowchart O bus. 首先,在系统电源启动后,由基本输入/输出系统(Basic Input/OutputSystem,BIOS)初始(initialize)LDT总线的启始设定,包括设定处理器与北桥之间的LDT总线的总线启始频宽与总线启始频率以及最佳化时的总线操作频宽与操作频率(S1)。 First, after the system power-up, start LDT bus is set by a basic input / output system (Basic Input / OutputSystem, BIOS) initial (the initialize), it includes a bus between the set start the processor and Northbridge bus LDT initiating bus bandwidth and operating frequency bandwidth bus operation (S1) when the frequency and optimized. 举例来说,在计算机系统启动后,总线启始频宽可为8位,但最佳化时可调整为16位。 For example, when the computer system starts, starting bandwidth bus may be 8 bits, but can be adjusted to optimize the time of 16-bit. 再者,总线启始频率可为200MHz,但可最佳化为400MHz、600MHz或800MHz等频率。 Further, the bus starting frequency may be 200MHz, but into the optimal like 400MHz, 600MHz or 800MHz frequency. 上述最佳化时的总线操作频宽与操作频率设定于BIOS中。 Bus bandwidth and operation frequency of the operation when set to optimize the BIOS. 接下来,BIOS依序初始处理器以及包含北桥以及南桥的芯片组的电源管理缓存器,并设定最佳化时的总线操作频宽与操作频率(S2)。 Subsequently, the BIOS, and the power management processor sequentially initial buffer comprising Northbridge chipset and south bridge and set the operating frequency bandwidth of the bus operation (S2) during optimization. 接下来,BIOS于南桥启动一自动恢复(Auto Resume)的计数器(S3),接下来,BIOS并发出读取指令至南桥的输入输出端口(PowerMana gement I/O,PMIO)偏移15th以设定(asserting)信号LDTSTOP#(S4)。 Next, BIOS South Bridge start an automatic recovery (Auto Resume) a counter (S3), Next, BIOS issues a read command to the south bridge and input and output ports (PowerMana gement I / O, PMIO) offset to 15th setting (ASSERTING) signal LDTSTOP # (S4). 在此,对信号LDTSTOP#执行设定的操作是将原本为高电平的信号LDTSTOP#转换为低电平信号。 Here, an operation setting signal is originally LDTSTOP # signal is high to a low level signal LDTSTOP #. 当南桥将信号LDTSTOP#设定为低电平时,则位于处理器以及北桥之间的LDT总线即中断连接(S5)。 When Southbridge LDTSTOP # signal is set to low level, the bus positioned between the processor and Northbridge LDT i.e. break the connection (S5).

接下来,当于步骤S3所启动的计数器的计数值达到一既定值时,则南桥将信号LDTSTOP#解除(deassert)为高电平(S6),亦即将先前设定为低电平的信号LDTSTOP#恢复为高电平。 Next, at step S3 when the count value of the counter start reaches a predetermined value, the south bridge release signal LDTSTOP # (deassert) the high level (S6), i.e., the previously set to a low level signal LDTSTOP # back to high. 当信号LDTSTOP#重新恢复为高电平后,则位于处理器以及北桥之间的LDT总线即恢复连接(S7),并根据于先前BIOS所设定的最佳化的总线操作频宽与操作频率作为重新联机后的LDT总线的操作频宽与频率,完成了LDT I/O总线的频宽与操作频率的最佳化。 When the restored LDTSTOP # signal is high, the bus positioned between the processor and Northbridge LDT is restored connection (S7), and the optimal operation of the bus bandwidth of the operating frequency to a previously set in accordance with the BIOS as the operating frequency bandwidth and the LDT bus back online, the I LDT complete optimization of the operating frequency bandwidth / O bus.

上述总线最佳化程序,必须藉由执行LDT总线的中断以及重新联机的操作才能完成调整总线的频宽与操作频率的操作。 The bus line optimization procedure, must operate bandwidth and operation frequency of adjustment by performing LDT bus and interrupt bus back online operation to complete. 然而,若LDT总线的中断以及重新联机的操作未完全执行,则总线的状态并不会改变,无法达到将总线最佳化的效果,因此导致系统效能无法有效提升。 However, if the LDT bus interrupts and back online operations are not fully implemented, the state of the bus does not change, can not reach the bus optimized effect, thus resulting in system performance can not be effectively improved.

然而,传统技术在判断总线是否已完成最佳化程序上,遭遇了许多困难。 However, conventional techniques on the bus to determine whether optimization procedure has been completed, encountered many difficulties. 以软件而言,软件工程师几乎无法确定总线是否已完成最佳化程序。 Software, the software engineer is almost impossible to determine whether the bus has completed the optimization procedure. 以硬件而言,系统工程师必须利用示波器的探针直接检测输出信号LDTSTOP#的接脚的电平变化来判断总线是否已完成最佳化程序,此检测操作相当的麻烦。 In terms of hardware, the system engineer must use the probe pin changes the level detection output signal directly LDTSTOP # oscilloscope determines whether the bus optimization procedure has been completed, this detecting operation is quite troublesome. 再者,纵使已检测到输出信号LDTSTOP#的接脚的电平被设定(assert)以及解除(deassert),若南桥18与处理器10或北桥14其中任何一者的电路联机发生断路的情形,则处理器10与北桥14无法同时接收到被设定(assert)以及解除(deassert)的信号LDTSTOP#,因此总线的频宽与操作频率仍然不会最佳化。 Further, even if the detected level of the output signal of the LDTSTOP # pin is set (Assert) and releasing (deassert), if the south bridge 18 and the north bridge 14 in which the processor 10 or any one of the circuit breaker occurs online the case, the processor 10 and the north bridge 14 can not be set simultaneously received (Assert) and releasing (deassert) signal LDTSTOP #, so bandwidth and operation frequency of the bus is still not optimized.

发明内容 SUMMARY

有鉴于此,为了解决上述问题,本发明主要目的是提供一种总线最佳化验证方法,以确认信号LDTSTOP#被设定(assert)以及解除(deassert)的程序完全被执行完毕,以避免计算机系统因为总线未被最佳化而导致整体系统效能不佳的情形。 In view of this, in order to solve the above problems, the main object of the present invention to provide a method for optimizing a bus authentication to confirm LDTSTOP # signal is set (Assert) and releasing (deassert) the procedure is completely finished, in order to avoid computer the system bus is not the best because of the situation caused by poor overall system performance.

为实现上述的目的,本发明提出一种处理器总线最佳化验证方法。 To achieve the above object, the present invention provides a method of verification optimize the processor bus. 首先,设定处理器与北桥之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率,设定该总线的最佳化操作频宽与最佳化操作频率;接下来,发出读取南桥的指令,接下来,南桥输出总线中断处理器与北桥芯片组之间的总线的连线,并启始计数器的计数值以及输出具有第一电平的最佳化验证信号。 First, to set the bus between the processor and Northbridge bus bandwidth to initiate the bus and the bus operation starting frequency and the bandwidth of the bus operating frequency, bandwidth and set an optimum operation of the optimum operating frequency of the bus; Next, Southbridge issues an instruction to read, the next, the south bridge output bus disconnect bus between the processor and Northbridge chipset, and starts the count value of the counter and an output having a first level of the best validation signal. 当计数器的计数值累积达一既定值,则南桥输出总线连接信号,并将上述最佳化验证信号的电平转换为第二电平。 When the count value of the counter accumulated to a certain level, the south bridge output bus connection signal, and converting the optimum level verification signal is of a second level. 最后,总线根据总线连接信号以及第二电平的最佳化验证信号而重新连接处理器与北桥,并工作于最佳化总线操作频宽与最佳化总线操作频率。 Finally, according to the best of the bus verification signal and a second bus connection signal level processor and Northbridge reconnected, and work in the best operational bandwidth of the bus and the bus operation frequency optimization.

为使本发明的上述目的、特征和优点能更明显易懂,下文特举一较佳实施例,并结合附图详细说明如下。 For the above objects, features and advantages of the present invention can be more fully understood by referring cite a preferred embodiment, the following detailed description in conjunction with the accompanying drawings.

附图说明 BRIEF DESCRIPTION

图1示出了传统具有LDT总线的计算机系统架构图。 Figure 1 shows a system architecture diagram of a conventional computer bus having LDT.

图2示出了传统LDT I/O总线的频宽与操作频率最佳化的操作流程图。 FIG 2 illustrates a conventional LDT I / optimizing the operating frequency bandwidth of an operational flowchart O bus.

图3示出了根据本发明实施例所述的具有LDT总线的计算机系统架构图。 FIG 3 illustrates a computer system architecture diagram of the embodiment having a bus LDT embodiment of the present invention.

图4示出了根据本发明实施例所述的电平检测电路的电路图。 Figure 4 shows a circuit diagram of the level detecting circuit according to the embodiment of the present invention.

图5示出了根据本发明实施例所述的处理器总线最佳化验证方法的操作流程图。 FIG 5 shows a flowchart of the operation of the verification method of the preferred embodiment of the processor bus in accordance with embodiments of the present invention.

符号说明10~处理器12~LDT总线14~北桥16~总线18~南桥21~电平检测电路LDTSTOP#~信号具体实施方式参阅图3,图3示出了根据本发明实施例所述的具有LDT总线的计算机系统架构图。 REFERENCE SIGNS LIST 10 ~ 12 ~ LDT processor bus 16 to the bus 14 through the north bridge 18 to the south bridge 21 to the level detection circuit signal LDTSTOP # ~ DETAILED DESCRIPTION Referring to FIG. 3, FIG. 3 shows an embodiment in accordance with the embodiment of the present invention. computer system architecture with LDT bus. 如图所示,处理器20与北桥24之间具有一LDT总线22,或称HT总线。 As illustrated, the LDT having a processor bus 20 and the north bridge 22 between 24, also known as HT bus. 在此,处理器20是以AMD所制造的K8CPU为例。 In this case, the processor 20 K8CPU AMD is manufactured as an example. 而北桥24与南桥28之间具有另一总线26。 Another bus 26 having a north bridge 24 and the south bridge 28 between. 当要执行总线最佳化程序时,位于处理器20与北桥24之间的LDT总线22必须执行中断以及重新联机的操作,上述操作受到南桥28所输出的信号LDTSTOP#的电平变化所控制。 When the optimization procedure is to be performed bus positioned between the processor 20 and the north bridge 24 LDT must perform an interrupt bus 22, and back online operation, the above-described operation by signal level changes LDTSTOP # south bridge 28 outputs the control . 信号LDTSTOP#的电平在正常情形为第一电平(以高电平为例),当南桥29将信号LDTSTOP#的电平拉低为第二电平时(以低电平为例),此称为设定(assert)信号LDTSTOP#,则LDT总线22中断联机。 LDTSTOP # signal level in a normal situation the first level (high level, for example), when the south bridge 29 LDTSTOP # signal level down to a second level (a low level for example), this setting is called (Assert) signal LDTSTOP #, the LDT bus interrupt line 22. 此时,南桥28内部的计数器29开始计数,待达到一既定值后,则南桥将信号LDTSTOP#的电平再恢复为原本的第一电平(高电平),此称为解除(deassert)信号LDTSTOP#,则LDT总线22重新联机,以套用新的LDT总线操作频率以及频宽。 At this time, the south bridge 28 inside the counter 29 starts counting until reaches a predetermined value, the south bridge LDTSTOP # signal be restored to its original level of a first level (high level), this is called the release ( deassert) signal LDTSTOP #, the LDT bus 22 back online, to apply the new frequency of operation and the LDT bus bandwidth.

再者,根据本发明实施例所述的总线最佳化验证方法,增设一信号电平检测电路21来判断信号LDTSTOP#是否已执行设定(assert)以及解除(deassert)的程序。 Further, according to the bus of the preferred embodiment of the verification method of the embodiment of the present invention, the addition of a signal level detecting circuit 21 determines whether to set the signal LDTSTOP # (Assert) and releasing (deassert) the program is executed.

图4示出了根据本发明实施例所述的电平检测电路21的电路图。 FIG 4 shows a circuit diagram of the level detecting circuit according to embodiments of the present invention 21. 根据本发明实施例所述的电平检测电路21包括一触发器40,以及耦接于触发器40的D端子的或逻辑门42。 The level detection circuit 21 of the embodiment of the present invention comprises a flip-flop 40, and an OR logic gate coupled to the D terminal of flip-flop 40 42. 在此电平检测电路21中,系统在或逻辑门42的输入端42A输入逻辑电平“1”的信号,此时于触发器40的Q端子输出逻辑电平“1”的信号LSTSTOP_STATUS。 The level detection circuit 21, the signal input system 42 of the OR logic gate 42A input terminal of a logic level "1", this time in the flip-flop output Q terminal 40 logic level "1" signal LSTSTOP_STATUS. 当触发器40的RST端子所接收的信号LDTSTOP#由低电平上升到高电平时,则触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平清除为“0”。 When the RST terminal of the flipflop 40 receiving a signal LDTSTOP # rises from low to high, then the signal Q terminal output of flip-flop LSTSTOP_STATUS 40 Clear logic level "0." 由于信号LDTSTOP#的电平于正常情况下系保持于高电平,当信号LDTSTOP#被设定(assert)为低电平,再被解除(deassert)为高电平时,触发器40的Q端子所输出的信号LSTSTOP_STATUS的逻辑电平才会为“0”。 Due LDTSTOP # signal level based on normally held at a high level, when the signal is set LDTSTOP # (Assert) is low, and then is released (deassert) is high, Q terminal of the flip-flop 40 LSTSTOP_STATUS logic level signal will be output as "0." 因此,藉由检测触发器40的Q端子所输出的,即可判断信号LDTSTOP#完成执行设定(assert)以及解除(deassert)的程序。 Thus, by detecting the Q terminal of flip-flop 40 the output signal is determined to complete the setting is performed LDTSTOP # (Assert) and releasing (deassert) program.

再者,关于电平检测电路21所设置的位置可置于南桥20的输出端,以及处理器20和北桥24接收信号LDTSTOP#的输入端,如图3所示。 Furthermore, regarding the position of the level detecting circuit 21 may set the output of the south bridge 20 is disposed, and an input processor 20 and the north bridge 24 receives the signal LDTSTOP #, as shown in FIG. 另外,根据本发明实施例图4中所示的电平检测电路的电路结构仅为一较佳实施例,然而,检测信号LSTSTOP_STATUS逻辑电平的操作同样也可利用其它电路来实现,并不限定于图4中所示的电平检测电路结构。 Further, according to the embodiment of the present invention, the circuit configuration of FIG embodiment level detection circuit 4 is only shown in a preferred embodiment, however, the logic level of the detection signal LSTSTOP_STATUS operation likewise be implemented using other circuitry, not limited level detecting circuit configuration shown in FIG. 4 in.

图5示出了根据本发明实施例所述的处理器总线最佳化验证方法的操作流程图。 FIG 5 shows a flowchart of the operation of the verification method of the preferred embodiment of the processor bus in accordance with embodiments of the present invention. 根据本发明实施例,首先,在系统电源启动后,由基本输入/输出系统(Basic Input/Output System,BIOS)初始(initialize)LDT总线的启始设定,包括设定处理器与北桥之间的LDT总线的总线启始频宽与总线启始频率以及最佳化时的总线操作频宽与操作频率(S21)。 According to an embodiment of the present invention, first, after the system power-up, by a basic input / output system (Basic Input / Output System, BIOS) Initial (initialize) LDT bus start setting, between the setting comprising a processor and Northbridge LDT start bus bandwidth of the bus and the bus and the bus operation starting frequency of the operating frequency bandwidth (S21) when optimized. 举例来说,总线启始频宽可为8位,但最佳化时可调整为16位。 For example, the bus bandwidth can initiate eight, but may be adjusted to optimize the time of 16-bit. 再者,总线启始频率可为200MHz,但可最佳化为400MHz、600MHz或800MHz等频率。 Further, the bus starting frequency may be 200MHz, but into the optimal like 400MHz, 600MHz or 800MHz frequency. 上述最佳化时的总线操作频宽与操作频率系设定于BIOS中。 The operating frequency bandwidth bus operation based upon the above-described optimization settings in the BIOS. 接下来,由BIOS依序初始处理器以及包含北桥以及南桥的芯片组的电源管理缓存器,以处理相关的电源设定(S22)。 Next, an initial sequence by the BIOS and a power management processor cache comprises Northbridge chipset and south bridge power settings related to the processing (S22). 接下来,BIOS将处理器与北桥之间的LDT总线的总线最佳化的操作频宽与操作频率设定于缓存器中(S23),例如,将总线最佳化操作频宽设定为16位、将总线最佳化操作频率设定为800MHz。 Next, the BIOS optimizing bus bandwidth and operation frequency of operation between the processor bus and the LDT Northbridge is set in the buffer (S23), e.g., the bus bandwidth is set to the optimum operation 16 bits, the bus frequency is set to the optimum operation 800MHz. 接下来,BIOS于南桥启动一自动恢复(Auto Resume)的计数器(S24)。 Next, BIOS South Bridge start an automatic recovery (Auto Resume) of the counter (S24). 当自动恢复(Auto Resume)的计数器的计数值累计到一既定值时,则解除(deassert)信号LDTSTOP#。 When the count value is automatically restored (Auto Resume) counter accumulated to a predetermined value, it is released (deassert) signal LDTSTOP #.

接下来,在如图4所示的电平检测电路21的逻辑门42的输入端42A输入逻辑电平“1”的信号,使得触发器40的Q端子输出逻辑电平“1”的信号LSTSTOP_STATUS(S25)。 Next, the logic gate input level detection circuit shown in FIG. 4 Fig. 21 42 42A input logic level "1" signal terminal, so that the Q terminal output of the flip-flop 40 is logic level "1" signal LSTSTOP_STATUS (S25). 接下来,BIOS发出读取指令至南桥的输入输出端口(Power Management I/O,PMIO)偏移15th以设定(asserting)信号LDTSTOP#(S26)。 Next, BIOS issues a read command to the south bridge input and output ports (Power Management I / O, PMIO) 15th to set the offset (ASSERTING) signal LDTSTOP # (S26). 在此,对信号LDTSTOP#执行设定的操作是将原本为高电平的信号LDTSTOP#转换为低电平信号。 Here, an operation setting signal is originally LDTSTOP # signal is high to a low level signal LDTSTOP #. 当南桥将信号LDTSTOP#设定为低电平时,则位于处理器以及北桥之间的LDT总线即中断连接(S27)。 When Southbridge LDTSTOP # signal is set to low level, the bus positioned between the processor and Northbridge LDT i.e. break the connection (S27).

接下来,当在步骤S24所启动的计数器的计数值达到一既定值时,则南桥将信号LDTSTOP#解除(deassert)为高电平(S28),亦即将先前设定为低电平的信号LDTSTOP#恢复为高电平。 Next, when the count value of the counter at the start of step S24 reaches a predetermined value, the south bridge release signal LDTSTOP # (deassert) the high level (S28), i.e., the previously set to a low level signal LDTSTOP # back to high. 当信号LDTSTOP#解除(deassert)为高电平后,由于信号LDTSTOP#耦接于电平检测电路21的的RST端子,因此触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平清除为“0”(S29)。 When the release signal LDTSTOP # (deassert) after a high level, since the signal LDTSTOP # is coupled to the RST terminal of the level detection circuit 21, the signal logic level LSTSTOP_STATUS clear flip-flop output Q terminal 40 is "0 "(S29). 接下来,检测触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平(S30),以判断信号LDTSTOP#是否已完成设定(assert)以及解除(deassert)的完整程序。 Next, the logic level of the signal detected LSTSTOP_STATUS Q terminal output of the flip-flop 40 (S30), to determine whether the setting has been completed LDTSTOP # signal (Assert) and releasing (deassert) the complete program. 接下来,处理器判断触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平是否为“0”(S31),若不为“0”,则回到步骤S30,继续检测触发器40的Q端子输出的信号LSTSTOP_STATUS的逻辑电平。 Next, the signal processor determines LSTSTOP_STATUS logic level Q output terminal of flip-flop 40 whether or not "0" (S31), if it is "0", the process returns to step S30, the Q terminal of flip-flop 40 continues to detect the LSTSTOP_STATUS logic level signal output. 若于步骤S31的判断出LSTSTOP_STATUS的逻辑电平为“0”,则位于处理器以及北桥之间的LDT总线即恢复连接,并根据于先前BIOS所设定的最佳化的总线操作频宽与操作频率作为重新联机后的LDT总线的操作频宽与频率(S32),完成了LDT I/O总线的频宽与操作频率的最佳化。 If the logic level LSTSTOP_STATUS determination in step S31 is "0", the bus positioned between the processor and Northbridge LDT connection is restored, and according to the previously set BIOS optimizing bus bandwidth and operation operating frequency as an operation frequency bandwidth and the back online LDT bus (S32), the I LDT complete optimization of the operating frequency bandwidth / O bus.

根据本发明实施例所述的处理器总线最佳化验证方法,藉由检测设置于南桥的电平检测电路21所输出的LSTSTOP_STATUS的逻辑电平即可判断信号LDTSTOP#是否已完成设定(assert)以及解除(deassert)的完整程序。 The processor bus optimization verification method described in the embodiment of the present invention, LSTSTOP_STATUS logic levels provided by detecting the south bridge output level detection circuit 21 can determine whether the setting has been completed LDTSTOP # signal ( assert) and release (deassert) the complete program. 再者,若在北桥或者处理器于接收信号LDTSTOP#的输入端处设置电平检测电路,还可确保完成设定(assert)以及解除(deassert)完整程序的信号LDTSTOP#正常连接至北桥或者处理器,确认位于北桥以及处理器之间的总线能够遵循信号LDTSTOP#电平的变化确实完成中断联机以及恢复联机的操作。 Further, if the level detection circuit is provided at the input of the received signal in LDTSTOP # Northbridge or processor, may ensure the completion of setting (Assert) and releasing (deassert) the complete program LDTSTOP # signal coupled to the Northbridge or normal processing It is confirmed between the North Bridge bus and a processor able to follow the line, and indeed the recovery operation completion interrupt line LDTSTOP # signal changes level.

本发明虽以较佳实施例披露如上,然其并非用以限定本发明的范围,本领域的技术人员在不脱离本发明的精神和范围的前提下,可做若干的更动与润饰,因此本发明的保护范围以本发明的权利要求为准。 While the invention disclosed above with reference to preferred embodiments, they are not intended to limit the scope of the present invention, those skilled in the art without departing from the spirit and scope of the present invention, a number of alterations and modifications do, so the scope of the present invention is subject to the claims of the present invention.

Claims (7)

1.一种处理器总线最佳化验证方法,适用于一处理器、一北桥芯片组、耦接于该处理器与北桥芯片组之间的总线以及耦接于该北桥芯片组的南桥芯片组,包括下列步骤:设定该处理器与北桥芯片组之间总线的总线启始频宽与总线启始频率以及总线操作频宽与总线操作频率;设定该总线的最佳化操作频宽与最佳化操作频率;发出读取该南桥芯片组的指令;该南桥芯片组接收到该指令后,输出一总线中断信号以中断该处理器与北桥芯片组之间的总线的连线,并启始一计数器的计数值,以及输出具有一第一电平的一最佳化验证信号;当该计数器的计数值累积达一既定值,则该南桥芯片组输出一总线连接信号,并将该最佳化验证信号的电平转换为一第二电平;以及该总线根据该总线连接信号以及具有第二电平的最佳化验证信号而重新连接该处理器与北桥芯 An authentication method for optimizing processor bus for a processor, a Northbridge chip set, a bus coupled between the processor and Northbridge chipset and coupled to the Northbridge chipset southbridge group, comprising the steps of: setting start bus bandwidth of the bus and the bus and the bus operation starting frequency of an operating frequency bandwidth of the bus between the processor and Northbridge chip set; sets the optimum operation of the bus bandwidth and optimizing the operating frequency; read command is issued to the Southbridge chipset; the south bridge chip set after receiving the instruction, outputs an interrupt signal to the bus interrupt bus between the processor and Northbridge chipset connection and a start count value of the counter start, and optimizing a verification signal having a first output level; when the count value of the counter accumulated to a predetermined value, the south bridge chip set outputs a signal bus connection, and optimizing the level conversion verification signal is a second level; and a bus connecting the processor and Northbridge again based on the core and optimized bus connection signal verification signal having a second level 组,并工作于最佳化总线操作频宽与最佳化总线操作频率。 Group, and work in the best operational bandwidth of the bus and the bus operation frequency optimization.
2.如权利要求1所述的处理器总线最佳化验证方法,其中该总线中断信号以及总线连接信号用于设定以及解除由该南桥芯片组的一输出端所输出的信号。 The processor bus optimizing the verification method as claimed in claim 1, wherein the interrupt signal bus and a bus connection signal for setting and releasing a signal from the output terminal of the Southbridge chipset output.
3.如权利要求1所述的处理器总线最佳化验证方法,其中该总线中断信号以及总线连接信号是由同一输出端所输出。 Optimizing processor bus verification method according to claim 1, wherein the interrupt signal bus and a bus connection signal is outputted from the same output terminal.
4.如权利要求1所述的处理器总线最佳化验证方法,其中该最佳化验证信号是由一电平检测电路所输出。 The processor bus optimizing the verification method as claimed in claim 1, wherein the verification signal is optimized by an output level detection circuit.
5.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路包括一触发器以及耦接于该触发器的一或逻辑门,当该南桥芯片组输出该总线中断信号时,则该触发器输出具有第一电平的最佳化验证信号,当该南桥芯片组输出该总线连接信号时,则该触发器输出具有第二电平的最佳化验证信号。 5. The optimization processor bus verification method according to claim 4, wherein the level detection circuit comprises a logic gate or a flip-flop and coupled to the trigger, when the output of the bus Southbridge chipset when the interrupt signal, the flip-flop output signal having the best of the first level verification, the south bridge chip set when the bus connection signal is output, the flip-flop output signal having the best second level of verification of .
6.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路设置于该南桥芯片组的输出端。 Optimizing processor bus verification method as claimed in claim 4, wherein the level detecting circuit provided in the output terminal Southbridge chipset.
7.如权利要求4所述的处理器总线最佳化验证方法,其中该电平检测电路设置于该北桥芯片组或处理器的输入端。 7. The processor bus optimizing authentication method according to claim 4, wherein the level detecting circuit provided in the Northbridge chipset or processor input.
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